CN108268717A - A kind of novel grid induced drain leakage current model - Google Patents
A kind of novel grid induced drain leakage current model Download PDFInfo
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- CN108268717A CN108268717A CN201810049423.0A CN201810049423A CN108268717A CN 108268717 A CN108268717 A CN 108268717A CN 201810049423 A CN201810049423 A CN 201810049423A CN 108268717 A CN108268717 A CN 108268717A
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- 238000004088 simulation Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 238000005259 measurement Methods 0.000 description 1
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
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Abstract
The invention discloses a kind of novel grid induced drain leakage current model, the expression formula of the current model is：
Description
Technical field
The present invention relates to a kind of current model, more particularly to a kind of novel grid induced drain leakage current model.
Background technology
In MOSFET element, when drain-to-gate voltage Vdg is very big at grid leak crossover region, electronics in crossover region near interface silicon
Band-to-band-tunneling occurs between valence band and conduction band and forms electric current, which is GIDL tunnelling currents.With the grid oxygen of MOS device
Change layer is more and more thinner, and GIDL tunnelling currents sharply increase.
Research shows that the leakage current for causing quiescent dissipation in MOSFET mainly has：Subthreshold leakage current, grid of the source to leakage
Leakage current, grid induced drain leakage GIDL (Gate-Induced-Drain-Leakage) electricity for being happened at grid leak crossover region
Stream, as shown in figure figure below.In these leakage currents, when device is in OFF state or is waited in circuit, GIDL
Electric current is occupied an leading position in leakage current, larger to the reliability effect of MOSFET.
In the prior art, the expression formula of grid induced drain leakage current model is as follows：
Wherein, f (L)=P3O, Vdg is drain-to-gate voltage, and P1, P2 are the model parameter suitable for all device sizes, wherein P1
For the saturation GIDL electric currents of unit voltage, in the range of [0, infinitely great], representative value 3e-5A/V, P2 are the threshold of GIDL electric currents
Threshold voltage, in the range of [minus infinity, positive infinity], the activation energy of representative value 0.5V, P3O for GIDL electric currents, range
For [0, infinitely great], representative value 30V.
However, the simulation value of the grid induced drain leakage current model of the prior art deviates in higher drain-to-gate voltage Vdg
Measured value is notable, is unfavorable for applying.
Fig. 1 is the I of long short channel under certain old technologyGIDLComparison diagram.It can be seen from Fig. 1 that under certain old technology, in identical drain-gate electricity
It presses under Vdg, when the grid induced drain leakage current (small fork line) of short channel (L=0.55um) is than long raceway groove (L=20um)
Grid induced drain leakage current (box line) is slightly larger.
Fig. 2 is the I of long short channel under certain new processGIDLComparison diagram.It can be seen from Fig. 2 that under certain new process, in identical drain-gate electricity
It presses under Vdg, when the grid induced drain leakage current (small fork line) of short channel (L=0.55um) is than long raceway groove (L=20um)
Grid induced drain leakage current (box line) is much greater.
Invention content
To overcome above-mentioned the shortcomings of the prior art, a kind of novel grid induced drain that is designed to provide of the present invention is let out
Leak electricity flow model, to realize a kind of higher grid induced drain leakage current model of accuracy.
In view of the above and other objects, the present invention proposes a kind of novel grid induced drain leakage current model, feature exists
In the expression formula of the current model is：
Wherein, f (L)=P3O, Vdg is drain-to-gate voltage, and P1 is the saturation GIDL electric currents of unit voltage, and P2 is GIDL electric currents
Threshold voltage, P3O be GIDL electric currents activation energy.
Further, f (L)=P3O-P3L/L。
Further, the value range of P3O be [0,100], unit V.
Further, P3LValue range be [0,10-4], unit V*m.
Further,
Wherein, activation energy of the P3O for GIDL electric currents, P3N1Energy short channel correction value, P3N are activated for GIDL2It is activated for GIDL
The channel length deviation ratio of energy short channel correction term, P3N3The channel length coefficient of energy short channel correction term is activated for GIDL,
P3N4The channel length index of energy short channel correction term is activated for GIDL, L is the channel length of MOS transistor.
Further, the value range of P3O be [0,100], unit V.
Further, P3N1Value range for [0,100], unit V.
Further, P3N2Value range for [- 20,20], unit
Further, P3N3Value range be [- 109,0]。
Further, P3N4Value range be [0,4].
Compared with prior art, the present invention is realized and is obtained by establishing a kind of novel grid induced drain leakage current model
Obtain the purpose of accurate grid induced drain leakage current.
Description of the drawings
Fig. 1 is the I of long short channel under certain old technologyGIDLComparison diagram；
Fig. 2 is the I of long short channel under certain new processGIDLComparison diagram；
Fig. 3 is the simulation comparison figure of the present invention and background technology.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand the further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, the various details in this specification also can be based on different viewpoints with application, without departing substantially from
Various modifications and change are carried out under the spirit of the present invention.
In the present invention, the expression formula of the grid induced drain current model remains as：
In a preferred embodiment, f (L)=P3O-P3L/ L, wherein, P3LEnergy short channel correction factor, L are activated for GIDL
Channel length for MOS transistor.Wherein, the value range of P3O be [0,100], unit V, P3LValue range for [0,
10-4], unit V*m.
And in a further preferred embodiment,
Wherein, the value range of P3O be [0,100], unit V, P3N1Energy short channel correction value, P3N are activated for GIDL2For
The channel length deviation ratio of GIDL activation energy short channel correction terms, P3N3The raceway groove that energy short channel correction term is activated for GIDL is long
Spend coefficient, P3N4The channel length index of energy short channel correction term is activated for GIDL, L is the channel length of MOS transistor, wherein
P3N1Value range for [0,100], unit V, P3N2Value range for [- 20,20], unitP3N3Value model
Enclose is [- 109, 0], no unit, P3N4Value range for [0,4], no unit.
Fig. 3 is the simulation comparison figure of the present invention and background technology.It can be seen from Fig. 3 that long channel device (L=20um), it is existing
There are grid induced drain leakage current (dotted line, in figure from top to bottom Article 4 filament) simulation value and the invention of the background model of technology
Model grid induced drain leakage current (solid line, in figure from top to bottom Article 3 filament) simulation value it is suitable, the two and actual measurement
It is suitable to be worth (box line) degree of approximation；To short channel device (L=0.55um), compared with measured value (box line), invention
Grid induced drain leakage current (solid line, in the figure from top to bottom first filament) simulation value of model is compared with the background mould of the prior art
Grid induced drain leakage current (dotted line, in figure from top to bottom Article 2 filament) simulation value of type is in higher drain-to-gate voltage Vdg
Closer to measured value, and to deviate measured value in higher drain-to-gate voltage Vdg notable for the simulation value of the background model of the prior art, no
Conducive to application.
As it can be seen that it is more accurate to realize acquisition by establishing a kind of novel grid induced drain leakage current model by the present invention
Grid induced drain leakage current purpose.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Field technology personnel can modify above-described embodiment and changed under the spirit and scope without prejudice to the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (10)
1. a kind of novel grid induced drain leakage current model, which is characterized in that the expression formula of the current model is：
Wherein, f (L)=P3O, Vdg is drain-to-gate voltage, and P1 is the saturation GIDL electric currents of unit voltage, and P2 is the threshold of GIDL electric currents
Threshold voltage, P3O are the activation energy of GIDL electric currents.
2. a kind of novel grid induced drain leakage current model as described in claim 1, it is characterised in that：
F (L)=P3O-P3L/L
Activation energy of the wherein P3O for GIDL electric currents, P3LEnergy short channel correction factor is activated for GIDL, L is the raceway groove of MOS transistor
Length.
3. a kind of novel grid induced drain leakage current model as claimed in claim 2, it is characterised in that：The value model of P3O
It encloses for [0,100], unit V.
4. a kind of novel grid induced drain leakage current model as claimed in claim 2, it is characterised in that：P3LValue range
It is [0,10-4], unit V*m.
5. a kind of novel grid induced drain leakage current model as described in claim 1, it is characterised in that：
Wherein, activation energy of the P3O for GIDL electric currents, P3N1Energy short channel correction value, P3N are activated for GIDL2It can be short for GIDL activation
The channel length deviation ratio of raceway groove correction term, P3N3The channel length coefficient of energy short channel correction term, P3N are activated for GIDL4For
The channel length index of GIDL activation energy short channel correction terms, L is the channel length of MOS transistor.
6. a kind of novel grid induced drain leakage current model as claimed in claim 5, it is characterised in that：The value model of P3O
It encloses for [0,100], unit V.
7. a kind of novel grid induced drain leakage current model as claimed in claim 5, it is characterised in that：P3N1Value model
It encloses for [0,100], unit V.
8. a kind of novel grid induced drain leakage current model as claimed in claim 5, it is characterised in that：P3N2Value model
It encloses for [- 20,20], unit
9. a kind of novel grid induced drain leakage current model as claimed in claim 5, it is characterised in that：P3N3Value model
Enclose is [- 109,0]。
10. a kind of novel grid induced drain leakage current model as claimed in claim 5, it is characterised in that：P3N4Value model
It encloses for [0,4].
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288943B1 (en) * | 2000-07-12 | 2001-09-11 | Taiwan Semiconductor Manufacturing Corporation | Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate |
| KR20080020417A (en) * | 2006-08-31 | 2008-03-05 | 동부일렉트로닉스 주식회사 | SPICE Modeling Method of CMS |
| CN101762781A (en) * | 2010-01-08 | 2010-06-30 | 西安西电科大射频集成电路有限责任公司 | Test circuit for predicting static discharge failure of integrated circuit and prediction method thereof |
| CN102543761A (en) * | 2012-02-28 | 2012-07-04 | 上海华力微电子有限公司 | Method for reducing grid induced drain leakage of semiconductor device, and MOS device manufacturing method |
| CN103035706A (en) * | 2013-01-04 | 2013-04-10 | 电子科技大学 | Vertical gallium nitride based nitride heterojunction field effect transistor with polarized doped current barrier layer |
| CN105373660A (en) * | 2015-11-12 | 2016-03-02 | 成都嘉石科技有限公司 | Equivalent circuit-based transistor reliability representation method |
| CN106024631A (en) * | 2016-05-23 | 2016-10-12 | 武汉新芯集成电路制造有限公司 | Method for lowering gate induced drain leakage current of MOS transistor |
-
2018
- 2018-01-18 CN CN201810049423.0A patent/CN108268717B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288943B1 (en) * | 2000-07-12 | 2001-09-11 | Taiwan Semiconductor Manufacturing Corporation | Method for programming and reading 2-bit p-channel ETOX-cells with non-connecting HSG islands as floating gate |
| KR20080020417A (en) * | 2006-08-31 | 2008-03-05 | 동부일렉트로닉스 주식회사 | SPICE Modeling Method of CMS |
| CN101762781A (en) * | 2010-01-08 | 2010-06-30 | 西安西电科大射频集成电路有限责任公司 | Test circuit for predicting static discharge failure of integrated circuit and prediction method thereof |
| CN102543761A (en) * | 2012-02-28 | 2012-07-04 | 上海华力微电子有限公司 | Method for reducing grid induced drain leakage of semiconductor device, and MOS device manufacturing method |
| CN103035706A (en) * | 2013-01-04 | 2013-04-10 | 电子科技大学 | Vertical gallium nitride based nitride heterojunction field effect transistor with polarized doped current barrier layer |
| CN105373660A (en) * | 2015-11-12 | 2016-03-02 | 成都嘉石科技有限公司 | Equivalent circuit-based transistor reliability representation method |
| CN106024631A (en) * | 2016-05-23 | 2016-10-12 | 武汉新芯集成电路制造有限公司 | Method for lowering gate induced drain leakage current of MOS transistor |
Non-Patent Citations (4)
| Title |
|---|
| N. MAOUHOUB 等: "Characterization of defect density created by stress in the gate to drain overlap region using GIDL current model in n-channel MOSFET", 《JOURNAL OF COMPUTATIONAL ELECTRONICS》 * |
| OLEG SEMENOV 等: "Impact of Gate Induced Drain Leakage on Overall", 《IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING》 * |
| 陈海峰: "超深亚微米CMOS器件GIDL电流及其可靠性研究", 《中国博士学位论文全文数据库 信息科技辑》 * |
| 陈静华 等: "CMOS电路漏电流模型及优化方法", 《第三届中国测试学术会议论文集》 * |
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