CN103325790B - Read-only memory and manufacture method thereof - Google Patents
Read-only memory and manufacture method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000002019 doping agent Substances 0.000 claims abstract description 56
- 239000007943 implant Substances 0.000 claims description 8
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- 238000013461 design Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- -1 carbon ion Chemical class 0.000 description 2
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- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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Abstract
The invention relates to a kind of read-only memory and manufacture method thereof.This read-only memory, comprises substrate, source area and drain region, charge storing structure, grid and local extreme doped region.Above-mentioned source area and drain region are arranged in substrate, in the substrate of charge storing structure between source area and drain region, grid is then arranged on charge storing structure.Local extreme doped region is in the substrate between source area and drain region, and described local extreme doped region comprises a low doping concentration district and at least one high-dopant concentration district.High-dopant concentration district one of to be arranged in source area and drain region between low doping concentration district, and wherein the doping content in high-dopant concentration district is higher than the doping content in low doping concentration district more than 3 times.Present invention also offers a kind of manufacture method of read-only memory.
Description
Technical field
The present invention relates to a kind of read-only memory, particularly relate to a kind of suppression second bit effect (2
ndbiteffect) read-only memory and manufacture method thereof.
Background technology
Having charge storing structure as the read-only memory (readonlymemory) of data storage kenel is non-volatility memory common at present.The structure of a read-only memory comprises one and is stored the structure sheaf even catching charge characteristic, as ONO (oxide-nitride-oxide) layer.As adopted the charge trapping structure of localization to store electric charge, the electric charge bit that two can be had in each memory cell to be separated can be allowed, and form the memory body that so-called single memory cell two bit (2bits/cell) stores.
In order to judge the electric charge be in fact separated of the memory body both sides that two bits store, and adopt reverse reading.Reverse reading representative puts on source terminal by by reading bias voltage, to sense electric charge in drain side junction to complete read operation; Vice versa.If source side injection has electric charge, then reading bias voltage needs enough high, can stop the impact of the electric charge on source side injection.
But when the memory body that operation two bit stores, two bits of same memory cell still can interact and have problems each other.Therefore, if the side of memory cell has stored a bit, then when reading the opposite side of memory cell, make originally to have the situation that electric current declines, i.e. so-called second bit effect for the part of high electric current.That is, when carrying out read operation to memory cell, the bit originally existed can impact memory cell, and energy barrier is improved, and causes the critical voltage (Vt) read to raise.In the case, just easily read error is caused.
Second bit effect not only can cause the difficulty on element operation, and the reliability of element even can be caused to reduce.Further, because second bit effect decreases the critical voltage space (Vtwindow) of reading induction nargin (sensemargin) and operation left and right bit, make the operation of multistage memory body more difficult.
As can be seen here, above-mentioned existing read-only memory and manufacture method thereof, in product structure, manufacture method and use, obviously still have inconvenience and defect, and are urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development always, and common product and method do not have appropriate structure and method to solve the problem, this is obviously the anxious problem for solving of relevant dealer.Therefore how to found a kind of new read-only memory and manufacture method thereof, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
The object of the invention is, overcome the defect that existing read-only memory exists, and provide a kind of new read-only memory, technical problem to be solved to reduce second bit effect, is very suitable for practicality.
Another object of the present invention is to, overcome the defect that existing read-only memory manufacture method exists, and a kind of manufacture method of new read-only memory is provided, technical problem to be solved to make by the little memory body of second bit effects, thus be more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of read-only memory that the present invention proposes, it comprises substrate, source area and drain region, charge storing structure, grid and local extreme doped region.Above-mentioned source area and drain region are arranged in substrate, in the substrate of charge storing structure between source area and drain region, grid is then arranged on charge storing structure.Local extreme doped region is in the substrate between source area and drain region, and described local extreme doped region comprises a low doping concentration district and at least one high-dopant concentration district.High-dopant concentration district one of to be arranged in source area and drain region between low doping concentration district, and wherein the doping content in high-dopant concentration district is higher than the doping content in low doping concentration district more than 3 times.Above-mentioned high-dopant concentration district and low doping concentration district are same conductivity.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid read-only memory, the doping content in wherein said high-dopant concentration district is higher than the doping content in low doping concentration district less than 10 times.
Aforesaid read-only memory, the doping content of wherein said substrate is higher than the doping content in low doping concentration district 3 times to 10 times.
Aforesaid read-only memory, wherein said high-dopant concentration district comprises two doped regions, lays respectively between source area and low doping concentration district and between drain region and low doping concentration district.
Aforesaid read-only memory, the thickness in wherein said low doping concentration district such as exists
between.
Aforesaid read-only memory, wherein said low doping concentration district directly contacts with charge storing structure.
Aforesaid read-only memory, the distance between the edge in wherein said low doping concentration district and source area or drain region is about less than
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of manufacture method of read-only memory that the present invention proposes, it is included in a substrate well region forming a distance of being separated by with its surface, and in substrate, form a charge storing structure, then on charge storing structure, form a grid.Then, in the substrate of charge storing structure both sides, one source pole district and a drain region is formed.A local extreme doped region is formed in substrate between source area and drain region, wherein said local extreme doped region at least comprises a low doping concentration district and at least one high-dopant concentration district, and the doping content in high-dopant concentration district is higher than the doping content in low doping concentration district more than 3 times.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid read-only memory, the method wherein forming above-mentioned well region comprises implants an admixture to substrate, is located in the substrate beyond above-mentioned distance; Or the method forming above-mentioned well region comprises adulterates to substrate, then inverse doping is carried out, to reduce the intrabasement doping content within above-mentioned distance to substrate.
The manufacture method of aforesaid read-only memory, the method wherein forming above-mentioned local extreme doped region comprises carries out carbon ion to the edge of source area and drain region and to implant altogether or low-temperature ion implants thermal reduction technique of arranging in pairs or groups, to form up-narrow and down-wide high-dopant concentration district.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, read-only memory of the present invention and manufacture method thereof at least have following advantages and beneficial effect: read-only memory of the present invention adopts the structure of local extreme doped region in channel region, so can reduce second bit effect by the passage that doping content difference is large for the impact on element operation.
In sum, the invention relates to a kind of read-only memory and manufacture method thereof.This read-only memory, comprises substrate, source area and drain region, charge storing structure, grid and local extreme doped region.Above-mentioned source area and drain region are arranged in substrate, in the substrate of charge storing structure between source area and drain region, grid is then arranged on charge storing structure.Local extreme doped region is in the substrate between source area and drain region, and described local extreme doped region comprises a low doping concentration district and at least one high-dopant concentration district.High-dopant concentration district one of to be arranged in source area and drain region between low doping concentration district, and wherein the doping content in high-dopant concentration district is higher than the doping content in low doping concentration district more than 3 times.Present invention also offers a kind of manufacture method of read-only memory.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of read-only memory according to the first embodiment of the present invention.
Fig. 2 is the schematic diagram of the read-only memory of simulated experiment one.
Fig. 3 A is the schematic diagram of doping content change of the source area of read-only memory of display simulation experiment one, passage and drain region.
Fig. 3 B is the second bit effect change figure of display simulation experiment one.
Fig. 4 is the schematic diagram of the read-only memory of simulated experiment two.
Fig. 5 A is the schematic diagram that display simulation tests the doping content change in the low doping concentration district in the local extreme doped region of the read-only memory of two.
Fig. 5 B is the second bit effect change figure of display simulation experiment two.
Fig. 6 is the second bit effect change figure of display simulation experiment three.
Fig. 7 is the second bit effect change figure of display simulation experiment four.
Fig. 8 A is the schematic diagram that display simulation tests the varied in thickness in the low doping concentration district in the local extreme doped region of the read-only memory of five.
Fig. 8 B is the second bit effect change figure of display simulation experiment five.
Fig. 9 is the schematic diagram of the read-only memory of simulated experiment six.
Figure 10 is the second bit effect change figure of display simulation experiment six.
Figure 11 is the schematic diagram of the read-only memory of simulated experiment seven.
Figure 12 A is the schematic diagram of the distance change between the edge of the charge storaging area of display simulation experiment seven and the edge in low doping concentration district.
Figure 12 B is the second bit effect change figure of display simulation experiment seven.
Figure 13 A is the schematic diagram of the distance change between the edge of the charge storaging area of display simulation experiment eight and the edge in low doping concentration district.
Figure 13 B is the second bit effect change figure of display simulation experiment eight.
Figure 14 A to Figure 14 C is the schematic diagram of the read-only memory of simulated experiment nine.
Figure 15 is the second bit effect change figure of display simulation experiment nine.
Figure 16 A to Figure 16 D is the manufacturing process generalized section of a kind of read-only memory according to the second embodiment of the present invention.
100,1600,406: substrate 102a, 408a, 1608: source area
102b, 408b, 1608: drain region 104,1604: charge storing structure
106,1606: grid 108,1610: local extreme doped region
110,412,1612: low doping concentration district 112,1614,404: high-dopant concentration district
114,1602: well region 200,400: read-only memory
202,402:ONO layer 204: position
410: charge storaging area 1600a: surface
1618: character line 1616: insulating barrier
D1, d2: distance W: width
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the read-only memory proposed according to the present invention and its embodiment of manufacture method, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Fig. 1 is the schematic diagram of a kind of read-only memory according to the first embodiment of the present invention.
In FIG, read-only memory comprises substrate 100, source area 102a and drain region 102b, charge storing structure 104, grid 106 and local extreme doped region 108.In this article, so-called " local extreme doped region " refers to the region having doping content difference and be greater than multiple doped regions formation of more than 3 times.Be in the substrate 100 between source area 102a and drain region 102b as local extreme doped region 108, and described local extreme doped region 108 comprise a low doping concentration district 110 and at least one high-dopant concentration district 112.Doping content difference in the above-mentioned local extreme doped region 108 be made up of multiple doped region, as being greater than more than 3 times, and only has compared with low doping concentration district 110, and its second bit effect can reduce about 0.66 times; Otherwise if when above-mentioned doping content difference is not greater than 3 times, it is not obvious that its second bit effect reduces degree.Above-mentioned source area 102a and drain region 102b is arranged in substrate 100, in the substrate 100 of charge storing structure 104 between source area 102a and drain region 102b, grid 106 is arranged on charge storing structure 104.
High-dopant concentration district 112 can select only to be arranged at and be arranged between drain region 102b and low doping concentration district 110 between source area 102a and low doping concentration district 110, only; Or as shown in Figure 1, be separately positioned on source area 102a and between drain region 102b and low doping concentration district 110.The doping content in high-dopant concentration district 112 need be higher than the doping content in low doping concentration district 110 more than 3 times; For example 3 times ~ 20 times; Be preferably more than 3 times and less than 10 times.Above-mentioned charge storing structure 104 can be ONO layer or other electric charge storage layers be applicable to.
In the present embodiment, high-dopant concentration district 110 is up-narrow and down-wide regions, and high-dopant concentration district 112 and low doping concentration district 110 are same conductivity, such as high-dopant concentration district 112 is all p-type with low doping concentration district 110, and source area 102a and drain region 102b is N-shaped.Generally have well region 114 as in substrate 100, its doping content (i.e. the doping content of substrate 100) is such as high than the doping content in low doping concentration district 110 3 times to 10 times; In other words, the doping content of substrate 100 can equal or close to the doping content in high-dopant concentration district 112.
Below enumerate several simulated experiment.
Simulated experiment one
Refer to shown in Fig. 2, Fig. 3 A and Fig. 3 B, Fig. 2 is the schematic diagram of the read-only memory of simulated experiment one.Fig. 3 A is the schematic diagram of doping content change of the source area of read-only memory of display simulation experiment one, passage and drain region.Fig. 3 B is the second bit effect change figure of display simulation experiment one.Simulated object is have the read-only memory (as Fig. 2) of local extreme doped region and do not have traditional read-only memory (reference examples) of local extreme doped region respectively, and shows the doping content change of its source area, passage and drain region at Fig. 3 A.In the read-only memory 200 of Fig. 2, position 204 iunjected charge on the right side of ONO layer 202, therefore the experiment of simulation is when reading the opposite side of ONO layer 202, estimates the second bit effect change of the memory body with or without local extreme doped region, the results are shown in Fig. 3 B.
Second bit effect can be significantly reduced by the known read-only memory with local extreme doped region of Fig. 3 B.
Simulated experiment two
Refer to shown in Fig. 4, Fig. 5 A and Fig. 5 B, Fig. 4 is the schematic diagram of the read-only memory of simulated experiment two.Fig. 5 A is the schematic diagram that display simulation tests the doping content change in the low doping concentration district in the local extreme doped region of the read-only memory of two.Fig. 5 B is the second bit effect change figure of display simulation experiment two.Simulated object is the read-only memory 400 (as Fig. 4) with local extreme doped region, and wherein fixing parameter is: L
g=0.08 μm; L
eff=0.057 μm;
Doping content=the 2e18cm of the doping content=substrate 406 in high-dopant concentration district 404
-3;
Doping content=the 1e20cm of source area 408a and drain region 408b
-3;
The width of charge storaging area 410 is
and the left hand edge of its right side edge and drain region 408b trims.
Parameter is the doping content in the low doping concentration district 412 in local extreme doped region, and the doping content change of asking for an interview Fig. 5 A display is by the 3.0e18cm greatly of the doping content than high-dopant concentration district 404
-3to the 1.0e16cm less than the doping content in high-dopant concentration district 404
-3.
Analog result please see the following form one with Fig. 5 B.
Table one
Can be learnt by table one, when concentration difference is greater than 3 times, second bit effect only has 0.66 times of uniform concentration (namely the concentration in low doping concentration district 412 is 2.0e18).If when the doping content in high-dopant concentration district 404 does not have higher than 3 times than the doping content in low doping concentration district 412, although second bit effect also has the trend reduced, effect is so obvious.
The above results can obtain from Fig. 5 B equally, and when the doping content in high-dopant concentration district 404 is higher than the doping content in low doping concentration district 412 more than 10 times, the change of second bit effect diminishes gradually, even if so the doping content difference between high-dopant concentration district 404 and low doping concentration district 412 is larger, will tend to consistent for reduction second bit effect to the impact of memory body.
Simulated experiment three
Refer to shown in Fig. 6, Fig. 6 is the second bit effect change figure of display simulation experiment three.Simulated object is substantially the same with the read-only memory 400 of Fig. 4, and wherein fixing parameter is: L
g=0.08 μm; L
eff=0.057 μm;
The doping content in low doping concentration district is fixed as 1e17cm
-3;
Doping content=the 1e20cm of source area and drain region
-3;
The width of charge storaging area 410 is
and the left hand edge of its right side edge and drain region 408b trims.
Parameter is the doping content of high-dopant concentration district in local extreme doped region and substrate, and simulates 1e18cm respectively
-3, 2e18cm
-3, 3e18cm
-3result as Fig. 6, the doping content change wherein showing high-dopant concentration district is little on the impact of memory body for reduction second bit effect, but lower doping content can affect V
pt(punch-throughvoltage).
Simulated experiment four
Refer to shown in Fig. 7, Fig. 7 is the second bit effect change figure of display simulation experiment four.Simulated object is substantially the same with the read-only memory 400 of Fig. 4, and wherein fixing parameter is: L
g=0.08 μm; L
eff=0.057 μm;
The doping content in low doping concentration district is fixed as 1e17cm
-3;
Doping content=the 1e20cm of source area and drain region
-3;
The width of charge storaging area 410 is
and the left hand edge of its right side edge and drain region 408b trims.
The doping content in the high-dopant concentration district in local extreme doped region is all high than the doping content in low doping concentration district 10 times.
Parameter is the doping content in high-dopant concentration district and low doping concentration district, and the doping content simulating high-dopant concentration district is respectively 1e18cm
-3, 2e18cm
-3, 3e18cm
-3situation, the results are shown in Fig. 7.
As shown in Figure 7, as long as maintain the doping content ratio of high and low concentration doped region, just similar result can be obtained.
Simulated experiment five
Refer to shown in Fig. 8 A and Fig. 8 B, Fig. 8 A is the schematic diagram that display simulation tests the varied in thickness in the low doping concentration district in the local extreme doped region of the read-only memory of five.Fig. 8 B is the second bit effect change figure of display simulation experiment five.Simulated object is substantially the same with the read-only memory 400 of Fig. 4, and wherein fixing parameter is: L
g=0.08 μm; L
eff=0.057 μm;
The doping content in low doping concentration district is 1e17cm
-3;
The doping content of high-dopant concentration district and substrate is all 2e18cm
-3;
Doping content=the 1e20cm of source area and drain region
-3;
The width of charge storaging area 410 is
and the left hand edge of its right side edge and drain region 408b trims.
Parameter is the thickness in low doping concentration district, ask for an interview Fig. 8 A show varied in thickness be by
extremely
analog result is shown in Fig. 8 B.From Fig. 8 B, the thickness in low doping concentration district exists
between, just there is the effect that can reduce second bit effect.And, because be greater than from the thickness of analog result when low doping concentration district
improvement degree increase limited, so the thickness in low doping concentration district is preferably
between.
Simulated experiment six
Refer to shown in Fig. 9 and Figure 10, Fig. 9 is the schematic diagram of the read-only memory of simulated experiment six.Figure 10 is the second bit effect change figure of display simulation experiment six.Simulated object is as the read-only memory of Fig. 9, and wherein fixing parameter is:
L
g＝0.08μm；L
eff＝0.057μm；
The doping content in low doping concentration district is 1e17cm
-3;
The doping content of high-dopant concentration district and substrate is all 2e18cm
-3;
Doping content=the 1e20cm of source area and drain region
-3;
The width of charge storaging area 410 is
and the left hand edge of its right side edge and drain region 408b trims.
Parameter be distance d1 between low doping concentration district and ONO floor by
change, analog result is shown in Figure 10.As shown in Figure 10, the effect that directly contacts of low doping concentration district and ONO floor (i.e. charge storing structure) is best.
Simulated experiment seven
Refer to shown in Figure 11, Figure 12 A and Figure 12 B, Figure 11 is the schematic diagram of the read-only memory of simulated experiment seven.Figure 12 A is the schematic diagram of the distance change between the edge of the charge storaging area of display simulation experiment seven and the edge in low doping concentration district.Figure 12 B is the second bit effect change figure of display simulation experiment seven.Simulated object is as the read-only memory of Figure 11, and wherein fixing parameter is:
L
g＝0.08μm；L
eff＝0.057μm；
The doping content in low doping concentration district is 1e17cm
-3;
The doping content of high-dopant concentration district and substrate is all 2e18cm
-3;
Doping content=the 1e20cm of source area and drain region
-3.
Parameter is the distance between the edge in source area 408a or drain region 408b and low doping concentration district, ask for an interview Figure 12 A show width W change be by
extremely
analog result is shown in Figure 12 B.
Due to L
gwhen being 0.08 μm, width W corresponding when the distance between the edge of charge storaging area 410 and the edge in low doping concentration district is 0 is
so from Figure 12 B, the distance between the edge in source area 408a or drain region 408b and low doping concentration district is less than
helpful to reduction second bit effect, and the edge that low doping concentration district is aimed at the edge of charge storaging area can obtain optimum efficiency.
Simulated experiment eight
Refer to shown in Figure 13 A and Figure 13 B, Figure 13 A is the schematic diagram of the distance change between the edge of the charge storaging area of display simulation experiment eight and the edge in low doping concentration district.Figure 13 B is the second bit effect change figure of display simulation experiment eight.Simulated object is as the read-only memory of simulated experiment seven, and wherein difference is only at L
gbe 0.07 μm, L
eff=0.043 μm.
Parameter is the distance between the edge in source area 408a or drain region 408b and low doping concentration district 412 equally, ask for an interview Figure 13 A show change width be by
extremely
analog result is shown in Figure 13 B.
Due to L
gwhen being 0.07 μm, width corresponding when the distance between the edge of charge storaging area and the edge in low doping concentration district is 0 is
so from Figure 13 B, the distance between the edge in source area 408a or drain region 408b and low doping concentration district is less than
helpful to reduction second bit effect, and the edge that low doping concentration district is aimed at the edge of charge storaging area can obtain optimum efficiency.Such result and the simulated experiment sample July 1st.
Simulated experiment nine
Consult shown in Figure 14 A to Figure 14 C and Figure 15, Figure 14 A to Figure 14 C is the schematic diagram of the read-only memory of simulated experiment nine.Figure 15 is the second bit effect change figure of display simulation experiment nine.
Simulated object is as the read-only memory of Figure 14 A to Figure 14 C, and wherein fixing parameter is:
L
g＝0.08μm；L
eff＝0.057μm；
The doping content in low doping concentration district is 1e17cm
-3;
The doping content of high-dopant concentration district and substrate is all 2e18cm
-3;
Doping content=the 1e20cm of source area and drain region
-3;
The width of charge storaging area 410 is
and the left hand edge of its right side edge and drain region 408b trims.
Parameter is the relation of high and low concentration doped region in local extreme doped region and charge storaging area.Figure 14 A is that both sides, low doping concentration district have symmetrical high-dopant concentration district; Figure 14 B is that low doping concentration district only has while there is asymmetric single high-dopant concentration district, and high-dopant concentration district and charge storaging area are positioned at the same side; Figure 14 C is that low doping concentration district only has while there is asymmetric single high-dopant concentration district equally, but high-dopant concentration district is positioned at not homonymy with charge storaging area.Analog result is shown in Figure 15.
As shown in Figure 15, the structure of Figure 14 C has the effect preferably suppressing second bit effect.
Above about the read-only memory schematic diagram of simulated experiment two ~ nine, as all can refer to the content of Fig. 4 without special sign.
Figure 16 A to Figure 16 D is the manufacturing process generalized section of a kind of read-only memory according to the second embodiment of the present invention.
Refer to shown in Figure 16 A, in a substrate 1600, form 1600a surperficial with it to be separated by the well region 1602 of a distance d2, wherein the doping content of well region 1602 is higher than the essential doping content of substrate 1600 more than 10 times.
Above technique directly implants an admixture to substrate 1600, is located in the substrate 1600 beyond distance d2, the heat treatment carried out after also can coordinating general implanted ions.In other embodiments, the mode forming well region 1602 can also be after adulterating to substrate 1600, then carries out once inverse doping, to reduce the doping content in the substrate 1600 within distance d2 to substrate 1600.That is, first can carry out p-type implanted ions to substrate 1600, then carry out N-shaped implanted ions in substrate 1600 within distance d2.
Then refer to shown in Figure 16 B, substrate 1600 is formed charge storing structure 1604, then form grid 1606 on charge storing structure 1604.Charge storing structure 1604 is ONO layer such as, and grid 1606 such as polysilicon layer.
Then refer to shown in Figure 16 C, in the substrate 1600 between charge storing structure 1604, form source/drain region 1608.Afterwards, a local extreme doped region 1610 is formed in substrate 1600 between source/drain region 1608, wherein said local extreme doped region 1610 at least comprises a low doping concentration district 1612 and at least one high-dopant concentration district 1614, and the doping content in high-dopant concentration district 1614 is higher than the doping content in low doping concentration district 1612 more than 3 times.And the making in high-dopant concentration district 1614 is for example carry out sack cloth to the edge of source/drain region 1608 to plant technique, to form up-narrow and down-wide high-dopant concentration district 1614, wherein said sack cloth is planted technique such as carbon ion and is implanted (Carbonco-implantation) or low-temperature ion altogether and implant (Lowtemperatureionimplantation) and to arrange in pairs or groups thermal reduction technique (Thermalreduction), accurately to obtain the doping profile (dopingprofile) in required high-dopant concentration district 1614.Now, the doping content of well region 1602 is such as high than the doping content in low doping concentration district 1,612 3 times to 10 times.
Last technique of optionally carrying out Figure 16 D, forms insulating barrier 1616 on surface, source/drain region 1608, and in whole substrate 1600, forms the character line 1618 connecting grid 1606.
Based on above-mentioned, design concept of the present invention is the channel region of read-only memory, is formed local extreme doped region with the doped region that multiple doping content difference is large, and reduces second bit effect by this for the impact on element operation.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (9)
1. a read-only memory, is characterized in that it comprises:
One substrate;
One source pole district and a drain region, be arranged in this substrate;
One charge storing structure, in this substrate between this source area and this drain region;
One grid, is arranged on this charge storing structure; And
One local extreme doped region, in this substrate between this source area and this drain region, and this local extreme doped region comprises:
One low doping concentration district; And
Liang Ge high-dopant concentration district, lays respectively between this source area and this low doping concentration district and between this drain region and this low doping concentration district, wherein:
The doping content in this Liang Ge high-dopant concentration district is higher than the doping content in this low doping concentration district more than 3 times, and this Liang Ge high-dopant concentration district and this low doping concentration district are same conductivity.
2. read-only memory according to claim 1, is characterized in that the doping content in wherein said Liang Ge high-dopant concentration district is higher than the doping content in this low doping concentration district less than 10 times.
3. read-only memory according to claim 1, is characterized in that the doping content of wherein said substrate is higher than the doping content in this low doping concentration district 3 times to 10 times.
4. read-only memory according to claim 1, is characterized in that the thickness in wherein said low doping concentration district exists
between.
5. read-only memory according to claim 1, is characterized in that wherein said low doping concentration district directly contacts with this charge storing structure.
6. read-only memory according to claim 1, is characterized in that the distance between the edge in wherein said low doping concentration district and this source area or this drain region is less than
7. a manufacture method for read-only memory, is characterized in that it comprises the following steps:
In a substrate, form a well region, the surface of this well region and this substrate is separated by a distance;
Form a charge storing structure on this substrate;
This charge storing structure is formed a grid;
One source pole district and a drain region is formed in this substrate of these charge storing structure both sides; And
A local extreme doped region is formed in this substrate between this source area and this drain region, wherein this local extreme doped region at least comprises a low doping concentration district and at least one high-dopant concentration district, and the doping content in this at least one high-dopant concentration district is higher than the doping content in this low doping concentration district more than 3 times;
Wherein, described at least one high-dopant concentration district comprises two doped regions, lays respectively between this source area and this low doping concentration district and between this drain region and this low doping concentration district.
8. the manufacture method of read-only memory according to claim 7, is characterized in that the method wherein forming this well region comprises: implant an admixture to this substrate, is located in this substrate in addition of this distance; Or the method forming this well region comprises:
This substrate is adulterated; And
Inverse doping is carried out, to reduce this intrabasement doping content within this distance to this substrate.
9. the manufacture method of read-only memory according to claim 7, it is characterized in that the method wherein forming this local extreme doped region comprises: carbon ion is carried out to the edge of this source area and this drain region and to implant altogether or low-temperature ion implants thermal reduction technique of arranging in pairs or groups, to form this up-narrow and down-wide high-dopant concentration district.
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| CN101083286A (en) * | 2006-06-01 | 2007-12-05 | 株式会社半导体能源研究所 | Nonvolatile semiconductor memory device |
| CN101087003A (en) * | 2006-06-09 | 2007-12-12 | 台湾积体电路制造股份有限公司 | Semiconductor element and its forming method |
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| US6724032B2 (en) * | 2002-07-25 | 2004-04-20 | Motorola, Inc. | Multi-bit non-volatile memory cell and method therefor |
| US8330232B2 (en) * | 2005-08-22 | 2012-12-11 | Macronix International Co., Ltd. | Nonvolatile memory device and method of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101083286A (en) * | 2006-06-01 | 2007-12-05 | 株式会社半导体能源研究所 | Nonvolatile semiconductor memory device |
| CN101087003A (en) * | 2006-06-09 | 2007-12-12 | 台湾积体电路制造股份有限公司 | Semiconductor element and its forming method |
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