CN108735795A - （0001）The hexagonal phase SiC wafers of face extension, UMOSFET devices and preparation method thereof - Google Patents
（0001）The hexagonal phase SiC wafers of face extension, UMOSFET devices and preparation method thereof Download PDFInfo
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- 235000012431 wafers Nutrition 0.000 title claims abstract description 76
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 175
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 82
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 80
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000003672 processing method Methods 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000012937 correction Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 21
- 238000001039 wet etching Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 9
- 239000000203 mixture Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 210000002421 cell wall Anatomy 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
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- 230000001590 oxidative effect Effects 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000004913 activation Effects 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 13
- 239000000243 solution Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
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- 230000008021 deposition Effects 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a kind of hexagonal phase SiC wafers of (0001) face extension, UMOSFET devices and preparation method thereof.The epi-layer surface of the wafer is formed at least one polygon groove, and has at least one line and hexagonal phase SiC crystal in the intersection of at least one of multiple faces for constituting polygon ditch groove groove wall face and epi-layer surfaceCrystal face orCrystal face is parallel.The processing method of the wafer includes：It processes to form an at least polygon groove in the epi-layer surface of the hexagonal phase SiC wafers of (0001) face extension, and makes it perpendicular to (0001) face silicon carbide epitaxial wafer surface；At least one of multiple faces face to constituting polygon ditch groove groove wall carries out crystal face correction and makes have at least one line and hexagonal phase SiC crystal in the intersection of at least one face and epi-layer surfaceCrystal face orCrystal face is parallel.The present invention is obtained, and UMOSFET devices can utilizeOrThe mobility characteristics of crystal face and its equivalent crystal planes improve device performance.
Description
Technical field
The present invention relates to a kind of preparation methods of silicon carbide UMOSFET devices, more particularly, to a kind of (0001) face (silicon
Face) extension hexagonal phase SiC wafers and its processing method, and based on (0001) face extension hexagonal phase SiC wafers { 1
00 } face and { 110 } the novel SiC UMOSFET device architectures and preparation method thereof in face, belong to microelectronic circuit arts field.
Background technology
Silicon carbide (SiC) is a kind of polycrystalline material, the use of more crystal form is at present tripartite's phase, cubic phase and six sides
Phase, hexagonal phase is common 2H, 4H, 6H, 8H and 10H etc., wherein most studied 4H crystal forms, as shown in fig.1, its is main
Crystal face has (0001), (000)、(11And (1 0)00) four and corresponding equivalent crystal planes (wherein (11And (1 0)00) and
Its equivalent crystal planes is also commonly known as faceted pebble), the mobility in each face is different, and what VDMOSFET devices were mainly studied at present is
(0001) the mobility influence factor of crystal face, most of device is also focused on carries out device design using (0001) face.It is international
Shang Yeyou seminars are in UMOSFET device of the research based on (0001) face wafer, but what is mainly studied is average vertical migration
Rate there is no a kind of device to pertain only to (11 at presentOr (1 0)00) crystal face and its device of equivalent crystal planes, and (11And (1 0)00) electron mobility in face is high than (0001) face.
Also there is researcher to use (11 in addition0) VDMOSFET devices are made on wafer, with utilization (110) Gao Qian in face
Shifting rate characteristic, still (110) wafer of face extension is seldom, and uses (110) epitaxy defect can extend directly into entire crystalline substance
Circular surfaces, prepared element leakage is very big, and electric property is bad.It would therefore be desirable to have a kind of novel silicon carbide UMOSFET
Device, can be on (0001) wafer with utilization (11And (1 0)00) mobility characteristics of crystal face and its equivalent crystal planes improve
The performance of device.
The prior art directly etches U-type groove down when preparing UMOSFET devices using (0001) wafer, there are the problem of
Include mainly following：(1) surface damage caused by dry etching can influence device performance；(2) wafer exists in cutting
Certain crystal orientation drift angle, shown in Fig. 2 a, usually 4 ° or 8 °, therefore epitaxial layer also carries certain drift angle, direct etching
Obtained slot is not real (11Or (1 0)00) crystal face and its their equivalent crystal planes, really one complicated more
Crystal face combines, shown in Fig. 2 b；(3) prepared by mask when dry etching cannot achieve fitting like a glove for crystal face or crystal orientation,
When there is overlay mark, when photoetching alignment, generally can all have overlay error, if accurate crystal orientation is not not present inherently
When label, just it is even more impossible to obtain accurate crystal face or crystal orientation.
Invention content
The main purpose of the present invention is to provide a kind of hexagonal phase SiC wafers of (0001) face extension and its processing method,
UMOSFET devices and preparation method thereof, to overcome deficiency in the prior art.
For realization aforementioned invention purpose, the technical solution adopted by the present invention includes：
An embodiment of the present invention provides a kind of hexagonal phase SiC wafers of (0001) face extension, the epitaxial layer tables of the wafer
Face is formed at least one polygon groove, and at least one of multiple faces for constituting polygon ditch groove groove wall face with
There is { the 1 of at least one line and hexagonal phase SiC crystal in the intersection of the epi-layer surface00 } crystal face or { 110 } crystal face is flat
Row.
One of preferably, it is hexagonal phase to constitute at least one of multiple faces of polygon ditch groove groove wall face
{ the 1 of SiC crystal00 } crystal face or { 110 } crystal face.
Preferably, the polygon groove includes hexagon groove and/or rectangular grooves.
The embodiment of the present invention additionally provides a kind of UMOSFET devices comprising：
(0001) the hexagonal phase SiC wafers of face extension, epi-layer surface are formed at least one polygon groove, and
Constitute at least one of multiple faces of polygon ditch groove groove wall face has at least one with the intersection of the epi-layer surface
Bar line and { the 1 of hexagonal phase SiC crystal00 } crystal face or { 110 } crystal face is parallel, while the epitaxial layer also includes p-well region, N+Area and P+Area；
The gate dielectric layer at least covering the polygon ditch groove groove wall, the grid being arranged on the gate dielectric layer and with
The source electrode of the wafer connection, drain electrode.
One of preferably, it is hexagonal phase to constitute at least one of multiple faces of polygon ditch groove groove wall face
{ the 1 of SiC crystal00 } crystal face or { 110 } crystal face.
Preferably, the polygon groove includes hexagon groove and/or rectangular grooves.
One of preferably, the wafer further includes substrate, and the epitaxial layer is formed over the substrate, the source
Pole is arranged on said epitaxial layer there, and the drain electrode is arranged on the substrate floor.
Preferably, the source electrode is arranged around the notch of the polygon groove.
Preferably, the material of the gate dielectric layer includes SiO2。
Preferably, it is additionally provided with passivation layer on the grid.
One of preferably, the p-well region, N+Area and P+Area is to be formed in the extension by ion implanting mode
In layer.
The processing method that the embodiment of the present invention additionally provides the hexagonal phase SiC wafers of (0001) face extension comprising：
It processes to form an at least polygon groove in the epi-layer surface of the hexagonal phase SiC wafers of (0001) face extension, and
Make at least one face of the composition polygon ditch groove groove wall perpendicular to (0001) face silicon carbide epitaxial wafer surface；
At least one of multiple faces to composition polygon ditch groove groove wall face carries out crystal face correction and makes this at least
One face has { the 1 of at least one line and hexagonal phase SiC crystal with the intersection of the epi-layer surface00 } crystal face or { 110}
Crystal face is parallel.
One of preferably, the processing method includes：In multiple faces to constituting the polygon ditch groove groove wall
At least one face carry out crystal face correction and make at least one face be hexagonal phase SiC crystal { 100 } crystal face or { 110 } brilliant
Face.
More preferably, the processing method includes：
It processes to be formed in the epi-layer surface of the hexagonal phase SiC wafers of (0001) face extension at least through dry etching mode
The polygon groove；
And/or at least select the multiple faces of oxidizing process and/or wet etching mode to the composition polygon ditch groove groove wall
At least one of face carry out the crystal face correction.
Further, first at least one of multiple faces of composition polygon ditch groove groove wall face is carried out at oxidation
Reason, carries out wet etching later, to complete the crystal face correction.
Preferably, the polygon groove includes hexagon groove and/or rectangular grooves.
The production method that the embodiment of the present invention additionally provides the UMOSFET devices comprising：
(1) the hexagonal phase SiC wafers of (0001) face extension are processed using processing method above-mentioned；
(2) the wafer manufacturing UMOSFET devices are based on.
Preferably, step (2) specifically includes：
Patterned injection mask is set in the epi-layer surface of the wafer, and by ion implanting mode in described outer
Prolong and forms p-well region, N in layer+Area and P+Area, later high-temperature annealing activation implanted dopant；
Gate oxide is formed on less than the cell wall of the polygon groove；
In forming patterned highly doped polysilicon gate on the gate oxide；
In forming continuous passivation layer on the grid and at least regional area of the epi-layer surface；
Source electrode is made on said epitaxial layer there, and source electrode is made to expose from passivation layer；
Drain electrode is made on the substrate floor of the wafer.
Compared with prior art, advantages of the present invention includes：
The processing method of the hexagonal phase SiC wafers of (0001) face provided by the invention extension passes through oxidizing process and wet etching
Method crystal face is corrected to { 100 } or { 10 }, can to avoid wafer in cutting crystal orientation existing for caused epitaxial layer
Drift angle is influenced caused by device performance；And obtained UMOSFET devices are based on the hexagonal phase SiC wafers of (0001) face extension, energy
It is enough to utilize { 100 } and { 110 } mobility characteristics of crystal face and its equivalent crystal planes, to improve the performance of device.
Description of the drawings
Fig. 1 is the structural schematic diagram of 4H-SiC crystal；
Fig. 2 a are the schematic diagrames of 4H-SiC crystal epitaxial layers crystal orientation drift angle；
Fig. 2 b are the relation schematic diagrams of U-type groove and crystal orientation drift angle that conventional dry lithographic method obtains；
Fig. 3 is to be based on { 1 in an exemplary embodiments of the invention00 } or { 110 } the silicon carbide UMOSFET devices of crystal face
Preparation method flow diagram；
Fig. 4 a and Fig. 4 b are to be based on { 1 in an exemplary embodiments of the invention respectively0 } the silicon carbide UMOSFET devices of crystal face
Vertical view and sectional view；
Fig. 5 a and Fig. 5 b are to be based on { 1 in an exemplary embodiments of the invention respectively00 } the silicon carbide UMOSFET devices of crystal face
Vertical view and sectional view；
Fig. 6 a and Fig. 6 b are the 4H- that an exemplary embodiments of the invention use wet etching crystal face alignment technique tentatively to obtain
The structural schematic diagram of SiC hexagon grooves；
Fig. 7 a and Fig. 7 b are to be based on { 1 in an exemplary embodiments of the invention00 } or { 110 } the hexagon groove of crystal face
Array schematic diagram；
Fig. 8 is that the side wall of hexagon groove in an exemplary embodiments of the invention is parallel to { 100 } crystal face or { 110 } brilliant
The structural schematic diagram in face；
Fig. 9 is that the side wall of hexagon groove and the intersection on surface are parallel to { 1 in an exemplary embodiments of the invention00 } crystal face
Or { 110 } structural schematic diagram of crystal face；
Figure 10 a and Figure 10 b are the hexagon ditch that side wall is all and partly faceted pebble in an of the invention exemplary embodiments respectively
Slot structure schematic diagram.
Specific implementation mode
In view of deficiency in the prior art, inventor is able to propose the present invention's through studying for a long period of time and largely putting into practice
Technical solution.The technical solution, its implementation process and principle etc. will be further explained as follows.But it should manage
Solution, within the scope of the present invention, each technical characteristic of the invention and specifically described in below (e.g. embodiment) each technical characteristic
Between can be combined with each other, to form a new or preferred technical solution.Due to space limitations, I will not repeat them here.
New technology of the present invention essentially consists in particular crystal plane SiC UMOSFET structures, and core content is how to obtain
To the polygon groove of particular crystal plane.
The one side of the embodiment of the present invention provides a kind of hexagonal phase SiC wafers of (0001) face extension, the wafer
Epi-layer surface be formed at least one polygon groove, and constitute in multiple faces of the polygon ditch groove groove wall extremely
A few face has { the 1 of at least one line and hexagonal phase SiC crystal with the intersection of the epi-layer surface00 } crystal face or { 11
0 } crystal face is parallel, to utilize the specific properties in the two faces.
One of preferably, it is hexagonal phase to constitute at least one of multiple faces of polygon ditch groove groove wall face
{ the 1 of SiC crystal00 } crystal face or { 110 } crystal face.
Preferably, the polygon groove is preferably hexagon groove, can also be the length of side meet the requirements other are polygon
Shape groove, such as rectangular grooves.
The embodiment of the present invention another aspect provides a kind of UMOSFET devices, it is a kind of based on outside (0001) face
{ the 1 of the hexagonal phase SiC wafers prolonged00 } crystal face and { 110 } crystal face and the novel UMOSFET devices of corresponding equivalent crystal planes, packet
It includes：
(0001) the hexagonal phase SiC wafers of face extension, epi-layer surface are formed at least one polygon groove, and
Constitute at least one of multiple faces of polygon ditch groove groove wall face has at least one with the intersection of the epi-layer surface
Bar line and { the 1 of hexagonal phase SiC crystal00 } crystal face or { 110 } crystal face is parallel, to utilize the specific properties in the two faces, simultaneously
The epitaxial layer also includes p-well region, N+Area and P+Area；
The gate dielectric layer at least covering the hexagon ditch groove groove wall, the grid being arranged on the gate dielectric layer and with
The source electrode of the wafer connection, drain electrode.
One of preferably, it is hexagonal phase to constitute at least one of multiple faces of polygon ditch groove groove wall face
{ the 1 of SiC crystal00 } crystal face or { 110 } crystal face.
Preferably, the polygon groove is preferably hexagon groove, can also be the length of side meet the requirements other are polygon
Shape groove, such as rectangular grooves.
One of preferably, the wafer further includes substrate, and the epitaxial layer is formed over the substrate, the source
Pole is arranged on said epitaxial layer there, and the drain electrode is arranged on the substrate floor.
Preferably, the source electrode is arranged around the notch of the polygon groove.
Preferably, the material of the gate dielectric layer includes SiO2。
Preferably, it is additionally provided with passivation layer on the grid.
Preferably, the substrate includes N+Substrate.
One of preferably, the p-well region, N+Area and P+Area is to be formed in the extension by ion implanting mode
In layer.
Preferably, the epi-layer surface shape of the hexagonal phase SiC wafers for (0001) face extension that the UMOSFET devices include
At there is a plurality of polygon groove arrays.
The other side of the embodiment of the present invention additionally provides the processing side of the hexagonal phase SiC wafers of (0001) face extension
Method comprising：
It processes to form an at least polygon groove in the epi-layer surface of the hexagonal phase SiC wafers of (0001) face extension, and
Make the polygon groove vertical in (0001) face silicon carbide epitaxial wafer surface；
At least one of multiple faces to composition polygon ditch groove groove wall face carries out crystal face correction and makes this at least
One face has { the 1 of at least one line and hexagonal phase SiC crystal with the intersection of the epi-layer surface00 } crystal face or { 110}
Crystal face is parallel, to utilize the specific properties in the two faces.
Further, in the processing method, above-mentioned " the polygon groove vertical is in outside the silicon carbide of (0001) face
Prolong piece surface " refer to constituting at least one face of the polygon ditch groove groove wall perpendicular to (0001) face silicon carbide epitaxial wafer table
Face.Particularly preferably, ideally, two faces of the polygon ditch groove groove wall are constituted outside the silicon carbide of (0001) face
Prolong piece surface, remaining four face out of plumb.
One of preferably, the processing method includes：In multiple faces to constituting the polygon ditch groove groove wall
At least one face carry out crystal face correction and make at least one face be hexagonal phase SiC crystal { 100 } crystal face or { 110 } brilliant
Face.
Preferably, the polygon groove is preferably hexagon groove, can also be the length of side meet the requirements other are polygon
Shape groove, such as rectangular grooves.
More preferably, the processing method includes：
It processes to be formed in the epi-layer surface of the hexagonal phase SiC wafers of (0001) face extension at least through dry etching mode
The polygon groove；
And/or at least select the multiple faces of oxidizing process and/or wet etching mode to the composition polygon ditch groove groove wall
At least one of face carry out the crystal face correction.
The first step that the polygon groove of particular crystal plane makes is prepared outside (0001) face by dry etching
Prolong the polygon groove on piece surface, groove vertical at this time is in epitaxial wafer surface, rather than (0001) crystal face.
One of preferably, the processing method includes：When forming the polygon groove with dry etching, answer
So that arbitrary one side and { 1 of the polygon groove00 } crystal face or { 110 } crystal face is parallel, can reduce crystal face school in this way
The positive time, and the size of figure is maintained as far as possible.
Further, first at least one of multiple faces of composition polygon ditch groove groove wall face is carried out at oxidation
Reason, carries out wet etching later, to complete the crystal face correction.
After forming polygon groove, next need to carry out crystal face correction, the six square SiC materials that alignment technique mainly utilizes
The anisotropic properties of structure are expected, including wet etching anisotropy and oxidation anisotropy.SiC material is very difficult to corrode,
Especially (0001) crystal face, still { 100 } and { 110 } two crystal faces can corrode.There is also each for the oxidation of SiC material
The oxidation rate of anisotropy, each crystal face is obviously different, and { 100 } and { 110 } oxidation rate of crystal face is obviously than (0001)
Crystal face is fast, after being oxidized to silica, then uses the method for wet etching again, removes silicon, exposes { 100 } or
{110 } crystal face.
Further, the processing method further includes：It is molten to melt highly basic in 500 DEG C after the completion of the oxidation processes
Liquid is preferably that KOH solution carries out wet etching processing at least one of multiple faces of polygon ditch groove groove wall face, is gone
Silicon forms { 100 } crystal face or { 110 } crystal face.
Preferably, the rate of wet etching processing is close to 1 [mu.
The production method that the other side of the embodiment of the present invention additionally provides the UMOSFET devices comprising：
(1) the hexagonal phase SiC wafers of (0001) face extension are processed using processing method above-mentioned；
(2) the wafer manufacturing UMOSFET devices are based on.
Common UMOSFET device technologies can be used to carry out ion note after correcting crystal face by crystal face alignment technique
The techniques such as enter and prepares UMOSFET devices.
Preferably, step (2) specifically includes：
Patterned injection mask is set in the epi-layer surface of the wafer, and by ion implanting mode in described outer
Prolong and forms p-well region, N in layer+Area and P+Area removes the injection mask, later high-temperature annealing activation implanted dopant；
Gate oxide is formed on less than the cell wall of the polygon groove；
It in deposit polycrystalline silicon gate on the gate oxide, and injects P and activates to form highly doped polysilicon gate, then figure
Change, forms patterned highly doped polysilicon gate；
In forming continuous passivation layer on the grid and at least regional area of the epi-layer surface, and opens electrode and connect
Contact hole；
Source metal is grown on said epitaxial layer there, is annealed, and making forms source electrode, and source electrode is made to expose from passivation layer；
The drain metal on the substrate floor of the wafer, annealing make and form drain electrode.
In short, by the method for the present invention, crystal face is corrected to { 1 by the method for oxidizing process and wet etching00 } brilliant
Face or { 110 } crystal face, can in cutting, device performance be caused in crystal orientation drift angle existing for caused epitaxial layer to avoid wafer
Influence；And obtained UMOSFET devices are based on the hexagonal phase SiC wafers of (0001) face extension, can utilize { 100 } and { 11
0 } mobility characteristics of crystal face and its equivalent crystal planes, to improve the performance of device.
Below in conjunction with attached drawing and some exemplary embodiments to technical scheme of the present invention carry out it is clear, completely retouch
It states.
As shown in figure 3, the preparation method of the UMOSFET devices of the embodiment of the present invention includes：
(1) hexagonal phase SiC wafers are set on substrate, to be dry-etched in hexagonal phase SiC wafer epi-layer surface shapes
At at least one perpendicular to the hexagonal phase SiC wafer epi-layer surfaces of (0001) face extension hexagon groove, the six of particular crystal plane
The first step that side shape groove makes is to prepare the hexagon groove perpendicular to (0001) face epi-layer surface by dry etching,
Groove vertical at this time is in epi-layer surface, rather than (0001) crystal face.Wherein, the hexagon groove is being formed with dry etching
When, it should make arbitrary one side and { 1 of the hexagon groove00 } crystal face or { 110 } crystal face is parallel, can reduce in this way
The time of crystal face correction, and the size of figure is maintained as far as possible.
(2) crystal face of the hexagon groove is corrected with oxidation processes and wet etching processing, forms { 100}
Crystal face or { 110 } crystal face.After forming hexagon groove, next need to carry out crystal face correction, what alignment technique mainly utilized
The anisotropic properties of six square SiC material structures, including wet etching anisotropy and oxidation anisotropy.SiC material is non-
It often is difficult to corrode, especially (0001) crystal face, still { 100 } and { 110 } two crystal faces can corrode.SiC material
There is also anisotropy for oxidation, and the oxidation rate of each crystal face is obviously different, and { 100 } and { 110 } oxidation rate of crystal face
It is obviously fast than (0001) crystal face, after first out being oxidized to silica using oxidation, the method for wet etching is then used again,
Specially：In 500 DEG C, to melt strong base solution, to be preferably KOH solution carry out wet etching processing to the oxidation silicon epitaxial wafer,
Silicon is removed, exposes { 100 } or { 110 } crystal face.Fig. 6 a and Fig. 6 b are respectively illustrated to be corrected using wet etching crystal face
The structural schematic diagram for the 4H-SiC hexagon grooves that technology tentatively obtains.By both the above crystal face alignment technique correct crystal face it
Common UMOSFET device technologies can be used to carry out the techniques such as ion implanting afterwards and prepare UMOSFET devices.
(3) deposition injects mask, and the graphical injection mask, and then ion implanting forms p-well region, N+Area and P+Area；
(4) the injection mask, high-temperature annealing activation implanted dopant are removed；
(5) oxidation forms grid oxide layer；
(6) the deposit polycrystalline silicon gate on the grid oxide layer, and inject P and activate to form highly doped polysilicon gate, then scheme
Shape；
(7) deposition forms passivation layer on the polysilicon gate, and opens electrode contact hole；
(8) in the N+Area and P+Source metal is grown in area, annealing forms source electrode, drains in the bottom surface deposition of substrate golden
Belong to, high annealing forms drain electrode.
The obtained UMOSFET devices of the present embodiment are { the 1 of hexagonal phase SiC wafer of the one kind based on (0001) face extension00}
Crystal face and { 110 } crystal face and the novel UMOSFET devices of corresponding equivalent crystal planes.Shown in Fig. 4 a to Fig. 5 b, it includes
(0001) the hexagonal phase SiC wafers of face extension, epi-layer surface are formed at least one hexagon groove, while the extension
Layer also includes p-well region, N+Area and P+Area；At least cover the gate dielectric layer of the hexagon ditch groove groove wall, setting is situated between in the grid
Grid on matter layer and the source electrode being connect with the wafer, drain electrode.Preferably, six of the hexagon ditch groove groove wall are constituted
At least one of face face is { the 1 of hexagonal phase SiC crystal00 } crystal face or { 110 } crystal face.The wafer further includes substrate, institute
It states epitaxial layer to be formed over the substrate, on said epitaxial layer there, the drain electrode is arranged at the substrate bottom for the source electrode setting
On face.Preferably, the source electrode is arranged around the notch of the hexagon groove.Preferably, the material packet of the gate dielectric layer
Include SiO2.Preferably, it is additionally provided with passivation layer on the grid.Preferably, the substrate includes N+Substrate.The p-well region, N+
Area and P+Area is formed in the epitaxial layer by ion implanting mode.
It is provided with an at least hexagon groove on the wafer epitaxial layer, and constitutes the six of the hexagon ditch groove groove wall
At least one of a face face has { the 1 of at least one line and hexagonal phase SiC crystal with the intersection of the epi-layer surface00}
Crystal face or { 110 } crystal face is parallel, to utilize the specific properties in the two faces.Wherein, Fig. 8 shows the cell wall of hexagon groove
It is parallel to { 100 } crystal face or { 110 } structural schematic diagram of crystal face, Fig. 9 show the cell wall of hexagon groove and the friendship on surface
Line is parallel to { 100 } crystal face or { 110 } structural schematic diagram of crystal face.
Specifically, Fig. 4 a and Fig. 4 b, which are respectively illustrated in an exemplary embodiments of the invention, is based on { 100 } crystal face
The vertical view and sectional view of UMOSFET devices；Fig. 5 a and Fig. 5 b are respectively illustrated in an exemplary embodiments of the invention and are based on { 11
0 } vertical view and sectional view of the UMOSFET devices of crystal face.
All illustrate for the hexagon groove structure of faceted pebble with part specifically, Figure 10 a and Figure 10 b respectively illustrate cell wall
Figure.
Preferably, the UMOSFET devices include a plurality of hexagon groove arrays.Wherein, Fig. 7 a and Fig. 7 b are shown
It is based on { 1 in an exemplary embodiments of the invention00 } crystal face or { 110 } the hexagon groove array schematic diagram of crystal face.
By above-described embodiment it can be found that crystal face is corrected to { 1 by the present invention by the method for oxidizing process and wet etching00 } crystal face or { 110 } crystal face, can to avoid wafer in cutting crystal orientation drift angle existing for caused epitaxial layer to device
Influence caused by energy；And obtained UMOSFET devices are based on the hexagonal phase SiC wafers of (0001) face extension, can utilize { 100}
{ 110 } mobility characteristics of crystal face and its equivalent crystal planes, to improve the performance of device.
The technology contents and technical characteristic of the present invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention, therefore, the scope of the present invention in teachings of the present invention and announcement
It should be not limited to the revealed content of embodiment, and should include various replacements and modification without departing substantially from the present invention, and be this patent Shen
Please claim covered.
Claims (10)
1. a kind of hexagonal phase SiC wafers of (0001) face extension, it is characterised in that：The epi-layer surface of the wafer be formed with to
A few polygon groove, and at least one of multiple faces for constituting polygon ditch groove groove wall face and the epitaxial layer
There are at least one line and hexagonal phase SiC crystal in the intersection on surfaceCrystal face orCrystal face is parallel.
2. the hexagonal phase SiC wafers of (0001) face according to claim 1 extension, it is characterised in that：It constitutes described polygon
At least one of multiple faces of shape ditch groove groove wall face is hexagonal phase SiC crystalCrystal face orCrystal face；With/
Or, the polygon groove includes hexagon groove and/or rectangular grooves.
3. a kind of UMOSFET devices, it is characterised in that including：
(0001) the hexagonal phase SiC wafers of face extension, epi-layer surface is formed at least one polygon groove, and constitutes
There is at least one line at least one of multiple faces of polygon ditch groove groove wall face with the intersection of the epi-layer surface
With hexagonal phase SiC crystalCrystal face orCrystal face is parallel, while the epitaxial layer also includes p-well region, N+Area
And P+Area；
The gate dielectric layer at least covering the polygon ditch groove groove wall, the grid being arranged on the gate dielectric layer and with it is described
The source electrode of wafer connection, drain electrode.
4. UMOSFET devices as claimed in claim 3, it is characterised in that：Constitute multiple faces of the polygon ditch groove groove wall
At least one of face be hexagonal phase SiC crystalCrystal face orCrystal face；And/or the polygon groove packet
Include hexagon groove and/or rectangular grooves.
5. UMOSFET devices as claimed in claim 3, it is characterised in that：The wafer further includes substrate, the epitaxial layer shape
At over the substrate, on said epitaxial layer there, the drain electrode is arranged on the substrate floor for the source electrode setting；It is preferred that
, the source electrode is arranged around the notch of the polygon groove；Preferably, the material of the gate dielectric layer includes SiO2；It is excellent
Choosing, it is additionally provided with passivation layer on the grid.
6. UMOSFET devices as claimed in claim 3, it is characterised in that：The p-well region, N+Area and P+Area is noted by ion
Enter mode to be formed in the epitaxial layer.
7. a kind of processing method of the hexagonal phase SiC wafers of (0001) face extension, it is characterised in that including：
It processes to form an at least polygon groove in the epi-layer surface of the hexagonal phase SiC wafers of (0001) face extension, and makes structure
At at least one face of the polygon ditch groove groove wall perpendicular to (0001) face silicon carbide epitaxial wafer surface；
At least one of multiple faces to composition polygon ditch groove groove wall face carries out crystal face correction and keeps this at least one
There are at least one line and hexagonal phase SiC crystal in the intersection of face and the epi-layer surfaceCrystal face orCrystal face
It is parallel.
8. processing method according to claim 7, it is characterised in that including：To constituting the more of the polygon ditch groove groove wall
At least one of a face face carries out crystal face correction and at least one face is made to be hexagonal phase SiC crystalCrystal face orCrystal face.
9. processing method according to claim 7 or 8, it is characterised in that including：
At least through dry etching mode the epi-layer surface of the hexagonal phase SiC wafers of (0001) face extension process to be formed it is described
Polygon groove；
And/or it at least selects in the multiple faces of oxidizing process and/or wet etching mode to constituting the polygon ditch groove groove wall
At least one face carries out the crystal face correction；
Preferably, oxidation processes first are carried out at least one of multiple faces of composition polygon ditch groove groove wall face, later
Wet etching is carried out, to complete the crystal face correction；
Preferably, the polygon groove includes hexagon groove and/or rectangular grooves.
10. the production method of any one of the claim 3-6 UMOSFET devices, it is characterised in that including：
(1) processing method described in any one of claim 7-9 is used to carry out the hexagonal phase SiC wafers of (0001) face extension
Processing；
(2) the wafer manufacturing UMOSFET devices are based on；
Preferably, step (2) specifically includes：
Patterned injection mask is set in the epi-layer surface of the wafer, and by ion implanting mode in the epitaxial layer
Interior formation p-well region, N+Area and P+Area, later high-temperature annealing activation implanted dopant；
Gate oxide is formed on less than the cell wall of the polygon groove；
In forming patterned highly doped polysilicon gate on the gate oxide；
In forming continuous passivation layer on the grid and at least regional area of the epi-layer surface；
Source electrode is made on said epitaxial layer there, and source electrode is made to expose from passivation layer；
Drain electrode is made on the substrate floor of the wafer.
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