CN102842581B - Memory structure and manufacturing method thereof - Google Patents
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- CN102842581B CN102842581B CN201110183996.0A CN201110183996A CN102842581B CN 102842581 B CN102842581 B CN 102842581B CN 201110183996 A CN201110183996 A CN 201110183996A CN 102842581 B CN102842581 B CN 102842581B
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Abstract
The invention relates to a memory structure and a manufacturing method thereof. The memory structure comprises memory cells, and each memory cell is characterized in that a first grid is arranged on a base; a stacking structure comprises a first dielectric structure arranged on the first grid, a channel layer, a second dielectric structure, a second grid, a first electric charge storing structure arranged in the first dielectric structure, and a second electric charge storing structure arranged in the second dielectric structure; at least one of the first electric charge storing structure and the second electric charge storing structure comprises two electric charge storing units separately arranged on a solid body; the first dielectric layer is arranged on the first grid on the both sides of the stacking structure; and a first source and a drain as well as a second source and another drain are arranged on the first dielectric layer, and are respectively located on the both sides of the channel layer. Therefore, the memory structure can overcome a reading error caused by a second bit effect and reduce programmed interference caused by secondary thermal electrons.
Description
Technical field
The present invention relates to a kind of memory structure and manufacture method thereof, particularly relate to a kind of memory structure and the manufacture method thereof with the electric charge storage unit that multiple entity is separated.
Background technology
Memory body is the semiconductor element that design is used for storing information or data.When the function of computer microprocessor becomes more and more stronger, the program that software carries out and computing also increase thereupon.Therefore, the capacity requirement of memory body is also just more and more higher.In various memory body product, non-volatility memory, such as erasable except programmable read-only memory (Electrically Erasable ProgrammableRead Only Memory, EEPROM) allow documentor repeatedly, reading and erase operation, even and if the data wherein stored still can preserve after memory body is de-energized.Based on above-mentioned advantage, erasablely become a kind of memory body that PC and electronic equipment extensively adopt except programmable read-only memory.
Typically erasable except and programmable read-only memory is the polysilicon that adulterates makes floating grid (floating gate) and control gate (control gate).When memory body carries out sequencing (program), the electrons injecting floating grid is uniformly distributed among whole polysilicon floating gate.But, when the tunnel oxide defectiveness below polysilicon floating gate exists, just easily cause the leakage current of element, affect the reliability of element.
Therefore, in order to solve the erasable problem except programmable read-only memory leakage current, current existing a kind of known method adopts the grid structure containing idioelectric electric charge storage layer to replace polysilicon floating gate.Another advantage replacing polysilicon floating gate with electric charge storage layer is, when software programs, only electronics can be stored in locally in the electric charge storage layer above close to source electrode or drain electrode.Therefore, when carrying out sequencing, voltage can be applied respectively to the source area of stack type grid one end and control gate, and produce the electronics of Gaussian Profile in close to the electric charge storage layer of source area, and also can apply voltage to the drain region of stack type grid one end and control gate respectively, and produce the electronics of Gaussian Profile in close to the electric charge storage layer of drain region.So, by the voltage that source/drain regions applies changing control gate and its both sides, two groups have the electronics of Gaussian Profile, single group has Gaussian Profile electronics can be there is or there is not electronics among single electric charge storage layer.Therefore, this kind replaces the fast flash memory bank of floating grid with electric charge storage layer, and can write four kinds of states among single memory cell, be the fast flash memory bank that one single memory cell two bit (2bits/cell) stores.
But, along with the increase of semiconductor element integration (integrity), the size of non-volatility memory also constantly micro.Because the micro of grid length (gate length) makes two, the left and right electric charge storage unit in same memory cell more and more close, and cause the problem of serious second bit effect (secondbit effect), therefore easily produce read error.In addition, due to the micro of source area and drain region, the second heat electronics (secondary hot electron) making source area and drain region not stop the memory cell selected by sequencing to produce, thus cause second heat to be electronically injected in adjacent memory cell, and then the problem of generating routineization interference (program disturbance), thus reduce the reliability of memory cell.
As can be seen here, above-mentioned existing memory structure and manufacture method thereof, in product structure, manufacture method and use, obviously still have inconvenience and defect, and are urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development always, and common product and method do not have appropriate structure and method to solve the problem, this is obviously the anxious problem for solving of relevant dealer.Therefore how to found a kind of new memory structure and manufacture method thereof, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
Object of the present invention is, overcome the defect that existing memory structure exists, and provide a kind of new memory structure, technical problem to be solved makes it can solve the read error caused by second bit effect, is very suitable for practicality.
Another object of the present invention is to, overcome the defect that existing memory structure exists, and a kind of manufacture method of new memory structure is provided, technical problem to be solved is the sequencing interference making it reduce to be caused by second heat electron institute, thus is more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of memory structure that the present invention proposes, comprise memory cell, and memory cell comprises following component.First grid is arranged in substrate.Stacked structure comprises the first dielectric structure be arranged on first grid, channel layer, the second dielectric structure and second grid, is arranged at the first charge storing structure in the first dielectric structure and is arranged at the second charge storing structure in the second dielectric structure.Wherein, the first charge storing structure and at least one in the second charge storing structure comprise two electric charge storage units entity being separated setting.First dielectric layer is arranged on the first grid of stacked structure both sides.First source electrode and drain electrode and the second source electrode and drain electrode to be arranged on the first dielectric layer and to be positioned at the both sides of channel layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid memory structure, the first wherein said charge storing structure and the second charge storing structure are such as all two electric charge storage units entity being separated setting.
Aforesaid memory structure, the first wherein said charge storing structure is such as single electric charge storage unit, and the second charge storing structure is such as two electric charge storage units entity being separated setting.
Aforesaid memory structure, the first wherein said charge storing structure is such as two electric charge storage units entity being separated setting, and the second charge storing structure is such as single electric charge storage unit.
Aforesaid memory structure, wherein when memory structure comprises multiple memory cell, the stacking setting of these memory cells.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of a kind of memory structure proposed according to the present invention, comprises the following steps.First, substrate forms first grid.Then, stacked structure is formed over the first gate, of a first.Stacked structure comprises the first dielectric structure be arranged on first grid, channel layer, the second dielectric structure and second grid, is arranged at the first charge storing structure in the first dielectric structure and is arranged at the second charge storing structure in the second dielectric structure.Wherein, the first charge storing structure comprises two the first electric charge storage units entity being separated setting, and the second charge storing structure comprises two the second electric charge storage units entity being separated setting.Then, the first grid of stacked structure both sides forms the first dielectric layer.Next, the first dielectric layer is formed first source electrode of position in channel layer both sides and drain electrode and the second source electrode and drain electrode.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid memory structure, the formation method of wherein said first grid is such as ionic-implantation or chemical vapour deposition technique.
The manufacture method of aforesaid memory structure, the formation method of wherein said stacked structure can comprise the following steps.First, the second dielectric materials layer, semiconductor material layer, the 3rd dielectric materials layer and gate material layers is sequentially formed over the first gate, of a first.Then, patterning second dielectric materials layer, semiconductor material layer, the 3rd dielectric materials layer and gate material layers, and sequentially form the second dielectric layer, channel layer, the 3rd dielectric layer and second grid over the first gate, of a first.Then, remove the two side portions of the second dielectric layer and the two side portions of the 3rd dielectric layer, and between channel layer and first grid, form two the first openings, and form two the second openings between second grid and channel layer.Next, the surface of the surface of the first opening and the second opening forms the 4th dielectric layer.Afterwards, on the 4th dielectric layer, formation is inserted the first electric charge storage unit of the first opening and is inserted the second electric charge storage unit of the second opening.
The manufacture method of aforesaid memory structure, the first wherein said source electrode and the formation method of drain electrode and the second source electrode and drain electrode can comprise the following steps.First, the first dielectric layer forms conductor layer, and conductor layer covers stacked structure.Then, remove segment conductor layer, and form the first source electrode and drain electrode and the second source electrode and drain electrode that are positioned at channel layer both sides, and the first source electrode and drain electrode, the second source electrode are such as identical in fact with drain electrode and the thickness of channel layer.
The manufacture method of aforesaid memory structure, more can be included in the first source electrode and drain electrode and the second source electrode and form with drain electrode is upper the 5th dielectric layer being positioned at second grid both sides.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, memory structure of the present invention and manufacture method thereof at least have following advantages and beneficial effect:
The memory structure that the present invention proposes comprises two electric charge storage units entity being separated setting due to the first charge storing structure and at least one in the second charge storing structure, therefore can solve the read error caused by second bit effect, and the sequencing interference caused by second heat electron institute can be reduced.
In addition, the manufacture method of of the present invention the memory structure proposed can be integrated with current technology, therefore, it is possible to effectively reduce process complexity.
In sum, the invention relates to a kind of memory structure and manufacture method thereof.This memory structure, comprises memory cell, and memory cell comprises following component.First grid is arranged in substrate.Stacked structure comprises the first dielectric structure be arranged on first grid, channel layer, the second dielectric structure and second grid, is arranged at the first charge storing structure in the first dielectric structure and is arranged at the second charge storing structure in the second dielectric structure.Wherein, the first charge storing structure and at least one in the second charge storing structure comprise two electric charge storage units entity being separated setting.First dielectric layer is arranged on the first grid of stacked structure both sides.First source electrode and drain electrode and the second source electrode and drain electrode to be arranged on the first dielectric layer and to be positioned at the both sides of channel layer.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to Fig. 1 H is the profile of the manufacturing process of the memory structure of the first embodiment of the present invention.
Fig. 2 is the vertical view of Fig. 1 H
Fig. 3 and Fig. 4 is the profile of the memory structure of the second embodiment of the present invention and the 3rd embodiment respectively.
Fig. 5 is the profile of the memory structure of the fourth embodiment of the present invention.
100: substrate
102,118: grid
104: dielectric materials layer
106: semiconductor material layer
108,124,140,158: dielectric materials layer
110: gate material layers
112,116,142,148,160: dielectric layer
114: channel layer
120,122: opening
126: charge storage layers
128,130,132,134: electric charge storage unit
136,136 ', 138,138 ': charge storing structure
144,144 ', 146,146 ': dielectric structure
150: stacked structure
152: conductor layer
154,156: source electrode and drain electrode
162: connect wire
164: character line
166: memory cell
168: isolation structure
170: passage leading-out wire
172,174,176,178: dielectric layer
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to the memory structure proposed according to the present invention and its embodiment of manufacture method, structure, method, step, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can know and present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, should to the present invention for the technological means reaching predetermined object and take and effect obtain one more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the present invention.
Figure 1A to Fig. 1 H is the profile of the manufacturing process of the memory structure of the first embodiment of the present invention.
Refer to shown in Figure 1A, first, substrate 100 forms grid 102.Grid 102 is such as N-type doped region, and substrate 100 is such as the substrate of P type.The grid 102 of N-type is contrary dopant profile with the substrate 100 of P type, therefore has effect that block charge circulates betwixt.In another embodiment, substrate 100 also can have the p type wells district (not illustrating) in N-type wellblock (not illustrating), and grid 102 is formed in the p type wells district of substrate 100.When grid 102 is N-type doped region, the formation method of grid 102 is such as utilize ionic-implantation to implant admixture in substrate 100 formed.
In another embodiment, grid 102 can be doped polycrystalline silicon grid.When grid 102 is doped polycrystalline silicon grid, more can be formed in be formed between substrate 100 and grid 102 and isolates dielectric layer, to isolate substrate 100 and grid 102.
Then, grid 102 is sequentially formed dielectric materials layer 104, semiconductor material layer 106, dielectric materials layer 108 and gate material layers 110.The material of dielectric materials layer 104 is such as silica.The material of semiconductor material layer 106 is such as crystal silicon of heap of stone, polysilicon or amorphous silicon.The material of dielectric materials layer 108 is such as silica.The material of gate material layers 110 is such as the conductor material such as doped polycrystalline silicon or metal.Dielectric materials layer 104, semiconductor material layer 106, dielectric materials layer 108 are such as chemical vapour deposition technique or physical vaporous deposition with the formation method of gate material layers 110.
Then, refer to shown in Figure 1B, patterned dielectric material layer 104, semiconductor material layer 106, dielectric materials layer 108 and gate material layers 110, and on grid 102, sequentially form dielectric layer 112, channel layer 114, dielectric layer 116 and grid 118.Dielectric materials layer 104, semiconductor material layer 106, dielectric materials layer 108 and the patterning method of gate material layers 110 are such as carry out lithography process and etch process to above-mentioned rete and formed.
Next, refer to shown in Fig. 1 C, remove the two side portions of dielectric layer 112 and the two side portions of dielectric layer 116, and between channel layer 114 and grid 102, form opening 120, and form opening 122 between grid 118 and channel layer 114.Part of dielectric layer 112 is such as wet etching with the removing method of part of dielectric layer 116.
Afterwards, refer to shown in Fig. 1 D, the surface of grid 102, dielectric layer 112, channel layer 114, dielectric layer 116 and grid 118 forms dielectric materials layer 124.The material of dielectric materials layer 124 is such as silica.The formation method of dielectric materials layer 124 is such as thermal oxidation method.
Subsequently, dielectric materials layer 124 is formed the charge storage layers 126 filling up opening 120 and opening 122.The material of charge storage layers 126 is such as silicon nitride, doped polycrystalline silicon or nanocrystal.The formation method of charge storage layers 126 is such as chemical vapour deposition technique.
Then, refer to shown in Fig. 1 E, remove and be positioned at the outside charge storage layers 126 with being positioned at opening 122 outside of opening 120, and formation is inserted the electric charge storage unit 128,130 of opening 120 and inserts the electric charge storage unit 132,134 of opening 122 on dielectric materials layer 124.In this embodiment, electric charge storage unit 128,130 is set forms charge storing structure 136 by entity is separated, and electric charge storage unit 132,134 is set by separation on entity forms charge storing structure 138.The removing method of Partial charge storage material layer 126 is such as that dry type erosion is excuted a law, the combination of wet etching or said method.
Then, dielectric materials layer 140 is formed on the surface at dielectric materials layer 124.The material of dielectric materials layer 140 is such as silica.The formation method of dielectric materials layer 140 is such as chemical vapour deposition technique.
Then, refer to shown in Fig. 1 F, remove and be positioned at outside dielectric materials layer 140 and the dielectric materials layer 124 with being positioned at opening 122 outside of opening 120, be positioned at dielectric materials layer 124 above grid 102 and dielectric materials layer 140 outside to stay with opening 122 outside of opening 120 and form dielectric layer 148, and form dielectric layer 142 by the dielectric materials layer 124 on the surface on the surface and opening 122 that are positioned at opening 120.Part dielectric materials layer 140 is such as dry etching method with the removing method of part dielectric materials layer 124.Now, part dielectric materials layer 124 may be had and part dielectric materials layer 140 remains in above grid 118.
Wherein, the dielectric layer 142 being positioned at opening 120 surface forms dielectric structure 144 with dielectric layer 112, can in order to isolate the electric charge storage unit 128,130 in charge storing structure 136, and charge storing structure 136 can be made to isolate with channel layer 114 and grid 102.The dielectric layer 142 being positioned at opening 122 surface forms dielectric structure 146 with dielectric layer 116, can in order to isolate the electric charge storage unit 132,134 in charge storing structure 138, and charge storing structure 138 can be made to isolate with channel layer 114 and grid 118.
In addition, by dielectric structure 144, channel layer 114, dielectric structure 146 and grid 118, be arranged at the charge storing structure 136 in dielectric structure 144 and be arranged at charge storing structure 138 in dielectric structure 146 and form the stacked structure 150 be arranged on grid 102.Although stacked structure 150 makes with said method, but the manufacture method of stacked structure 150 and wherein each component is not as limit.
In addition, be positioned at the dielectric layer 148 on the grid 102 of stacked structure 150 both sides, be formed at source electrode on dielectric layer 148 and drain electrode in order to isolated gate 102 with follow-up.As long as the thickness of dielectric layer 148 can be formed at the source electrode on dielectric layer 148 with follow-up and drain in order to isolated gate 102.For example, the thickness of dielectric layer 148 is such as the thickness approximating dielectric structure 144.
Next, dielectric layer 148 forms conductor layer 152, and conductor layer 152 covers stacked structure 150.The material of conductor layer 152 is such as doped polycrystalline silicon or metal.The formation method of conductor layer 152 is such as chemical vapour deposition technique.
Afterwards, refer to shown in Fig. 1 G, remove segment conductor layer 152, and form the source electrode and drain electrode 154 and source electrode and drain electrode 156 that are positioned at channel layer 114 both sides, and source electrode and drain electrode 154, source electrode and drain electrode 156 are such as identical in fact with the thickness of channel layer 114.The removing method of segment conductor layer 152 is such as dry etching method.Now, the conductor layer 152 be positioned on channel layer 114 sidewall can be removed, to prevent grid 118 and source electrode and drain electrode 154 and source electrode and drain electrode 156 mutual conduction.In addition, segment conductor layer 152 may be had to remain on dielectric materials layer 140.
Moreover, dielectric materials layer 158 can be formed on source electrode with drain electrode 154 and source electrode and drain electrode 156, and dielectric materials layer 158 covers stacked structure 150.The material of dielectric materials layer 158 is such as silica.The formation method of dielectric materials layer 158 is such as chemical vapour deposition technique.
Subsequently, refer to shown in Fig. 1 H, remove part dielectric materials layer 158, until expose grid 118, to form the dielectric layer 160 being positioned at grid 118 both sides on source electrode with drain electrode 154 and source electrode and drain electrode 156.While removing part dielectric materials layer 158, the dielectric materials layer 124, dielectric materials layer 140 and the conductor layer 152 remained on dielectric materials layer 140 that are positioned at above grid 118 can be removed in the lump.Part dielectric materials layer 158, dielectric materials layer 140, dielectric materials layer 124 are such as chemical mechanical milling methods with the removing method of the segment conductor layer 152 remained on dielectric materials layer 140.
Then, can be formed on grid 118 and connect wire 162, and grid 118 be connected wire 162 and form character line 164.The formation method connecting wire 162 is such as first utilize chemical vapour deposition technique on grid 118, form conductor layer (not illustrating), is formed carrying out patterning to conductor layer.The material of conductor layer is such as doped polycrystalline silicon or metal.
Based on above-mentioned known, the manufacture method of the memory structure that above-described embodiment proposes can be integrated with current technology, therefore effectively can reduce process complexity.
Below, by Fig. 1 H, the memory structure that the first embodiment proposes is described.Fig. 2 is the vertical view of Fig. 1 H, and Fig. 1 H is also the profile along I-I ' hatching in Fig. 2 simultaneously.
Shown in Fig. 1 H and Fig. 2, memory structure comprises memory cell 166.Each memory cell 166 comprises grid 102, stacked structure 150, dielectric layer 148, source electrode and drain electrode 154 and source electrode and drain electrode 156.In addition, memory structure more can comprise dielectric layer 160, connect wire 162 and passage leading-out wire 170.Connect wire 162 in order to connect the grid 118 in stacked structure 150, and form character line 164.Isolation structure 168 is utilized to isolate between character line 164.Wherein, a corresponding character line formed by grid 102 of character line 164, and between the character line formed by grid 102, utilize isolation structure (not illustrating) to isolate.Character line 164 can not need to aim at the character line formed by grid 102.Passage leading-out wire 170 is connected to channel layer 114, the electric hole accumulated in channel layer 114 can be derived, to prevent floating matrix effect (floating-body effect), and then the current potential because of channel layer is avoided to improve and the problem of not easily sequencing.The material of passage leading-out wire 170 is such as the conductor materials such as metal.In addition, the configuration mode of other components in memory structure, material, manufacture method and effect have carried out at large illustrating in the above-described embodiments, therefore do not repeat them here.
Known based on above-described embodiment, arrange due to electric charge storage unit 128,130 entity in charge storing structure 136 being separated, and electric charge storage unit 132,134 entity in charge storing structure 138 is separated arranges, so when grid length carries out micro, can prevent from producing second bit effect between two, the left and right electric charge storage unit 128,130 (or 132,134) in memory cell 166, therefore can avoid producing read error.In addition, arrange due to electric charge storage unit 128,130 entity in charge storing structure 136 being separated, and electric charge storage unit 132,134 entity in charge storing structure 138 is separated arranges, so when source electrode and drain electrode 154,156 micro, second heat can be reduced and be electronically injected to quantity in adjacent memory cell 166, and then reduce the problem of sequencing interference, and promote the reliability of memory cell.
Below, the method for operation of the memory structure that the first embodiment proposes is described by Fig. 1 H.
When carrying out programming operations to the electric charge storage unit 134 in memory cell 166, the first voltage can be applied, apply the second voltage at grid 102, apply tertiary voltage in source electrode and drain electrode 154 and apply the 4th voltage at source electrode and drain electrode 156 at grid 118, wherein the first voltage is greater than the second voltage, and the 4th voltage is greater than tertiary voltage.First voltage is such as 11V, the second voltage is such as that 0V, tertiary voltage are such as 0V and the 4th voltage is such as 4V, but the operating voltage of programming operations of the present invention is not as limit.
When carrying out read operation to the electric charge storage unit 134 in memory cell 166, the 5th voltage can be applied, apply the 6th voltage at grid 102, apply the 7th voltage in source electrode and drain electrode 154 and apply the 8th voltage at source electrode and drain electrode 156 at grid 118, wherein the 5th voltage is greater than the 6th voltage, and the 7th voltage is greater than the 8th voltage.5th voltage is such as 3V, the 6th voltage is such as 0V, the 7th voltage is such as 1.6V and the 8th voltage is such as 0V, but the operating voltage of read operation of the present invention is not as limit.
When carrying out erase operation to the electric charge storage unit 134 in memory cell 166, can apply the 9th voltage, apply the tenth voltage at grid 102, apply the 11 voltage and 156 apply the 12 voltage at source electrode with draining in source electrode and drain electrode 154 at grid 118, wherein the tenth voltage is greater than the 9th voltage, the 12 voltage is greater than the 11 voltage and the 9th voltage and the 12 voltage electrical contrary.9th voltage is such as-6V, the tenth voltage is such as 0V, the 11 voltage is such as 0V and the 12 voltage is such as 4V, but the operating voltage of erase operation of the present invention is not as limit.
In addition, the technical staff having usual knowledge in this technical field can learn the mode of operation to the electric charge storage unit 128,130,134 in memory cell 166 with reference to the method for operation disclosed by above-described embodiment, therefore does not repeat them here.
Fig. 3 and Fig. 4 be respectively the present invention the second embodiment and the profile of memory structure of the 3rd embodiment.
In a first embodiment, memory structure is respectively for the charge storing structure 136,138 in memory cell 166 two electric charge storage units 128,130 and 132,134 entity being separated setting to be described.But scope of the present invention is not as limit, as long as namely at least one in charge storing structure 136,138 belongs to the scope that the present invention protects for two electric charge storage units entity being separated setting.
For example, referring to Fig. 1 H and Fig. 3, the difference of the memory structure in the first embodiment and the second embodiment is: in the memory structure of the second embodiment, charge storing structure 136 ' is single electric charge storage unit, and dielectric structure 144 ' comprises dielectric layer 172 and dielectric layer 174, its dielectric layer 172 is arranged between grid 102 and charge storing structure 136 ', and dielectric layer 174 is arranged between charge storing structure 136 ' and channel layer 114.The material of charge storing structure 136 ' is such as silicon nitride, doped polycrystalline silicon or nanocrystal.Dielectric layer 172 is such as silica with the material of dielectric layer 174 respectively.Other components in second embodiment are similar to the first embodiment, therefore do not repeat them here.
In addition, shown in Fig. 1 H and Fig. 4, the difference of the memory structure in the first embodiment and the 3rd embodiment is: in the memory structure of the 3rd embodiment, charge storing structure 138 ' is single electric charge storage unit, and dielectric structure 146 ' comprises dielectric layer 176 and dielectric layer 178, its dielectric layer 176 is arranged between channel layer 114 and charge storing structure 138 ', and dielectric layer 178 is arranged between charge storing structure 138 ' and grid 118.The material of charge storing structure 138 ' is such as silicon nitride, doped polycrystalline silicon or nanocrystal.Dielectric layer 176 is such as silica with the material of dielectric layer 178 respectively.Other components in 3rd embodiment are similar to the first embodiment, therefore do not repeat them here.
Fig. 5 is the profile of the memory structure of the fourth embodiment of the present invention.
The difference of the memory structure in the first embodiment and the 4th embodiment is: the memory structure in the 4th embodiment has multiple memory cells 166 of stacking setting, and vertically adjacent two memory cells 166 share a character line.Other components in 4th embodiment are similar to the first embodiment, therefore do not repeat them here.
In the fourth embodiment, because memory structure has multiple memory cells 166 of stacking setting, the integration of memory cell can therefore be promoted further.
In sum, above-described embodiment at least has following advantages:
1. the memory structure that above-described embodiment proposes can solve the read error caused by second bit effect, and can reduce the sequencing interference caused by second heat electron institute.
2. the manufacture method of memory structure that above-described embodiment proposes can be integrated with current technology, therefore, it is possible to effectively reduce process complexity.
3. the memory structure that above-described embodiment proposes can promote the integration of memory cell further.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when the method and technology contents that can utilize above-mentioned announcement are made a little change or be modified to the Equivalent embodiments of equivalent variations, in every case be the content not departing from technical solution of the present invention, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (7)
1. a memory structure, it is characterized in that it comprises a memory cell, this memory cell comprises:
One first grid, is arranged in a substrate;
Stacked arrangement, comprising:
Be arranged at one first dielectric structure on this first grid, a channel layer, one second dielectric structure and a second grid;
One first charge storing structure, is arranged in this first dielectric structure; And
One second charge storing structure, is arranged in this second dielectric structure, and wherein this first charge storing structure and at least one in this second charge storing structure comprise two electric charge storage units entity being separated setting;
One first dielectric layer, is arranged on this first grid of these stacked structure both sides; And
One first source electrode and drain electrode and one second source electrode and drain electrode, to be arranged on this first dielectric layer and to be positioned at the both sides of this channel layer.
2. memory structure method according to claim 1, is characterized in that wherein when this memory structure comprises multiple memory cell, the stacking setting of those memory cells.
3. a manufacture method for memory structure, is characterized in that it comprises the following steps:
A substrate is formed a first grid;
This first grid forms stacked arrangement, and this stacked structure comprises:
Be arranged at one first dielectric structure on this first grid, a channel layer, one second dielectric structure and a second grid;
One first charge storing structure, is arranged in this first dielectric structure, and comprises two the first electric charge storage units entity being separated setting; And
One second charge storing structure, is arranged in this second dielectric structure, and comprises two the second electric charge storage units entity being separated setting;
This first grid of these stacked structure both sides forms one first dielectric layer; And
This first dielectric layer is formed one first source electrode of position in these channel layer both sides and drain electrode and one second source electrode and drain electrode.
4. the manufacture method of memory structure according to claim 3, is characterized in that the formation method of wherein said first grid comprises ionic-implantation or chemical vapour deposition technique.
5. the manufacture method of memory structure according to claim 3, is characterized in that the formation method of wherein said stacked structure comprises:
This first grid is sequentially formed one second dielectric materials layer, semiconductor material layer, one the 3rd dielectric materials layer and a gate material layers;
This second dielectric materials layer of patterning, this semiconductor material layer, the 3rd dielectric materials layer and this gate material layers, and on this first grid, sequentially form one second dielectric layer, this channel layer, one the 3rd dielectric layer and this second grid;
Remove the two side portions of this second dielectric layer and the two side portions of the 3rd dielectric layer, and between this channel layer and this first grid, form two the first openings, and between this second grid and this channel layer, form two the second openings;
The surface of the surface of those the first openings and those the second openings forms one the 4th dielectric layer; And
4th dielectric layer is formed and inserts those first electric charge storage units of those the first openings and insert those second electric charge storage units of those the second openings.
6. the manufacture method of memory structure according to claim 3, is characterized in that the formation method of the first wherein said source electrode and drain electrode and this second source electrode and drain electrode comprises:
This first dielectric layer forms a conductor layer, and this conductor layer covers this stacked structure; And
Remove this conductor layer of part, and form this first source electrode and drain electrode and this second source electrode and drain electrode of being positioned at these channel layer both sides, and this first source electrode is identical in fact with the thickness of this channel layer with drain electrode, this second source electrode and drain electrode.
7. the manufacture method of memory structure according to claim 3, is characterized in that being more included in this first source electrode and drain electrode and this second source electrode forms with drain electrode is upper one the 5th dielectric layer being positioned at these second grid both sides.
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| US7512012B2 (en) * | 2007-04-30 | 2009-03-31 | Macronix International Co., Ltd. | Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory |
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