CN102437163A

CN102437163A - CMOS (Complementary Metal Oxide Semiconductor) structure of wide forbidden band material on insulator and preparation method thereof

Info

Publication number: CN102437163A
Application number: CN2011102502437A
Authority: CN
Inventors: 黄晓橹; 刘格致; 陈玉文
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2011-08-29
Filing date: 2011-08-29
Publication date: 2012-05-02

Abstract

The invention discloses a CMOS (Complementary Metal Oxide Semiconductor) structure of a wide forbidden band material on an insulator. A PMOS (P-channel Metal Oxide Semiconductor) transistor and an NMOS (N-channel Metal Oxide Semiconductor) transistor share a grid region, and after a source region and a drain region of the NMOS transistor are subjected to ion doping implantation, a forbidden band of a semiconductor material for forming the source region and the drain region of the NMOS transistor is wider than the forbidden band of silicon. In the invention, through introducing SiC to the source/drain end of the NMOS transistor, the hole potential barrier of a bypass PN junction is enlarged, and the bypass drain current is greatly reduced; and meanwhile, the threshold voltage of an NMOS cannot be influenced, in addition, SiC is used at the source/drain end of the NMOS, and tensile stress exists in the channel direction, thus, the electron mobility can be effectively increased, and the performance of the NMOS is further improved.

Description

Wide-band gap material CMOS structure and preparation method thereof on the insulator

Technical field

The present invention relates to the ic manufacturing technology field, relate in particular to wide-band gap material CMOS structure and preparation method thereof on a kind of insulator.

Background technology

MOSFET has two kinds of P raceway groove and N raceway grooves, and two types of depletion type MOS FET and enhancement mode MOSFET are arranged again among every kind of MOSFET, and the circuit of being made up of N raceway groove and two kinds of MOSFET of P raceway groove is called complementary MOS or cmos circuit.The CMOS inverter is to be composed in series by a P-channel enhancement type metal-oxide-semiconductor and a N channel enhancement metal-oxide-semiconductor; Usually P ditch deferent is as the load pipe, and N ditch deferent is as input pipe, and this configuration can significantly reduce power consumption; Because in two kinds of logic states; In two transistors one always ends, and because the resistance of CMOS inverter is relatively low, processing speed also can be improved.Fig. 1 shows the profile of CMOS inverter of the prior art, and is as shown in Figure 1, and PMOS and NMOS are arranged side by side on the horizontal direction of Fig. 1; Comprise Semiconductor substrate 000; In N type dopant well that separates with isolation structure 101 and P type dopant well 102, form PMOS and NMOS respectively, N type dopant well 101 both sides form P type source region/drain region 201; P type dopant well 102 both sides form N type source region/drain region 202,301 and 302 and represent gate electrode respectively.Fig. 2 shows the equivalent electric circuit of CMOS inverter structure shown in Figure 1; Wherein, The source electrode of PMOS and power line Vdd link together; The source electrode of NMOS and ground wire Vss link together, and the grid of PMOS and the grid of NMOS interconnect as input Vin, and the drain electrode of the drain electrode of PMOS and NMOS interconnects as output end vo ut.The basic functional principle of CMOS inverter is: when input high level, and the NMOS conducting, PMOS ends, output low level; Otherwise when input low level, NMOS ends, PMOS conducting, output high level.

Above-mentioned traditional CMOS inverter is a double pipe structure; China application CN101916762A discloses a kind of silicon-on-insulator CMOSFET tubular construction; Be that NMOS and PMOS share same grid; And both source drain terminals are separately along the crisscross layout of grid, and substrate is weak P type under the grid, and Fig. 3 a and Fig. 3 b show the embodiment sketch map of two kinds of domain structures of this cmos device respectively.Shown in figure; This CMOS structure comprises the PMOS transistor and the nmos pass transistor in common grid zone 10,10 '; Be furnished with the drain region 40,40 ' and the drain region 50,50 ' of NMOS of source region 30,30 ', the PMOS of source region 20,20 ', the NMOS of PMOS successively around area of grid 10,10 '; Above-mentioned area of grid 10,10 ',

source region

20,20 ', 30,30 ' and

drain region

40,40 ', 50,50 ' in be furnished with respectively corresponding gate electrode 100,100 ', source electrode 200,200 ', 300,300 ' with drain electrode 400,400 ', 500,500 ', and between above-mentioned each source region and the drain region and between each source region and the neighboring area, all be furnished with insulating spacer between each drain region and the neighboring area.PMOS transistor drain zone 40,40 ' with the drain region of nmos pass transistor 50,50 ' respectively through PMOS transistor drain electrode 400,400 ' and the drain electrode 500,500 ' of nmos pass transistor link together, be Vout; PMOS passes through transistorized source region 20,20 ' its source electrode 200,200 ' and connects power line Vdd, and its source electrode 300,300 ' earth connection Vss are passed through in the source region 30,30 ' of nmos pass transistor, and gate electrode 100,100 ' is input Vin.When grid voltage during greater than Vdd (being high level), the raceway groove transoid is the N type, and NMOS opens, and PMOS closes; When grid voltage was 0, PMOS opened, and NMOS closes, thereby forms a single tube inverter structure, can effectively increase the CMOS integration density.And, can increase channel length when the source of NMOS and PMOS drain terminal during separately along the crisscross layout of grid diagonal, suppress short-channel effect (SCE, Short Channel Effect).But should invention have a defective, promptly when grid added high level, NMOS opened; PMOS closes; But when substrate does not exhaust fully under this moment N type raceway groove, be the P type below, thereby P+ type source end (high level) the à P type that has the PMOS conductive channel of the N+ type source drain terminal (low level) of depletion region à NMOS not; Form bypass leakage stream If, device power consumption is increased.Because the preparation of ultra-thin top layer silicon type silicon-on-insulator is difficult to, be difficult to therefore guarantee that substrate exhausts fully.In order to overcome this defective; Chinese patent CN102005454A proposes a kind of method that reduces bypass leakage stream; Promptly leak two ends and inject than the bigger P type layer of compensation of substrate P-dopant dose, thereby increase bypass PN junction forward cut-in voltage, reduce bypass leakage stream through rake angle in the NMOS source; Reduce power consumption, but it is very limited to increase the effect of bypass PN junction forward cut-in voltage by this method.

Semiconductor material with wide forbidden band (being the semi-conducting material of energy gap Eg more than or equal to 2.3ev) is called as third generation semi-conducting material, mainly comprises diamond, SiC, GaN etc.Compare with the first generation, second generation semi-conducting material; It is big that third generation semi-conducting material has energy gap; The characteristics that the electron drift saturated velocity is high, dielectric constant is little, conduct electricity very well are highly suitable for making radioresistance, high frequency, high-power and superintegrated electronic device.

Summary of the invention

Problem to above-mentioned existence; The purpose of this invention is to provide wide-band gap material CMOS structure and preparation method thereof on a kind of insulator; Increase bypass PN junction hole potential barrier, reduced bypass leakage stream greatly, can not influence the threshold voltage of NMOS simultaneously again; Further improve the NMOS performance, power consumption is low.

The objective of the invention is to realize through following technical proposals:

Wide-band gap material CMOS structure on a kind of insulator comprises: be disposed in PMOS transistor and nmos pass transistor on the bottom insulator; The said nmos pass transistor common grid of said PMOS transistor AND gate zone; Said area of grid comprises the P type semiconductor material, is furnished with the drain region of the source region of the transistorized source region of said PMOS, said nmos pass transistor, said PMOS transistor drain zone and said nmos pass transistor successively around said area of grid; And said PMOS transistor drain zone links together through the drain electrode of said PMOS transistor drain electrode and said nmos pass transistor respectively with the drain region of said nmos pass transistor; The transistorized source region of said PMOS connects power line through its source electrode, and the source region of said nmos pass transistor is through its source electrode ground connection; Wherein, after the ion doping injection was carried out in the source region of said nmos pass transistor and drain region, the forbidden band of silicon was wider than in the forbidden band of the source region of formation nmos pass transistor and the semi-conducting material of drain region.

Wide-band gap material CMOS structure on the above-mentioned insulator, wherein, the ion of injection is a carbon ion, the source region of said formation nmos pass transistor and the semi-conducting material of drain region are wide-band gap material, and this wide-band gap material is SiC.

Wide-band gap material CMOS structure on the above-mentioned insulator; Wherein, Said PMOS transistor drain zone and source region lay respectively at the outside at a pair of diagonal angle of area of grid, and the drain region of said nmos pass transistor and source region lay respectively at another outside to the diagonal angle of area of grid.

Wide-band gap material CMOS structure on the above-mentioned insulator; Wherein, Said PMOS transistor drain zone and source region lay respectively at the outside of a pair of opposite side of area of grid, and the drain region of said nmos pass transistor and source region lay respectively at another outside to opposite side of area of grid.

Wide-band gap material CMOS structure on the above-mentioned insulator, wherein, between each said source region and the said drain region, between each said source region and the neighboring area and all be furnished with insulating spacer between each said drain region and the neighboring area.

A kind of preparation method like wide-band gap material CMOS structure on above-mentioned any described insulator wherein, comprises the following steps:

Be formed with buried insulator layer on one substrate and on this buried insulator layer, be formed with silicon substrate; Be formed with in inside fleet plough groove isolation structure the well region that silicon substrate comprised above growth oxide layer and polysilicon layer; Polysilicon layer is carried out etching form polysilicon gate; In well region, implant P type ion and form the source area drain region of PMOS, and in well region, implant the source area drain region that N type ion forms NMOS;

Apply photoresist and cover on silicon substrate and the grid, carry out photoetching process afterwards, in photoresist, form the source area of aligning NMOS and the opening of drain region;

Utilizing said opening to carry out the two-way carbon ion of rake angle injects; It is combined with silicon in the source area drain region of said nmos pass transistor; Make the source area drain region of nmos pass transistor near forming SiCx layer longitudinally under the grid after inject accomplishing, afterwards said oxide layer is carried out etching and only kept the gate oxide that is positioned at the grid below;

Remove photoresist, form the common grid zone of said PMOS transistor and said nmos pass transistor in the central region of said area of isolation.

The preparation method of wide-band gap material CMOS structure on the above-mentioned insulator, wherein, said silicon substrate is the P-type.

Compared with present technology, beneficial effect of the present invention is: through the drain terminal introducing use SiC in the source of nmos pass transistor, increase bypass PN junction hole potential barrier, reduce bypass leakage stream greatly; Can not influence simultaneously the threshold voltage of NMOS again, and drain terminal uses SiC because NMOS is in the source, has tensile stress (Tensile Stress) at channel direction, can effectively increase electron mobility, further improves the NMOS performance.

Description of drawings

Fig. 1 is the profile of CMOS inverter in the prior art;

Fig. 2 is the equivalent circuit diagram of CMOS inverter structure shown in Figure 1;

Fig. 3 a is the structure domain of the embodiment one of wide-band gap material CMOS structure on CMOS structure and the insulator of the present invention in the prior art;

Fig. 3 b is the structure domain of the embodiment two of wide-band gap material CMOS structure on CMOS structure and the insulator of the present invention in the prior art;

Fig. 4 is the structural representation when wide-band gap material CMOS structure is carried out the carbon ion injection on the insulator of the present invention;

Fig. 5 is the effect sketch map after wide-band gap material CMOS structure is accomplished on the insulator of the present invention.

Embodiment

Below in conjunction with schematic diagram and concrete operations embodiment the present invention is described further.

Embodiment one

Shown in Fig. 3 a, wide-band gap material CMOS structure comprises on the insulator of the present invention: the PMOS transistor and the nmos pass transistor that are disposed in silicon on the bottom insulator; PMOS transistor AND gate nmos pass transistor common grid zone 10; Area of grid 10 comprises the P type semiconductor material, is furnished with the drain region 50 of source region 30, PMOS transistor drain zone 40 and the nmos pass transistor of the transistorized source region of PMOS 20, nmos pass transistor successively around area of grid 10; And PMOS transistor drain zone 40 links together through the drain electrode 500 of PMOS transistor drain electrode 400 and nmos pass transistor respectively with the drain region 50 of nmos pass transistor; The transistorized source region 20 of PMOS connects power line through its source electrode 200, and the source region 30 of nmos pass transistor is through its source electrode 300 ground connection.PMOS transistor drain zone and source region lay respectively at the outside at a pair of diagonal angle of area of grid, and the drain region of NMOS and source region lay respectively at another outside to the diagonal angle of area of grid.Wherein, after the ion doping injection was carried out in the source region 30 and the drain region 50 of nmos pass transistor, the forbidden band of silicon was wider than in the forbidden band of the source region 30 of formation nmos pass transistor and the semi-conducting material of drain region 50.

Further, the ion of injection is a carbon ion, and constituting the source region of nmos pass transistor and the semi-conducting material of drain region is wide-band gap material, and this wide-band gap material is SiC.

Further, each

source region

20,30 and drain region 40, between 50, between each

source region

20,30 and the neighboring area and all be furnished with insulating spacer between each

drain region

40,50 and the neighboring area.

Embodiment two

Shown in Fig. 3 b, wide-band gap material CMOS structure comprises on the insulator of the present invention: the PMOS transistor and the nmos pass transistor that are disposed in silicon on the bottom insulator; PMOS transistor AND gate nmos pass transistor common grid zone 10 '; Area of grid 10 ' comprises the P type semiconductor material, is furnished with the drain region 50 ' of source region 30 ', PMOS transistor drain zone 40 ' and the nmos pass transistor of the transistorized source region of PMOS 20 ', nmos pass transistor successively around area of grid 10 '; And PMOS transistor drain zone 40 ' links together through the drain electrode 500 ' of PMOS transistor drain electrode 400 ' and nmos pass transistor respectively with the drain region 50 ' of nmos pass transistor; The transistorized source region 20 ' of PMOS connects power line through its source electrode 200 ', and the source region 30 ' of nmos pass transistor is through its source electrode 300 ' ground connection.PMOS transistor drain zone 40 ' and source region 20 ' lay respectively at the outside of a pair of opposite side of area of grid 10 ', and the drain region 50 ' and the source region 30 ' of nmos pass transistor lays respectively at another outside to opposite side of area of grid 10 '.

Further, the ion of injection is a carbon ion, and constituting the source region 30 ' of nmos pass transistor and the semi-conducting material of drain region 50 ' is wide-band gap material, and this wide-band gap material is SiC.

Further, each source region 20 ', 30 ' and drain region 40 ', between 50 ', each source region 20 ', 30 ' and the neighboring area between and each drain region 40 ', 50 ' and the neighboring area between all be furnished with insulating spacer.

The invention also discloses a kind of preparation method, wherein, comprise the following steps: like wide-band gap material CMOS structure on the insulator of above-mentioned embodiment one and embodiment two structures

Applying photoresist 0 covers on silicon substrate and the grid; Carry out photoetching process afterwards; As shown in Figure 4, in photoresist 0, form the source area of aligning NMOS and the opening of drain region, utilize opening to carry out the two-way carbon ion of rake angle and inject; It is combined with silicon in the source area drain region of nmos pass transistor; Make after inject accomplishing the source area drain region of nmos pass transistor near forming SiCx layer longitudinally under the grid, afterwards oxide layer carried out etching and only kept the gate oxide that is positioned at the grid below that the design sketch after the completion is as shown in Figure 5;

Remove photoresist, form the common grid zone of PMOS transistor and nmos pass transistor in the central region of area of isolation.

Further, silicon substrate is the P-type.

In sum, the present invention increases bypass PN junction hole potential barrier through the drain terminal introducing use SiC in the source of nmos pass transistor, reduces bypass leakage stream greatly; Can not influence simultaneously the threshold voltage of NMOS again, and drain terminal uses SiC because NMOS is in the source, has tensile stress at channel direction, can effectively increase electron mobility, further improves the NMOS performance.

More than specific embodiment of the present invention is described in detail, but the present invention is not restricted to the specific embodiment of above description, it is just as example.To those skilled in the art, any equivalent modifications that wide-band gap material CMOS structure and preparation method thereof on this insulator is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of having done under the spirit and scope of the present invention, all should contain within the scope of the invention.

Claims

1. wide-band gap material CMOS structure on the insulator comprises: be disposed in PMOS transistor and nmos pass transistor on the bottom insulator; The said nmos pass transistor common grid of said PMOS transistor AND gate zone; Said area of grid comprises the P type semiconductor material, is furnished with the drain region of the source region of the transistorized source region of said PMOS, said nmos pass transistor, said PMOS transistor drain zone and said nmos pass transistor successively around said area of grid; And said PMOS transistor drain zone links together through the drain electrode of said PMOS transistor drain electrode and said nmos pass transistor respectively with the drain region of said nmos pass transistor; The transistorized source region of said PMOS connects power line through its source electrode, and the source region of said nmos pass transistor is through its source electrode ground connection; It is characterized in that after the ion doping injection was carried out in the source region of said nmos pass transistor and drain region, the forbidden band of silicon was wider than in the forbidden band of the source region of formation nmos pass transistor and the semi-conducting material of drain region.

2. wide-band gap material CMOS structure on the insulator according to claim 1; It is characterized in that; The ion that injects is a carbon ion, and the source region of said formation nmos pass transistor and the semi-conducting material of drain region are wide-band gap material, and this wide-band gap material is SiC.

3. wide-band gap material CMOS structure on the insulator according to claim 1; It is characterized in that; Said PMOS transistor drain zone and source region lay respectively at the outside at a pair of diagonal angle of area of grid, and the drain region of said nmos pass transistor and source region lay respectively at another outside to the diagonal angle of area of grid.

4. wide-band gap material CMOS structure on the insulator according to claim 1; It is characterized in that; Said PMOS transistor drain zone and source region lay respectively at the outside of a pair of opposite side of area of grid, and the drain region of said nmos pass transistor and source region lay respectively at another outside to opposite side of area of grid.

5. according to wide-band gap material CMOS structure on claim 1 or the 3 or 4 described insulators; It is characterized in that, between each said source region and the said drain region, between each said source region and the neighboring area and all be furnished with insulating spacer between each said drain region and the neighboring area.

6. the preparation method like wide-band gap material CMOS structure on any described insulator in the above-mentioned claim 1 to 5 is characterized in that, comprises the following steps:

7. the preparation method of wide-band gap material CMOS structure is characterized in that on the insulator according to claim 6, and said silicon substrate is the P-type.