CN102738000A - Ultra-shallow junction formation method - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 27
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims description 94
- 238000002347 injection Methods 0.000 claims description 32
- 239000007924 injection Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052732 germanium Inorganic materials 0.000 claims description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 6
- 229910015900 BF3 Inorganic materials 0.000 claims description 5
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 229910001449 indium ion Inorganic materials 0.000 claims description 3
- -1 carbon ion Chemical class 0.000 claims 5
- 125000001475 halogen functional group Chemical group 0.000 claims 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 17
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000001953 recrystallisation Methods 0.000 abstract 1
- 230000002950 deficient Effects 0.000 description 13
- 125000005843 halogen group Chemical group 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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Abstract
The invention provides an ultra-shallow junction formation method. Through wide angle inclination LDD ion implantation of In ion with a relative large atomic mass, vertical LDD ion implantation of Ge ion is replaced so that an EOR defect is effectively reduced, and noncrystalline layer recrystallization, a TED effect and a junction leakage phenomenon which are formed through the implantation are improved. Simultaneously, an inclination mode LDD ion implantation is used so as to form LDD source/drain extension which is close to a grid bottom. Therefore, the ultra-shallow junction possessing a longer effective channel length can be obtained; a SCE effect is reduced; an electrical property of a MOS device is increased; a shallower source/drain junction depth can be made in an ultra-shallow junction technology.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of ultra shallow junction formation method.
Background technology
Progress along with semi-conductor industry; The characteristic size and the degree of depth of semiconductor device are constantly dwindled; Particularly entering into 65 nanometers reaches with lower node; Requirement source/drain region and source/drain electrode extension area (Source/DrainExtension) correspondingly shoals, and the doped junction that junction depth is lower than 100nm is commonly called ultra shallow junction (USJ), and ultra shallow junction can better improve the short-channel effect of device; But along with the further raising of device size and performance, the junction leakage phenomenon is the problem that ultra shallow junction technology more and more need solve.
In the prior art, be mask with grid structure 101 usually, with germanium 102, boron (or BF
2) ion 103 vertically is injected into successively and forms lightly-doped source/drain region (LDD) and lightly-doped source/drain electrode extension area in the Semiconductor substrate 100, reaches the purpose (like 1 among Fig. 1) of the ultra shallow junction of MOS device.This LDD ion implantation technique is utilized germanium, boron (or BF
2) the non-electroactive Semiconductor substrate that makes of ion is decrystallized, to eliminate short-channel effect (SCE), is commonly referred to as pre-amorphous injection (PAI) technology.But pre-amorphous injection meeting substrate produce with below the adjacent noncrystalline superficial layer of crystalline semiconductor materials, and outside the amorphous/crystalline interface, produce a large amount of serious defectives and (generally become the end region defective, EOR).Between the active period of subsequently annealing in process and semiconductor device, on the one hand, this EOR defective can make germanium, boron (or the BF of previous injection
2) diffusion of ion strengthens, and increases short-channel effect, is unfavorable for the formation of ultra shallow junction; On the other hand, the crystallization again of the noncrystalline layer of formation, the EOR defective can be dissolved the semiconductor interstitial atom to device architecture surface effective mobility, is prone to cause instantaneous enhancing diffusion (TED), causes short channel device performance degradation and junction leakage bigger.
Summary of the invention
The object of the present invention is to provide a kind of ultra shallow junction formation method, can effectively reduce end region defective and junction leakage phenomenon, and effectively control instantaneous enhancing diffusion and short-channel effect.
For addressing the above problem, the present invention proposes a kind of ultra shallow junction formation method, and this method comprises the steps:
Semiconductor substrate is provided, forms grid structure on the said Semiconductor substrate;
With the grid structure is mask, in said Semiconductor substrate, carries out first kind ion lightly-doped source/drain region with first angle and tilts to inject, and said first kind ion comprises the relative atomic mass ion bigger than germanium;
With the grid structure is mask, in said Semiconductor substrate, carries out second type of ion lightly-doped source/drain region with second angle and tilts to inject, and said second angle is littler than first angle;
The execution short annealing is handled, and forms ultra shallow junction.
Further, said grid structure comprises gate medium and is positioned at the grid on the gate medium.
Further, the ion that said relative atomic mass is bigger than germanium is indium (In) ion, and said first angle is 22 °～37 °.
Further, the injection energy of said indium (In) ion is 6KeV～20KeV, and dosage is 1E14～2E15/cm
2
Further, said first kind ion also comprises carbon (C) ion or fluorine (F) ion.
Further, the injection energy of said C ion or F ion is 3KeV～20KeV, and dosage is 1E14～2E15/cm
2, angle is 22 °～37 °.
Further, said second type of ion is boron fluoride (BF
2) ion or boron (B) ion, said second angle is 2 °～15 °.
Further, said BF
2The injection energy of ion or B ion is 0.5KeV～4KeV, and dosage is 2E14～2E15/cm
2
Further, tilt in said first kind ion lightly-doped source/drain region injection and said second type of ion lightly-doped source/drain region tilt between the injection, also comprise the hot activation operation is carried out in the zone after said first kind ion lightly-doped source/drain region injection.
Further, said hot activation is operating as hot furnaceman skill, rta technique, a kind of in diffusion furnace thermocouple technology or the laser pulse annealing process.
Further, said second type of ion lightly-doped source/drain region also comprises with the grid structure being mask before or after tilting to inject, and in said Semiconductor substrate, carries out the step that halo injects.
Further, the ion of said halo injection is arsenic (As) ion or phosphorus (P) ion.
Further, the angle of said halo injection is 25 °～35 °.
Further, said first angle and said second angle are benchmark with the vertical plane perpendicular to said semiconductor substrate surface all.
Compared with prior art; The present invention injects through the wide-angle tilt LDD ion of the bigger In ion of relative atomic mass, and the vertical LDD ion that replaces the Ge ion injects, and has effectively reduced the EOR defective; Improved and injected the noncrystalline layer crystallization again that forms, TED effect and junction leakage phenomenon; Simultaneously, adopt inclination mode LDD ion to inject, form,, reduce the SCE effect, improved the MOS electric properties of devices with this ultra shallow junction that obtains having longer length of effective channel more near the LDD source/drain extension region of gate bottom.
Description of drawings
Fig. 1 is a kind of ultra shallow junction structures sketch map of prior art;
Fig. 2 is the process chart of the embodiment of the invention;
The cross-sectional view of Fig. 3 A to 3E embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the ultra shallow junction formation method that the present invention proposes is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 2, the present invention provides a kind of ultra shallow junction formation method, is accomplished by step shown in the S1 to S4, below in conjunction with the cross-sectional view shown in process chart shown in Figure 2 and Fig. 3 A～3E above-mentioned ultra shallow junction formation method is explained in detail.
S1 provides Semiconductor substrate, forms grid structure on the said Semiconductor substrate.
Please refer to Fig. 3 A, Semiconductor substrate 300 is provided, on Semiconductor substrate 300, form grid structure 301; Grid structure generally comprises gate dielectric layer and grid (not shown), and said grid is formed at the gate dielectric layer top, and gate dielectric layer can be silica or silicon oxynitride; Below the 65nm technology node, preferred high-k (high K) material is like aluminium oxide; Zirconia, hafnium oxide etc.Grid is generally polysilicon.
S2 is a mask with the grid structure, in said Semiconductor substrate, carries out first kind ion lightly-doped source/drain region with first angle and tilts to inject, and said first kind ion comprises the relative atomic mass ion bigger than germanium.
Please refer to Fig. 3 B; With gate junction structure 301 is mask; Adopting first kind ion, is benchmark with the vertical plane perpendicular to Semiconductor substrate 300 surfaces, and the first angle [alpha] inclination injection mode is carried out lightly-doped source drain region (LDD) ion and injected the unactivated first lightly-doped source drain region 302 of formation; Shorten injection length, improve injection efficiency.Said first kind ion comprises the relative atomic mass ion bigger than germanium.Wide-angle tilt LDD ion through the bigger heavy ion of relative atomic mass injects; The decrystallized ion of vertical LDD that replaces the Ge ion of prior art injects; On the one hand, the diffusion coefficient of the heavy ion that relative atomic mass is bigger is lower, has effectively reduced the EOR defective; Improved and injected noncrystalline layer crystallization again, carrier mobility and the junction leakage phenomenon that forms, helped forming more shallow ultra shallow junction; On the other hand, wide-angle tilt injects and can stop the depletion region expansion relevant with darker source/drain region, has reduced the dependence of threshold voltage to channel length, has reduced SCE.
Select ion that LDD injects and the suitable angle of choosing injection, energy and dosage range, the further junction capacitance and the junction leakage of optimised devices generation, EOR defective; Therefore; Comprehensive first kind ion LDD injects SCE, junction capacitance and junction leakage, EOR defective, and preferable, the ion that said relative atomic mass is bigger than germanium is indium (In) ion; The injection energy is 6KeV～20KeV, and dosage is 1E14～2E15/cm
2, first angle [alpha] is 22 °～37 °.
Please refer to Fig. 3 C; Normally; After the said ion LDD big to atom mass rate germanium tilts to inject; Also can carry out with grid structure 301 is mask, in said Semiconductor substrate 300, adopts carbon (C) ion or fluorine (F) ion to carry out LDD wide-angle γ and tilts to inject, and forms the unactivated second lightly-doped source drain region 303; Instantaneous enhancing diffusion (TED) effect and hot carrier to suppress to cause when indium (In) ion injects as heavy ion are injected (HCI) effect, improve indium ion and inject the lattice damage defective that causes.Preferable, the injection energy of said C ion or F ion is 3KeV～20KeV, dosage is 1E14～2E15/cm
2, angle γ can equate with α, also can not wait, in the present embodiment, γ equates with α, is 22 °～37 °.
Normally; After said first kind ion LDD wide-angle tilt ion injects, also comprise the hot activation operation is carried out in the zone after said first kind ion lightly-doped source/drain region injection, promptly to the unactivated first lightly-doped source drain region 302 and the unactivated second lightly-doped source drain region 303; Adopt hot furnaceman's skill; Rta technique, a kind of in diffusion furnace thermocouple technology or the laser pulse annealing process carries out hot activation; Make indium (In) ion, C ion or the F ions diffusion of injection even, eliminate and inject defective.
S3 is a mask with the grid structure, in said Semiconductor substrate, carries out second type of ion lightly-doped source/drain region with second angle and tilts to inject, and said second angle is littler than first angle.
Please refer to Fig. 3 D; With gate junction structure 301 is mask; Adopting second type of ion, is benchmark with the vertical plane perpendicular to Semiconductor substrate 300 surfaces, and the second angle beta inclination injection mode is carried out lightly-doped source drain region (LDD) ion and injected unactivated the 3rd lightly-doped source drain region 304 of formation; Shorten injection length, improve injection efficiency.Second type of ion LDD small angle inclination injected, and can penetrate the darker part of substrate, but can not cause diffusion or punch through, connects face to form high performance P type, improves the leakage current that the P type connects face.Preferably, said second type of ion is boron fluoride (BF
2) ion or boron (B) ion, the injection energy is 0.5KeV～4KeV, dosage is 2E14～2E15/cm
2, second angle beta is 2 °～15 °.
Please refer to Fig. 3 E; Normally, before or after second type of ion LDD small angle inclination ion injected, also can carry out with grid structure 301 was mask; Vertical plane with perpendicular to Semiconductor substrate 300 surfaces is a benchmark; Wide-angle θ inclination injection mode is carried out the step that halo injects in said Semiconductor substrate 300, form unactivated halo 305, to suppress boron fluoride (BF
2) the TED effect and the punch-through effect of ion or boron (B) ion, further improve device performance.The ion that said halo injects is arsenic (As) ion or phosphorus (P) ion, and the angle θ that said halo injects is 25 °～35 °.This injection technique is those skilled in that art's known technology, no longer details.
In other embodiments of the invention, step S2 and step S3 can exchange.
S4 carries out short annealing and handles, and forms ultra shallow junction.
Please refer to Fig. 3 D and Fig. 3 E, short annealing under inert gas environments such as nitrogen or argon gas activates and injects ion and eliminate the injection defective, forms ultra shallow junction 2.Compare with the ultra shallow junction 1 of prior art manufacturing among Fig. 1; The ultra shallow junction 2 that this heavy ion wide-angle tilt mode forms is more near the gate bottom center; Obtain longer effective raceway groove, thereby when keeping electric properties of devices, effectively suppressed the HCI effect; Significantly improve the SCE effect, reduce punch-through effect that device size reduces to be brought and by its junction leakage that causes.
In sum; Method of the present invention; Can be used for forming the ultra shallow junction MOS device of 65nm and following technology node, through the wide-angle tilt LDD ion injection of the bigger In ion of relative atomic mass, the vertical LDD ion that replaces the Ge ion injects; Effectively reduced the EOR defective, improved and injected noncrystalline layer crystallization again, TED effect and the junction leakage phenomenon that forms; Simultaneously; Adopt inclination mode LDD ion to inject; Form more near the LDD source/drain extension region of gate bottom,, reduce the SCE effect with this ultra shallow junction that obtains having longer length of effective channel; Improved the MOS electric properties of devices, made that the more shallow source/drain region junction depth of manufacturing becomes possibility in ultra shallow junction technology.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (14)
1. a ultra shallow junction formation method is characterized in that, comprising:
Semiconductor substrate is provided, forms grid structure on the said Semiconductor substrate;
With the grid structure is mask, in said Semiconductor substrate, carries out first kind ion lightly-doped source/drain region with first angle and tilts to inject, and said first kind ion comprises the relative atomic mass ion bigger than germanium;
With the grid structure is mask, in said Semiconductor substrate, carries out second type of ion lightly-doped source/drain region with second angle and tilts to inject, and said second angle is littler than first angle;
The execution short annealing is handled, and forms ultra shallow junction.
2. ultra shallow junction formation method as claimed in claim 1 is characterized in that, said grid structure comprises gate medium and is positioned at the grid on the gate medium.
3. ultra shallow junction formation method as claimed in claim 1 is characterized in that, the ion that said relative atomic mass is bigger than germanium is an indium ion, and said first angle is 22 °～37 °.
4. ultra shallow junction formation method as claimed in claim 3 is characterized in that the injection energy of said indium ion is 6KeV～20KeV, and dosage is 1E14～2E15/cm
2
5. ultra shallow junction formation method as claimed in claim 1 is characterized in that said first kind ion also comprises carbon ion or fluorine ion.
6. ultra shallow junction formation method as claimed in claim 5 is characterized in that the injection energy of said carbon ion or fluorine ion is 3KeV～20KeV, and dosage is 1E14～2E15/cm
2, angle is 22 °～37 °.
7. ultra shallow junction formation method as claimed in claim 1 is characterized in that, said second type of ion is boron fluoride ion or boron ion, and said second angle is 2 °～15 °.
8. ultra shallow junction formation method as claimed in claim 7 is characterized in that the injection energy of said boron fluoride ion or boron ion is 0.5KeV～4KeV, and dosage is 2E14～2E15/cm
2
9. ultra shallow junction formation method as claimed in claim 1; It is characterized in that; Tilt between injection and the said second type of ion lightly-doped source/drain region inclination injection in said first kind ion lightly-doped source/drain region, comprise that also hot activation is carried out in the zone after said first kind ion lightly-doped source/drain region inclination is injected to be operated.
10. ultra shallow junction formation method as claimed in claim 9 is characterized in that, said hot activation is operating as hot furnaceman skill, rta technique, a kind of in diffusion furnace thermocouple technology or the laser pulse annealing process.
11. ultra shallow junction formation method as claimed in claim 1 is characterized in that, said second type of ion lightly-doped source/drain region also comprises with the grid structure being mask before or after tilting to inject, and in said Semiconductor substrate, carries out the step that halo injects.
12. ultra shallow junction formation method as claimed in claim 11 is characterized in that, the ion that said halo injects is arsenic ion or phosphonium ion.
13. ultra shallow junction formation method as claimed in claim 12 is characterized in that, the angle that said halo injects is 25 °～35 °.
14. each the described ultra shallow junction formation method as in claim 1 or 4 or 6 or 8 is characterized in that said first angle and said second angle are benchmark with the vertical plane perpendicular to said semiconductor substrate surface all.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113555432A (en) * | 2020-04-23 | 2021-10-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2023029196A1 (en) * | 2021-08-31 | 2023-03-09 | 长鑫存储技术有限公司 | Method for forming field effect transistor, method for adjusting electrical performance parameters, and structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1218298A (en) * | 1997-11-25 | 1999-06-02 | 三星电子株式会社 | MOS transistor and thereof manufacturing method |
| US20030178685A1 (en) * | 2002-03-19 | 2003-09-25 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
| CN1469488A (en) * | 2002-06-24 | 2004-01-21 | ��ʿͨ��ʽ���� | Semiconductor device and producing method thereof |
-
2011
- 2011-04-12 CN CN2011100905490A patent/CN102738000A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1218298A (en) * | 1997-11-25 | 1999-06-02 | 三星电子株式会社 | MOS transistor and thereof manufacturing method |
| US20030178685A1 (en) * | 2002-03-19 | 2003-09-25 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
| CN1469488A (en) * | 2002-06-24 | 2004-01-21 | ��ʿͨ��ʽ���� | Semiconductor device and producing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113555432A (en) * | 2020-04-23 | 2021-10-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2023029196A1 (en) * | 2021-08-31 | 2023-03-09 | 长鑫存储技术有限公司 | Method for forming field effect transistor, method for adjusting electrical performance parameters, and structure |
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Application publication date: 20121017 |