JPS5570035A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5570035A
JPS5570035A JP14370978A JP14370978A JPS5570035A JP S5570035 A JPS5570035 A JP S5570035A JP 14370978 A JP14370978 A JP 14370978A JP 14370978 A JP14370978 A JP 14370978A JP S5570035 A JPS5570035 A JP S5570035A
Authority
JP
Japan
Prior art keywords
region
bonding
alloy
pellet
adhered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14370978A
Other languages
Japanese (ja)
Inventor
Kosei Kajiwara
Tatsunori Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14370978A priority Critical patent/JPS5570035A/en
Publication of JPS5570035A publication Critical patent/JPS5570035A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PURPOSE: To obtain a bonding stable for its step and preferable in its reproducibility in a semiconductor device by implanting germanium ion onto the back surface of a pellet, depositing a film having mainly gold thereon and then bonding via Au-Si eutectic.
CONSTITUTION: Ge+ is implanted at 50keVW100keV and higher than 5×10-15cm2 on the surface 6 of a silicon substrate 5 and on the surface 11 to be adhered to the opposite surface thereof to thereby form an implantation region 12. An Au deposited film 13 is formed in several micron further thereon by means of a vacuum depositing process. It is then placed on a metallic header 15 and heated at 450°C, and pressurized then. When the Au-Si alloy starts melting in the boundary between the Au deposited film 13 and the Ge ion implanted region 12, the Ge implanted region is molten into the Au-Si alloy molten region 16. When it is then cooled, a pellet 14 is adhered to the header 15. Thus, a bonding can be stably obtained without deposition of different element alloy of vapor pressure such as Au and Ge.
COPYRIGHT: (C)1980,JPO&Japio
JP14370978A 1978-11-20 1978-11-20 Manufacture of semiconductor device Pending JPS5570035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14370978A JPS5570035A (en) 1978-11-20 1978-11-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14370978A JPS5570035A (en) 1978-11-20 1978-11-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5570035A true JPS5570035A (en) 1980-05-27

Family

ID=15345140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14370978A Pending JPS5570035A (en) 1978-11-20 1978-11-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5570035A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5037778A (en) * 1989-05-12 1991-08-06 Intel Corporation Die attach using gold ribbon with gold/silicon eutectic alloy cladding
CN103500704A (en) * 2013-09-29 2014-01-08 武汉新芯集成电路制造有限公司 Ion implantation method for back face of wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5037778A (en) * 1989-05-12 1991-08-06 Intel Corporation Die attach using gold ribbon with gold/silicon eutectic alloy cladding
CN103500704A (en) * 2013-09-29 2014-01-08 武汉新芯集成电路制造有限公司 Ion implantation method for back face of wafer

Similar Documents

Publication Publication Date Title
JPS57113289A (en) Semiconductor device and its manufacture
WO1989002653A1 (en) Bonding of aligned conductive bumps on adjacent surfaces
EP0817254A3 (en) Semiconductor device and methods for producing and mounting the semiconductor device
US3785892A (en) Method of forming metallization backing for silicon wafer
JPS5570035A (en) Manufacture of semiconductor device
GB1190993A (en) Improved methods of Depositing Semiconductor Material and Forming Semiconductor Junctions
GB1215088A (en) Process for affixing thin film electrical contacts to a semiconductor body comprising silicon carbide
US2870050A (en) Semiconductor devices and methods of making same
JPS5570036A (en) Fabricating method of semiconductor device
JPS5512735A (en) Semiconductor device
JPS54153573A (en) Manufacture for compound semiconductor device
JPS52124860A (en) Electrode formation method for semiconductor devices
JPS6471136A (en) Semiconductor device
JPS5728336A (en) Forming method for electrode of semiconductor device
JPS556839A (en) Semiconductor device
JPS57154829A (en) Forming method for electrode metal of semiconductor device
JPS5570037A (en) Fabricating method of semiconductor device
JPS54158864A (en) Brazing method for semiconductor pellet
JPS54106166A (en) Manufacture of semiconductor device
JPS54113250A (en) Production of semiconductor device
JPS54160166A (en) Electrode forming method for semiconductor device
JPS54102969A (en) Semiconductor device
JPS54101666A (en) Semiconductor device
JPS54101263A (en) Semiconductor device
JPS5494874A (en) Semiconductor device