CN105609419A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN105609419A CN105609419A CN201610104847.3A CN201610104847A CN105609419A CN 105609419 A CN105609419 A CN 105609419A CN 201610104847 A CN201610104847 A CN 201610104847A CN 105609419 A CN105609419 A CN 105609419A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 48
- 230000007547 defect Effects 0.000 claims abstract description 39
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000002513 implantation Methods 0.000 claims description 73
- 238000010438 heat treatment Methods 0.000 claims description 28
- 238000012545 processing Methods 0.000 claims description 13
- 238000012805 post-processing Methods 0.000 claims description 9
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 6
- 239000005864 Sulphur Substances 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 5
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- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000009467 reduction Effects 0.000 claims description 5
- 229910052711 selenium Inorganic materials 0.000 claims description 5
- 239000011669 selenium Substances 0.000 claims description 5
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 2
- 239000012535 impurity Substances 0.000 abstract description 25
- 230000004913 activation Effects 0.000 abstract description 11
- 239000002019 doping agent Substances 0.000 abstract description 8
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- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
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- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps as follows: a well region is formed on the first surface of a semiconductor substrate; the semiconductor substrate and the well region are a first doping type and a second doping type, which are opposite to each other, respectively; a gate dielectric layer is formed on the well region; a gate conductor layer is formed on the gate dielectric layer; a base region with the second doping type is formed in the well region; an emitter region with the first doping type is formed in the base region; an emitter electrode is formed on the emitter region; pretreatment is carried out to form a pretreatment region in the region close to the second surface of the semiconductor substrate; a collector region with the first doping type is formed on the second surface of the semiconductor substrate; a collector electrode is formed on the collector region; and first thermal treatment is carried out, activates a dopant in the first doping region and forms a defect layer near the collector region. The method lowers the thermal treatment temperature of post production of the semiconductor device and obtains high-impurity activation by introducing the defect layer.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, more specifically, relate to semiconductor devices and system thereofMaking method.
Background technology
Integrated circuit is included in that single Semiconductor substrate forms and by together multiple of wire interconnectsSemiconductor devices. In integrated circuit, semiconductor devices can be used as power switch or signal processingDevice. Power semiconductor is also called power electronic devices, comprise power diode, IGCT,VDMOS (vertical DMOS) field-effect transistor, LDMOS (horizontal strokeTo diffused metal oxide emiconductor) field-effect transistor and IGBT (insulated gate bipolar crystalline substanceBody pipe) etc. IGBT is by BJT (double pole triode) and FET (field-effect transistor) groupThe compound full-control type voltage driven type power semiconductor becoming. IGBT has BJT and FET concurrentlyBoth advantages, i.e. the feature of high input impedance and low conduction voltage drop, therefore has good switchCharacteristic, is widely used in the field with the feature such as high pressure, heavy current, for example, and alternating currentThe fields such as machine, frequency converter, Switching Power Supply, lighting circuit, Traction Drive.
Manufacture in the technique of power semiconductor need to be in Semiconductor substrate implanted dopant, withAnd anneal, with activator impurity. For example,, making when IGBT, in the of Semiconductor substrateAfter one surface forms launch site, also need to form current collection at the relative second surface of Semiconductor substrateDistrict. For this reason, first Semiconductor substrate is carried out to attenuate, to reach predetermined thickness, then from semiconductorThe second surface implanted dopant of substrate, then anneal with activator impurity, make in Semiconductor substrateDoped region as collecting zone. But, due in semiconductor devices, formed multiple metal levels andDoped region, therefore, can not be too high for the temperature of the annealing of collecting zone, in order to avoid the gold having formedBelong to layer and damage, or there is undesirable diffusion in doped region. On the other hand, if this annealing temperatureToo low, the activity ratio of impurity is low, causes that IGBT saturation voltage drop is high and switching loss is large.
Therefore, expect further to improve the manufacture method of semiconductor devices, follow-up impurity is swashedThe annealing of living can also can realize high activity ratio under cryogenic conditions.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of semiconductor devices and manufacture method side thereofMethod, wherein introduces defect layer and manufactures the heat treatment temperature in later stage and obtain high to reduce semiconductor devicesImpurity activation rate.
According to an aspect of the present invention, provide a kind of manufacture method of semiconductor devices, comprising:The first surface of Semiconductor substrate forms well region, and described Semiconductor substrate and described well region are respectively theOne doping type; On described well region, form gate dielectric layer; On described gate dielectric layer, forming grid leadsBody layer; In described well region, form the base of the second doping type, described the second doping type and instituteState the first doping type contrary; In described base, form the launch site of the first doping type; InstituteState and on launch site, form emission electrode; Carry out pretreatment, near the second surface of Semiconductor substrateFormation pretreating zone, region; Form the collection of the first doping type at the second surface of Semiconductor substrateElectricity district; On described collecting zone, form collecting electrodes; And carry out the first heat treatment, described firstHeat treatment activates the adulterant of the first doped region and form defect layer near described collecting zone.
Preferably, forming the step of collecting zone and forming between the step of collecting electrodes, also comprising:Carry out post processing, near region generating defect Semiconductor substrate is positioned at the first doped region.
Preferably, described pretreatment and described post processing produce described lacking by Implantation or irradiationFall into.
Preferably, the adulterant that described Implantation adopts is for being selected from hydrogen, helium, sulphur, oxygen and seleniumAt least one.
Preferably, the Implantation Energy of the Implantation adopting in pretreatment is 25KeV～500KeV,Implantation dosage is 1E11/cm2～1E15/cm2.
The Implantation Energy of the Implantation preferably, adopting in post processing is200KeV～600KeV, implantation dosage is 1E11/cm2～1E15/cm2.
Preferably, in post processing, carry out repeatedly Implantation, the injection of described repeatedly ImplantationEnergy successively decreases, and implantation dosage is identical, thereby forms multiple roughly peak values such as grade but the defect of different depthDistrict.
Preferably, described the first heat treated temperature is between 350 DEG C～420 DEG C, and the time is 10 pointsBetween clock to 60 minute.
Preferably, forming the step of collecting zone and forming between the step of collecting electrodes, also compriseThe second heat treatment, the common activation of described the first heat treatment and described the second heat treatment the first doped regionNear adulterant and form defect layer the first doped region.
Preferably, described the first heat treated temperature is between 400 DEG C～450 DEG C, and the time is 0.5Hour between 2 hours.
Preferably, the first doping type is the one being selected from P type and N-type, the second doping typeFor being selected from the another kind in P type and N-type.
Preferably, before carrying out pretreated step, also comprise: carry out reduction processing, to subtractThe thickness of little described Semiconductor substrate.
According to a further aspect in the invention, provide a kind of semiconductor devices, comprising: be positioned at semiconductorNear well region in substrate first surface, described Semiconductor substrate and described well region are respectively first and mixMiscellany type; Be positioned at the gate dielectric layer on described well region; Be positioned at the grid conductor layer on described gate dielectric layer;Be arranged in the base of the second doping type of described well region, described the second doping type and described firstDoping type is contrary; Be arranged in the launch site of the first doping type of described base; Be positioned at described sending outPenetrate the emission electrode in district; Be arranged near the collecting zone of described Semiconductor substrate second surface; LackFall into layer, described defect layer is arranged near the region described collecting zone; And be positioned at described collecting zoneOn collecting electrodes.
Preferably, described defect layer comprises that at least one that be selected from hydrogen, helium, sulphur, oxygen and selenium mixAssorted agent.
Preferably, described defect layer comprises multiple roughly peak values such as grade but the defect area of different depth.
Preferably, the first doping type is the one being selected from P type and N-type, the second doping typeFor being selected from the another kind in P type and N-type.
Compared with prior art, the present invention adopted before the doping of semiconductor devices collecting zone Impurity injectionWith the pretreatment of Implantation, can significantly promote semiconductor devices collecting zone impurity at low temperatureHeat treated activity ratio, and then improve the conduction voltage drop of semiconductor devices, reduce its conduction loss;And, by this ion irradiation processing, can suppress semiconductor devices collecting zone impurity heat treatedDiffusion junction depth in journey, special, the semiconductor devices that adopts p type impurity to adulterate for collecting zone,The turn-off power loss of this device can effectively fall;
Further, the following table of energy more than employing 200KeV to the preset thickness region retainingFace carries out H+ Implantation/radiation treatment at least one times, twice and twice above injection/irradiationEnergy difference, forms the defect layer with the peak Distribution such as continuous, and described defect layer is through oneAfter the heat treatment of fixed temperature condition, can form in vivo extra complex centre, this complex centre canTo play N-type impurity compensation effect, reduce the minority carrier life time of semiconductor devices, thereby reach into oneStep reduces the object of the switching loss of semiconductor devices; Moreover the present invention is default thick to what retainAfter the lower surface in degree region carries out H+ Implantation/radiation treatment at least one times, directly halfThe lower surface depositing metal layers in the preset thickness region that conductive substrate retains, and then semiconductor is served as a contrastPreset thickness region and metal level that the end retains are heat-treated technique, without at H+ ImplantationAfter/irradiation, carry out extra Technology for Heating Processing, reduced processing step, saved processing cost.
The temperature of Technology for Heating Processing arranges requirement can not make the established upper surface of IGBT deviceMetal level is damaged, and what therefore the heat treated temperature of this annealing arranged is lower, at this temperatureThe activity ratio of implanted dopant is not ideal enough, causes the saturation voltage drop of IGBT device higher. Especially, for modern IGBT device products, for improving the operating frequency of IGBT device, conventionally canAdopt the setting of lightly doped collecting zone impurity, now the activation to collecting zone impurity Low Temperature Heat TreatmentRate requires further to promote. The present invention has not only solved semiconductor devices collecting zone implanted dopant lowThe lower problem of activity ratio in warm processing procedure provides raising semiconductor devices switch lock simultaneouslyThe process program of rate.
Brief description of the drawings
By the description to the embodiment of the present invention referring to accompanying drawing, of the present invention above-mentioned and otherObject, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 to 11 illustrates according to the method, semi-conductor device manufacturing method different phase of the embodiment of the present inventionSectional view;
The doping content that Figure 12 illustrates semiconductor devices according to an embodiment of the invention respectively and lackFall into and distribute;
Figure 13 illustrates the heat place of the method, semi-conductor device manufacturing method of the embodiment of the present invention and prior artThe curve of relation between reason temperature and the saturation voltage drop of semiconductor devices.
Detailed description of the invention
Hereinafter with reference to accompanying drawing, the present invention is described in more detail. In each accompanying drawing, identical elementAdopt similar Reference numeral to represent. For the sake of clarity, the various piece in accompanying drawing is not pressedScale. In addition, may not shown some known part. For brevity, Ke YiThe semiconductor structure obtaining after several steps is described in one width figure.
Should be appreciated that in the time of the structure of outlines device, when one deck, a region are called and are positioned at separatelyWhen one deck, another region " above " or " top ", can refer to be located immediately at another layer, anotherOne above region, or itself and another layer, also comprise between another region other layer orRegion. And, if by device upset, this one deck, region will be positioned at another layer, anotherIndividual region " below " or " below ".
If to be located immediately at another layer, another situation above region in order describing, will to adopt hereinWith the form of presentation of " A is directly on B " or " A on B and with it in abutting connection with ". At thisIn application, " A is located immediately in B " represents that A is arranged in B, and A and B adjacency, andNon-A is arranged in the doped region that B forms.
In this application, term " semiconductor structure " refers in each step of manufacturing semiconductor devicesThe general designation of the whole semiconductor structure of middle formation, comprises all layers or the region that have formed.
Many specific details of the present invention have been described hereinafter, the structure of for example device, material,Size, treatment process and technology, to more clearly understand the present invention. But as the skill of this areaIt is such that art personnel can understand, and can realize the present invention not according to these specific details.
Unless particularly pointed out hereinafter, the various piece of semiconductor devices can be by the skill of this areaThe known material of art personnel forms. Semi-conducting material for example comprises III-V family semiconductor, as GaAs,InP, GaN, SiC, and IV family semiconductor, as Si, Ge.
Fig. 1 to 11 illustrates according to the method, semi-conductor device manufacturing method different phase of the embodiment of the present inventionSectional view. In this embodiment, do with non-through insulated-gate bipolar transistor (NPT-IGBT)For the example of semiconductor devices.
Igbt (IGBT) is mos field effect transistor (MOSFET) with the compound power device of bipolar junction transistor (BJT). Non-through insulated-gate is twoGated transistors (NPT-IGBT) adopts thin substrate technology, thus with ion implanted impurity in substrateForm launch site, to replace high complexity and expensive epitaxial layer, be produced into thereby can reduceThis. The embodiment of the present invention relates to the further improvement of the manufacturing process of NPT-IGBT.
In this embodiment, Semiconductor substrate 101 be for example<100>crystal orientation and be N-type doping classThe silicon wafer of type.
For example, adopt zone-melting process Crystal Growth Technique can form monocrystalline substrate, and can mixMix into required doping type. The doping content of monocrystalline substrate can be according to the resistivity choosing of expectingSelect, for example, Semiconductor substrate 101 doping contents in this embodiment can be 5E14/cm3Extremely5E15/cm3Between, resistivity is preferably between 20～80ohm*cm.
Then,, by the first Implantation, in Semiconductor substrate 101, form the first doping typeWell region 112, as shown in Figure 1, wherein arrow represents the direction of Implantation. The first doping classType is contrary with the second doping type, is respectively the one being selected from N-type and P type. At this embodimentIn, well region 112 is N-type doped region.
Before Implantation, in Semiconductor substrate 101, form photoresist layer, by photoetchingPhotoresist layer is formed to the mask that comprises opening, then carry out Implantation via mask. ShouldMask is as the block masks of Implantation, the opening portion pattern of mask and the well region that will form112 pattern is identical. After Implantation, remove photic by dissolving or ashing in solventResist layer.
Control the energy of Implantation and the dosage of adulterant, can controlled doping agent at well region 112In the degree of depth and doping concentration distribution. Preferably, well region 112 is from the surface of Semiconductor substrate 101Reach to downward-extension the position that the degree of depth exceedes 10 microns. For this reason, the energy of Implantation is about800keV-1500keV, thus inject and arrive the degree of depth of expecting by high-energy. For example,, for shapeBecome N-type well region 112, can adopt P elements or arsenic element as adulterant, implantation dosage is5E12/cm2～5E14/cm2。
Then, on the surface of semiconductor structure, form successively gate dielectric layer 114 and grid conductor layer115, as shown in Figure 2.
Gate dielectric layer is for example the dielectric layer forming by thermal oxide, or by known deposition workThe dielectric layer that skill technique forms. Grid conductor layer is for example the conductor forming by known depositing operationLayer. These known depositing operations comprise physical vapour deposition (PVD) (PVD), chemical vapour deposition (CVD)(CVD), ald (ALD) etc. In this embodiment, gate dielectric layer is for example logicalCross the silicon oxide layer that thermal oxide forms, grid conductor layer is for example the DOPOS doped polycrystalline silicon forming by sputterLayer, wherein sputter is a kind of technique of physical vapour deposition (PVD). In this embodiment, gate dielectric layer 114Be for example the silicon oxide layer of thickness 80 nanometer to 150 nanometers, grid conductor layer 115 is for example thicknessThe doped polysilicon layer of the N-type of 500 nanometers to 2 micron. The doped resistor rate of grid conductor layer 115Be for example between 0.5ohm/sqrt to 50ohm/sqrt.
Then,, according to the design needs of the cellular cellular construction of semiconductor devices, can adopt additionalMask, grid conductor layer and gate dielectric layer are patterned to required pattern form, as shown in Figure 3.
Then,, by the second Implantation, in well region 112, form the base of the second doping type111, as shown in Figure 4, wherein arrow represents the direction of Implantation. In this embodiment, base111 is P type doped region.
During Implantation, can adopt photoresist layer to form mask PR1, to limit baseThe pattern in district 111. Adulterant enters in well region 112 via the opening of mask.
What control the energy of Implantation and adulterant be dosage, makes the bottom surface arrival of base 111In Semiconductor substrate 101, sidewall by well region 112 around. For this reason, the energy of Implantation is about60KeV～120KeV. For example, in order to form P type base, can adopt boron element as dopingAgent, implantation dosage is 5E13/cm2～2E15/cm2。
Preferably exist, after the second Implantation, anneal, to activate mixing in base 111Assorted agent. This annealing can be carried out under nitrogen environment, annealing temperature between 850 DEG C～1050 DEG C,Annealing time is between 0.5 hour to 2 hours.
Then,, by the 3rd Implantation, in base 111, form the transmitting of the first doping typeDistrict 113, as shown in Figure 5, wherein arrow represents the direction of Implantation. In this embodiment,Launch site 113 is N-type doped region.
During Implantation, as mentioned above, can adopt photoresist layer to form mask PR2,To limit the pattern of launch site 113. Adulterant enters in base 111 via the opening of mask.
What control the energy of Implantation and adulterant be dosage, the bottom surface that makes launch site 113 withSidewall by base 111 around. Preferably, the surface of launch site 113Cong base 111 extends to baseThe position of desired depth in district 111. For this reason, the energy of Implantation is about 60KeV～120KeV.For example, in order to form N-type launch site, can adopt P elements or arsenic element as adulterant, noteEntering dosage is 5E13/cm2～2E15/cm2。
Preferably exist, after the 3rd Implantation, anneal, to activate in launch site 113Adulterant. This annealing can be carried out under nitrogen environment, annealing temperature 850 DEG C～1050 DEG C itBetween, annealing time is between 0.5 hour to 2 hours.
As shown in Figure 5, grid conductor layer 115 and gate dielectric layer 114 are stacked on described base 111Peripheral part top, and extend laterally on the surface of launch site 113 and Semiconductor substrate 101.As mentioned above, a part of peripheral part of base 111 is used to form channel region, grid conductor layer 115Be positioned at channel region top, thereby can control the conducting state of channel region.
Then, form passivation layer 116 on the surface of semiconductor structure, adopt mask to carry out etching,In passivation layer 116, form the opening that exposes 113 surfaces, launch site, as shown in Figure 6.
In the time forming above-mentioned passivation layer 116, can adopt above-mentioned known deposition process partly leadingThe surface of body structure forms insulating barrier. In this embodiment, passivation layer 116 is for example by sputterThe silicon nitride layer forming, or the boron phosphorus silicate glass forming by chemical vapour deposition (CVD)(BPSG), thickness is between 600 nanometers to 1.5 micron.
Then, form emission electrode 118 on passivation layer 116, this emission electrode 118 is via bluntThe opening of changing in layer 116 arrives launch site 113, as shown in Figure 7.
On the surface of semiconductor structure, for example, by sputter, deposits conductive material, this conduction materialMaterial at least can filling opening. Adopt mask to carry out etching, conductive layer pattern is turned to emission electrode118。
Through each above-mentioned step, in the first surface side of Semiconductor substrate 101, form and partly leadThe Facad structure of body device. Will be appreciated that, above-mentioned Facad structure can also be included in semiconductor liningThe potential dividing ring structure (not shown) forming etc., and the formation side of above-mentioned Facad structure at the end 101Formula is also not limited to above-mentioned explanation, the content that this is well known to those skilled in the art, and the present invention is alsoDo not relate to the improvement of this part, thereby repeat no more.
Then, in the second surface side of Semiconductor substrate 102, carry out reduction processing, remove partBacking material, retains preset thickness region. In this step, the thickness of Semiconductor substrate 101 fromTH1 is decreased to TH2, as shown in Figure 8.
In the time of reduction processing, can carry out chemical-mechanical planarization (CMP), from Semiconductor substrate101 second surface is removed the semi-conducting material of predetermined thickness, this predetermined thickness ΔTH=TH1-TH2. Preferably, after chemical-mechanical planarization, can also be in Semiconductor substrate101 second surface carries out wet etching, and after this wet etching course can make attenuate, semiconductor serves as a contrastThe stress at the end is effectively discharged, and can effectively eliminate the mechanical damage layer of semiconductor substrate surface,Improve semiconductor substrate surface roughness.
Determine the thickness after Semiconductor substrate 101 attenuates according to the performance parameter of IGBT. WithThe IGBT device of 1200V specification is example, and Semiconductor substrate thickness can be thinned to 110～240 μ mBetween.
Then,, by the 4th Implantation, near the second surface of Semiconductor substrate 101, formPretreating zone 120, as shown in Figure 9, wherein arrow represents the direction of Implantation. In this enforcementIn example, the 4th Implantation is the pretreatment before forming collecting zone, near collecting zoneProduce defect layer.
What control the energy of Implantation and adulterant is dosage, and pretreating zone 120 is extended toThe position of the second surface top desired depth of Semiconductor substrate 101. For this reason, the energy of ImplantationAmount is about 25KeV～500KeV. The adulterant of this pretreating zone 120 can adopt ion elements bagDraw together hydrogen, helium, sulphur, oxygen or selenium, implantation dosage is about 1E11/cm2～1E15/cm2. Preferably,The 3rd Implantation adopts H+ ion elements as adulterant, and Implantation Energy is 400KeV, injectsDosage is 1E14/cm2。
Then,, by the 5th Implantation, near the second surface of Semiconductor substrate 101, formThe collecting zone 122 of the second doping type, as shown in figure 10, wherein arrow represents the side of ImplantationTo. In this embodiment, collecting zone 122 is P type doped region, with pretreating zone 120 adjacency.Meanwhile, the remainder of Semiconductor substrate 101 is N-type doped region, with base 111 and well region 112Adjacency.
What control the energy of Implantation and adulterant is dosage, makes collecting zone 122 from semiconductorThe second surface of substrate 101 extends to the position of inner desired depth. For this reason, the energy of ImplantationAmount is about 25KeV～100Ke. The adulterant of this collecting zone 122 can adopt ion elements boron to injectDosage is about 5E12/cm2～5E14/cm2。
Preferably exist, after the 5th Implantation, anneal, to activate in collecting zone 122Adulterant. This annealing can be carried out under nitrogen environment, annealing temperature between 400 DEG C～450 DEG C,Annealing time is between 0.5 hour to 2 hours. It should be noted that moving back of carrying out at activation adulterantIn ignition technique, annealing temperature is usually above 800 DEG C, and the method for the embodiment of the present invention swashs at collecting zoneThe annealing temperature adopting in annealing alive is starkly lower than conventional activation annealing temperature.
As shown in figure 10, pretreating zone 120 extends to the second surface top of Semiconductor substrate 101The position of desired depth. The pretreating zone 120 that a part for collecting zone 122 and previous steps formOverlapping, as will be described, pretreating zone 120 will be introduced and be lacked near collecting zone 122Fall into.
Then, by above-mentioned known deposition process, on collecting zone 122, form collecting electrodes 124,As shown in figure 11. In this embodiment, collecting electrodes is for example the metal laminated of Al/Ti/Ni/Ag.
Then, the preset thickness region to described reservation and heavy under vacuum or nitrogen protection atmosphereLong-pending metal level is heat-treated. In near the pretreating zone 120 of this heat treatment collecting zone 122,Be the front end (being the region of collecting zone 122 near base 111) of collecting zone 122, produce defectLayer 121, as shown in figure 11.
In heat treatment step, heat treatment temperature and deficiency of time are to make power semiconductorMetal level melting. In this embodiment, the heat place under described vacuum and nitrogen protection atmosphereReason temperature is between 350 DEG C～420 DEG C, and heat treatment time is between 10 minutes to 60 minutes.
It should be noted that activating in the annealing process that carries out of adulterant, annealing temperature usually above800 DEG C, the heat treatment temperature of the method for the embodiment of the present invention after forming collecting electrodes 124 is obviousLower than conventional activation annealing temperature.
In the above-described embodiment, near collecting zone 122, produce defect by pretreating zone 120Distribute. Pretreatment significantly the collecting zone impurity of hoisting power semiconductor devices under cryogenic conditionsActivity ratio, and then improve the conduction voltage drop of power semiconductor, reduce its conduction loss. ?In pretreated Implantation, found through experiments, wherein adopt the effect of hydrogen (H+) particularly aobviousWork. Taking 600VIGBT product as example, this product adopt respectively pretreatment that H+ injects withAnd different collecting zone impurity heat treatment temperatures is carried out impurity activation.
In a preferred embodiment, forming between collecting zone 122 and the step of collecting electrodes 124,Said method can also be carried out the 6th additional at least one times Implantation. In this embodiment,Six Implantations are the post processings after forming collecting zone, for further changing collecting zone 122In defect distribution. In continuous repeatedly the 6th Implantation, can continuously change ImplantationEnergy, to obtain the defect of the peak Distribution such as continuous. For this reason, the energy of the 6th ImplantationBe about 200KeV～600KeV. Adulterant can adopt ion elements to comprise hydrogen, helium, sulphur, oxygenOr selenium, implantation dosage is about 1E11/cm2～1E15/cm2. Preferably, carry out three times continuous theSix Implantations, wherein adopt H+ ion elements as adulterant, and Implantation Energy is respectively600KeV, 400KeV and 200KeV, implantation dosage is respectively 4E13/cm2Thereby, form manyIndividual peak value but the defect area of different depth of roughly waiting.
In this preferred embodiment, by the 4th Implantation and the 6th Implantation at collecting zoneIn 122, produce the defect distribution of expecting. Thereby, even forming after collecting zone 122,At low temperature, anneal, also can realize compared with Gao Di electricity district impurity activation rate.
Further, in alternative embodiment, can adopt irradiation replace the 4th Implantation andThe 5th Implantation. By changing irradiation energy, to make obtaining defect peak in desired depth positionValue, enters identical effect thereby obtain with the 4th Implantation and the 6th Implantation.
The doping content that Figure 12 illustrates semiconductor devices according to an embodiment of the invention respectively and lackFall into and distribute, junction depth in the drawings represents the distance from launch site 113 to collecting zone 122. At theseIn embodiment, adopt H+ ion as adulterant, to produce defect distribution.
As shown in figure 12, according to the semiconductor devices of the second embodiment, before forming collecting zone, enterRow pretreatment, and carry out repeatedly post processing after forming collecting zone. Curved section 11,12 respectivelyThe doping concentration distribution of launch site 113, well region 112 is shown. Curved section 22,23 illustrates respectively in advanceThe impurities concentration distribution of the impurities concentration distribution for the treatment of region 120 and collecting zone 122. Curved section 21After being illustrated in formation collecting electrodes 124, after the heat treatment of certain condition, at semiconductor deviceCollecting zone 122 fronts of part have formed the defect distribution of the defect layer that can accurately control 121.
Owing to adopting repeatedly post processing to obtain, form and multiplely roughly wait lacking of peak values but different depthFall into district, therefore, the final defect layer forming has continuous defect distribution such as peak value such as grade. Therefore, rootCan further improve hole and electronics compound while turn-offing according to the semiconductor devices of the second embodimentRate, reduces the turn-off time of device and estimates turn-off power loss.
Figure 13 illustrates the heat place of the method, semi-conductor device manufacturing method of the embodiment of the present invention and prior artThe curve of relation between reason temperature and the saturation voltage drop of semiconductor devices.
Adopt pretreatment to introduce defect layer according to the method, semi-conductor device manufacturing method of the embodiment of the present invention.Due to the doping compensation effect of defect layer, even also can realize higher in lower heat treatment temperatureDopant activation rate. As shown in the figure, heat treatment temperature is decreased to 400 DEG C, semiconductor device from 500 DEG CThe saturation voltage drop of part still keeps being about 1.72V.
Contrast ground, do not adopt pretreatment according to the method, semi-conductor device manufacturing method of prior art,Lower heat treatment temperature dopant activation rate is lower. As shown in the figure, heat treatment temperature subtracts from 500 DEG CLittle of 400 DEG C, the saturation voltage drop of semiconductor devices is increased to 1.84V left and right from 1.65V.
Saturation voltage drop by above-mentioned contrast different technology conditions converted products can be confirmed, adoptsOne time H+ injects pretreated device, under same heat treatment temperature, its collecting zone impurity swashMotility rate will be higher than not adopting a H+ to inject pretreated device.
The present invention adopted Implantation before the doping of power semiconductor collecting zone Impurity injectionPretreatment, significantly locating in process annealing heat of the collecting zone impurity of hoisting power semiconductor devicesThe activity ratio of reason, and then improve the conduction voltage drop of semiconductor devices, reduce its conduction loss; And,By this ion irradiation processing, can suppress power semiconductor collecting zone impurity heat treatment processIn diffusion junction depth, special, adopt the power semiconductor device of p type impurity doping for collecting zoneThe turn-off power loss of this device, can effectively fall in part; Further, adopt energy more than 200KeVAmount is carried out H+ Implantation/irradiation place at least one times to the lower surface in the preset thickness region retainingReason, the above injections/irradiation energy difference of twice and twice, formation has the peak Distribution such as continuousDefect layer, described defect layer can form in vivo after the heat treatment of uniform temperature conditionExtra complex centre, N-type impurity compensation effect can be played in this complex centre, reduces semiconductorThe minority carrier life time of device, thus reach the object of the switching loss of further reduction semiconductor devices;Moreover the present invention is carrying out H+ ion at least one times to the lower surface in the preset thickness region retainingAfter injection/radiation treatment, the lower surface in the preset thickness region directly retaining in Semiconductor substrate is heavyLong-pending metal level, and then preset thickness region and metal level that Semiconductor substrate is retained carry out heatTreatment process, without carry out extra Technology for Heating Processing after H+ Implantation/irradiation, reducesProcessing step, saved processing cost.
In above description, do not make for the ins and outs such as patterning, etching of each layerDetailed explanation. Can be by various technological means but it will be appreciated by those skilled in the art that,Form layer, the region etc. of required form. In addition, in order to form same structure, art technologyPersonnel can also design and the not identical method of method described above. In addition, althoughEach embodiment is being described respectively above, but this and do not mean that measure in each embodiment is notCan advantageously be combined with.
It should be noted that in this article, the relational terms such as the first and second grades onlyBe used for an entity or operation and another entity or operating space to separate, and not necessarily requirementOr imply the relation or the order that between these entities or operation, there are any this reality. And,Term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability,Thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise that those willElement, but also comprise other key elements of clearly not listing, or be also included as this process,The key element that method, article or equipment are intrinsic. In the situation that there is no more restrictions, by statementThe key element that " comprising one ... " limits, and be not precluded within the process, method, the thing that comprise key elementIn product or equipment, also there is other identical element.
According to embodiments of the invention, as above, these embodiment do not have all thin of detailed descriptiontheJoint, does not limit the specific embodiment that this invention is only yet. Obviously,, according to above description, can do veryMany modifications and variations. These embodiment are chosen and specifically described to this description, is for betterExplain principle of the present invention and practical application, thereby under making, technical field technical staff can be wellUtilize the present invention and the amendment on basis of the present invention to use. The present invention be only subject to claims andThe restriction of its four corner and equivalent.
Claims (17)
1. a manufacture method for semiconductor devices, comprising:
First surface in Semiconductor substrate forms well region, and described Semiconductor substrate and described well region divideIt is not the first doping type;
On described well region, form gate dielectric layer;
On described gate dielectric layer, form grid conductor layer;
In described well region, form the base of the second doping type, described the second doping type with described inThe first doping type is contrary;
In described base, form the launch site of the first doping type;
On described launch site, form emission electrode;
Carry out pretreatment, near the formation pretreating zone, the region second surface of Semiconductor substrate;
Form the collecting zone of the first doping type at the second surface of Semiconductor substrate;
On described collecting zone, form collecting electrodes; And
Carry out the first heat treatment, described the first heat treatment activate the adulterant of the first doped region andNear described collecting zone, form defect layer.
2. method according to claim 1, is forming the step of collecting zone and is forming current collection electricityBetween the step of the utmost point, also comprise: carry out post processing, be positioned at the first doped region in Semiconductor substrate attachedNear region generating defect.
3. method according to claim 1, wherein, described pretreatment by Implantation orIrradiation produces described defect.
4. method according to claim 2, wherein, described post processing by Implantation orIrradiation produces described defect.
5. according to the method described in claim 3 or 4, wherein, what described Implantation adopted mixesAssorted agent is at least one being selected from hydrogen, helium, sulphur, oxygen and selenium.
6. method according to claim 1, wherein, the Implantation adopting in pretreatmentImplantation Energy be 25KeV～500KeV, implantation dosage is 1E11/cm2～1E15/cm2。
7. method according to claim 2, wherein, the Implantation adopting in post processingImplantation Energy be 200KeV～600KeV, implantation dosage is 1E11/cm2～1E15/cm2。
8. method according to claim 2 wherein, is carried out repeatedly implantation in post processingEnter, the Implantation Energy of described repeatedly Implantation successively decreases, and implantation dosage is identical, thereby forms multipleRoughly wait peak value but the defect area of different depth.
9. method according to claim 1, wherein, described the first heat treated temperature isBetween 350 DEG C～420 DEG C, the time is between 10 minutes to 60 minutes.
10. method according to claim 1, is forming the step of collecting zone and is forming current collectionBetween the step of electrode, also comprise the second heat treatment, described the first heat treatment and described the second heat placeReason is common to be activated the adulterant of the first doped region and form defect layer near the first doped region.
11. methods according to claim 10, wherein, described the first heat treated temperature isBetween 400 DEG C～450 DEG C, the time is between 0.5 hour to 2 hours.
12. methods according to claim 1, wherein, the first doping type is for being selected from P typeWith the one in N-type, the second doping type is the another kind being selected from P type and N-type.
13. methods according to claim 1, before carrying out pretreated step, also bagDraw together: carry out reduction processing, to reduce the thickness of described Semiconductor substrate.
14. 1 kinds of semiconductor devices, comprising:
Be arranged in Semiconductor substrate first surface neighbouring well region, described Semiconductor substrate and described trapDistrict is respectively the first doping type;
Be positioned at the gate dielectric layer on described well region;
Be positioned at the grid conductor layer on described gate dielectric layer;
Be arranged in the base of the second doping type of described well region, described the second doping type with described inThe first doping type is contrary;
Be arranged in the launch site of the first doping type of described base;
Be positioned at the emission electrode on described launch site;
Be arranged near the collecting zone of described Semiconductor substrate second surface;
Defect layer, described defect layer is arranged near the region described collecting zone; And
Be positioned at the collecting electrodes on described collecting zone.
15. semiconductor devices according to claim 14, wherein, described defect layer comprises choosingAt least one adulterant in hydrogen, helium, sulphur, oxygen and selenium.
16. semiconductor devices according to claim 14, wherein, described defect layer comprises manyIndividual peak value but the defect area of different depth of roughly waiting.
17. semiconductor devices according to claim 14, the first doping type is for being selected from POne in type and N-type, the second doping type is the another kind being selected from P type and N-type.
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