CN105609419B - Semiconductor devices and its manufacture method - Google Patents
Semiconductor devices and its manufacture method Download PDFInfo
- Publication number
- CN105609419B CN105609419B CN201610104847.3A CN201610104847A CN105609419B CN 105609419 B CN105609419 B CN 105609419B CN 201610104847 A CN201610104847 A CN 201610104847A CN 105609419 B CN105609419 B CN 105609419B
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- type
- doping type
- collecting zone
- zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 124
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 230000007547 defect Effects 0.000 claims abstract description 47
- 238000010438 heat treatment Methods 0.000 claims abstract description 42
- 239000002019 doping agent Substances 0.000 claims abstract description 35
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 238000002513 implantation Methods 0.000 claims description 21
- 238000012545 processing Methods 0.000 claims description 16
- 238000012805 post-processing Methods 0.000 claims description 8
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims description 6
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 6
- 239000005864 Sulphur Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910052711 selenium Inorganic materials 0.000 claims description 6
- 239000011669 selenium Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000009467 reduction Effects 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 2
- 239000012535 impurity Substances 0.000 abstract description 26
- 230000004913 activation Effects 0.000 abstract description 13
- 150000002500 ions Chemical class 0.000 description 65
- 238000000137 annealing Methods 0.000 description 21
- 238000009826 distribution Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000002161 passivation Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000012190 activator Substances 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000001727 in vivo Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Disclose semiconductor devices and its manufacture method.The manufacture method of the semiconductor devices includes：Well region is formed in the first surface of Semiconductor substrate, Semiconductor substrate and well region are respectively reciprocal first doping type and the second doping type；Gate dielectric layer is formed on well region；Grid conductor layer is formed on gate dielectric layer；The base of the second doping type is formed in well region；The launch site of the first doping type is formed in base；Emission electrode is formed on launch site；Pre-processed, the region near the second surface of Semiconductor substrate forms pretreating zone；The collecting zone of the first doping type is formed in the second surface of Semiconductor substrate；Collecting electrodes are formed on collecting zone；And the first heat treatment is carried out, the first heat treatment activates the dopant of the first doped region and is formed about defect layer in collecting zone.This method reduces heat treatment temperature and the high impurity activation of acquisition that semiconductor devices manufactures the later stage by introducing defect layer.
Description
Technical field
The present invention relates to IC manufacturing field, more particularly, to semiconductor devices and its manufacture method.
Background technology
Integrated circuit is included in multiple semiconductor devices that single Semiconductor substrate is formed and is interconnected by wiring.
In integrated circuits, semiconductor devices may be used as power switch or signal processor.Power semiconductor is also known as electricity
Power electronic device, including power diode, IGCT, VDMOS (vertical DMOS) field effect transistor
Pipe, LDMOS (LDMOS) field-effect transistors and IGBT (insulated gate bipolar transistor) etc..
The compound full-control type voltage driven type power half that IGBT is made up of BJT (double pole triode) and FET (field-effect transistor)
Conductor device.IGBT has the advantages of both BJT and FET concurrently, i.e. high input impedance and the characteristics of low conduction voltage drop, therefore with very
Good switching characteristic, is widely used in the field with high pressure, heavy current, for example, alternating current generator, frequency converter,
The fields such as Switching Power Supply, lighting circuit, Traction Drive.
Implanted dopant in the semiconductor substrate is needed in the technique of manufacture power semiconductor, and is annealed,
With activator impurity.For example, when making IGBT, after the first surface formation launch site of Semiconductor substrate, it is also necessary to half
The relative second surface of conductor substrate forms collecting zone.Therefore, first Semiconductor substrate is thinned, to reach predetermined thickness,
Then from the second surface implanted dopant of Semiconductor substrate, then annealed with activator impurity so that mixing in Semiconductor substrate
Miscellaneous area is as collecting zone.However, due to having formed multiple metal levels and doped region in semiconductor devices, therefore, for current collection
The temperature of the annealing in area can not be too high, in case undesirable diffusion occurs for the metal level damage formed, or doped region.Separately
On the one hand, if the annealing temperature is too low, the activity ratio of impurity is low, causes IGBT saturation voltage drops height and switching loss
Greatly.
Therefore, it is desirable to further improve the manufacture method of semiconductor devices so that follow-up impurity activation anneal can be
Also high activity ratio can be realized under cryogenic conditions.
The content of the invention
In order to solve the above technical problems, the present invention provides a kind of semiconductor devices and its manufacture method method, wherein introducing
Defect layer is to reduce the heat treatment temperature in semiconductor devices manufacture later stage and obtain high impurity activation rate.
According to an aspect of the present invention, there is provided a kind of manufacture method of semiconductor devices, including：The of Semiconductor substrate
One surface forms well region, and the Semiconductor substrate and the well region are respectively the first doping type；Grid are formed on the well region
Dielectric layer；Grid conductor layer is formed on the gate dielectric layer；Form the base of the second doping type in the well region, described
Two doping types are opposite with first doping type；The launch site of the first doping type is formed in the base；Described
Emission electrode is formed on launch site；Pre-processed, the region near the second surface of Semiconductor substrate forms pretreating zone；
Semiconductor substrate second surface formed the second doping type collecting zone, wherein, a part for the collecting zone with previously
The pretreating zone of formation is overlapping；Collecting electrodes are formed on the collecting zone；And the first heat treatment is carried out, at first heat
Reason activates the dopant of the collecting zone and is formed about defect layer in the collecting zone.
Preferably, between form collecting zone the step of and the step of forming collecting electrodes, in addition to：Post-processed,
Defect is produced in the region that Semiconductor substrate is located near the collecting zone.
Preferably, the pretreatment and the post processing produce the defect by ion implanting or irradiation.
Preferably, the dopant that the ion implanting uses is selected from least one of hydrogen, helium, sulphur, oxygen and selenium.
Preferably, for 25KeV~500KeV, implantation dosage is the Implantation Energy of the ion implanting used in pretreatment
1E11/cm2~1E15/cm2.
Preferably, for 200KeV~600KeV, implantation dosage is the Implantation Energy of the ion implanting used in post processing
1E11/cm2~1E15/cm2.
Preferably, multiple ion implanting is carried out in post processing, the Implantation Energy of the repeatedly ion implanting successively decreases, injected
Dosage is identical, so as to form multiple the defects of substantially waiting peak value but different depth areas.
Preferably, it is described first heat treatment temperature be 350 DEG C~420 DEG C between, the time be 10 minutes to 60 minutes it
Between.
Preferably, between form collecting zone the step of and the step of forming collecting electrodes, in addition to the second heat treatment, institute
State the dopant of the first heat treatment and second heat treatment the first doped region of common activation and the shape near the first doped region
Into defect layer.
Preferably, it is described second heat treatment temperature be 400 DEG C~450 DEG C between, the time be 0.5 hour to 2 hours it
Between.
Preferably, the first doping type is one kind in p-type and N-type, and the second doping type is selected from p-type and N-type
In another kind.
Preferably, before the step of being pre-processed, in addition to：Reduction processing is carried out, is served as a contrast with reducing the semiconductor
The thickness at bottom.
According to another aspect of the present invention, there is provided a kind of semiconductor devices, including：The first surface in Semiconductor substrate
Neighbouring well region, the Semiconductor substrate and the well region are respectively the first doping type；Gate medium on the well region
Layer；Grid conductor layer on the gate dielectric layer；The base of the second doping type in the well region, described second mixes
Miscellany type is opposite with first doping type；The launch site of the first doping type in the base；Positioned at the hair
The emission electrode penetrated in area；Collecting zone near second surface in the Semiconductor substrate；Defect layer, the defect layer position
In region near the collecting zone；And the collecting electrodes on the collecting zone, wherein, before collecting zone is formed
Region near the second surface of Semiconductor substrate forms pretreating zone, and a part for the collecting zone is pre- with being previously formed
Handle area overlapping.
Preferably, the defect layer is included selected from least one of hydrogen, helium, sulphur, oxygen and selenium dopant.
Preferably, the defect layer includes multiple the defects of substantially waiting peak value but different depth areas.
Preferably, the first doping type is one kind in p-type and N-type, and the second doping type is selected from p-type and N-type
In another kind.
Compared with prior art, the present invention uses ion implanting before the injection doping of semiconductor devices collecting zone impurity
Pretreatment, the activity ratio in Low Temperature Heat Treatment of the collecting zone impurity of semiconductor devices can be obviously improved, and then improve and partly lead
The conduction voltage drop of body device, reduce its conduction loss；Also, handled by the ion irradiation, semiconductor devices collection can be suppressed
Diffusion junction depth in electric area's impurity heat treatment process, particularly, the semiconductor devices of p type impurity doping is used for collecting zone,
The turn-off power loss of the device can effectively drop；
Further, the lower surface in the preset thickness region of reservation is carried out at least once using more than 200KeV energy
H+ ion implantings/radiation treatment, twice and injection more than twice/irradiation energy is different, is formed to have and continuous waits peak value
The defects of distribution layer, it is described the defects of heat treatment of the layer by certain temperature condition after can be formed in vivo it is extra it is compound in
The heart, the complex centre can play N-type impurity compensating action, reduce the minority carrier life time of semiconductor devices, further so as to reach
Reduce the purpose of the switching loss of semiconductor devices；Furthermore the present invention is carried out in the lower surface in the preset thickness region to reservation
After H+ ion implantings/radiation treatment at least once, the lower surface directly in the preset thickness region that Semiconductor substrate retains
Deposited metal layer, the preset thickness region then retained again Semiconductor substrate and metal level carry out Technology for Heating Processing, without
Extra Technology for Heating Processing is carried out after H+ ion implantings/irradiation, reduces processing step, has saved processing cost.
The temperature setting requirement of Technology for Heating Processing can not cause the established upper surface metal level of IGBT device to damage
It is bad, therefore the ratio of the temperature setting of the annealing heat-treats is relatively low, the activity ratio of implanted dopant is not ideal enough at this temperature, causes
The saturation voltage drop of IGBT device is higher.Particularly, for modern IGBT device product, to improve the work of IGBT device frequency
Rate, it will usually using the setting for the collecting zone impurity being lightly doped, now to the activity ratio requirement of collecting zone impurity Low Temperature Heat Treatment
Further lifting.The present invention not only solve semiconductor devices collecting zone implanted dopant in low temperature heat treatment activity ratio compared with
The problem of low, while provide the process program for improving semiconductor device switch frequency.
Brief description of the drawings
By the description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 to 11 shows the sectional view of method, semi-conductor device manufacturing method different phase according to embodiments of the present invention；
Figure 12 shows the doping concentration of semiconductor devices according to an embodiment of the invention respectively and defect distribution；
Figure 13 shows the heat treatment temperature of the method, semi-conductor device manufacturing method of the embodiment of the present invention and prior art with partly leading
The curve of relation between the saturation voltage drop of body device.
Embodiment
The present invention is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.Furthermore, it is possible to it is not shown some
Known part.For brevity, the semiconductor structure that can be obtained described in a width figure after several steps.
It should be appreciated that in the structure of outlines device, it is referred to as when by a floor, a region positioned at another floor, another area
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Other layers or region are also included between individual region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and
And A and B is abutted, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to whole half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
It describe hereinafter many specific details of the present invention, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, it can not press
The present invention is realized according to these specific details.
Unless hereinafter particularly pointing out, the various pieces of semiconductor devices can be by well known to those skilled in the art
Material is formed.Semi-conducting material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC, and IV races semiconductor, such as
Si、Ge。
Fig. 1 to 11 shows the sectional view of method, semi-conductor device manufacturing method different phase according to embodiments of the present invention.At this
In embodiment, the example of semiconductor devices is used as using non-through insulated-gate bipolar transistor (NPT-IGBT).
Igbt (IGBT) is mos field effect transistor (MOS FET) and bipolar junction
The compound power device of transistor npn npn (BJT).Non-through insulated-gate bipolar transistor (NPT-IGBT) uses thin substrate skill
Art, with ion implanted impurity so as to form launch site in the substrate, to replace the epitaxial layer of high complexity and high cost, so as to
To reduce production cost.The present embodiments relate to the further improvement of NPT-IGBT manufacturing process.
In this embodiment, Semiconductor substrate 101 is, for example,<100>Crystal orientation and for n-type doping type silicon wafer.
For example, monocrystalline substrate can be formed using zone-melting process Crystal Growth Technique, and required mix can be doping to
Miscellany type.The doping concentration of monocrystalline substrate can select according to desired resistivity, for example, the semiconductor lining in the embodiment
The doping concentration of bottom 101 can be 5E14/cm3To 5E15/cm3Between, resistivity is preferably between 20~80ohm*cm.
Then, by the first ion implanting, the well region 112 of the first doping type is formed in Semiconductor substrate 101, is such as schemed
Shown in 1, wherein arrow represents the direction of ion implanting.First doping type and the second doping type are on the contrary, be respectively to be selected from N-type
With one kind in p-type.In this embodiment, well region 112 is n-type doping area.
Before ion implantation, photoresist layer is formed in Semiconductor substrate 101, by photoetching by photoresist layer
The mask for including opening is formed, then carries out ion implanting via mask.Block masks of the mask as ion implanting, mask
Well region 112 of the opening portion pattern with that will be formed pattern it is identical.After ion implantation, by dissolving in a solvent or
Ashing removes photoresist layer.
The energy of ion implanting and the dosage of dopant are controlled, depth of the dopant in well region 112 can be controlled and mixed
Miscellaneous concentration distribution.Preferably, well region 112 extends downwardly from the surface of Semiconductor substrate 101 reaches position of the depth more than 10 microns
Put.Therefore, the energy of ion implanting is about 800keV-1500keV, so as to be injected into by high-energy up to desired depth.Example
Such as, in order to form N-type well region 112, P elements or arsenic element can be used as dopant, implantation dosage 5E12/cm2~
5E14/cm2。
Then, gate dielectric layer 114 and grid conductor layer 115 are sequentially formed on the surface of semiconductor structure, as shown in Figure 2.
Gate dielectric layer is, for example, the dielectric layer formed by thermal oxide, or formed by known depositing operation technique
Dielectric layer.Grid conductor layer is, for example, the conductor layer formed by known depositing operation.These known depositing operations include thing
Physical vapor deposition (PVD), chemical vapor deposition (CVD), ald (ALD) etc..In this embodiment, gate dielectric layer is for example
It is the silicon oxide layer formed by thermal oxide, grid conductor layer is, for example, by sputtering the doped polysilicon layer formed, wherein sputtering
It is a kind of technique of physical vapour deposition (PVD).In this embodiment, gate dielectric layer 114 is, for example, 80 nanometers to 150 nanometers of thickness
Silicon oxide layer, grid conductor layer 115 are, for example, the doped polysilicon layer of the N-type of 500 nanometers to 2 microns of thickness.Grid conductor layer 115
Doped resistor rate is, for example, 0.5ohm/sqrt between 50ohm/sqrt.
Then, according to the design needs of the cellular cellular construction of semiconductor devices, additional mask can be used, grid are led
Body layer and gate dielectric layer are patterned to required pattern form, as shown in Figure 3.
Then, by the second ion implanting, the base 111 of the second doping type is formed in well region 112, as shown in figure 4,
Wherein arrow represents the direction of ion implanting.In this embodiment, base 111 is p-type doped region.
During ion implanting, photoresist layer can be used to form mask PR1, to limit the pattern of base 111.Mix
The miscellaneous dose of opening via mask enters in well region 112.
Control ion implanting energy and dopant for dosage so that the bottom surface of base 111 reaches Semiconductor substrate 101
In, side wall is surrounded by well region 112.Therefore, the energy of ion implanting is about 60KeV~120KeV.For example, in order to form p-type base
Area, boron element can be used as dopant, implantation dosage 5E13/cm2~2E15/cm2。
Preferably exist, after the second ion implanting, annealed, to activate the dopant in base 111.The annealing can be with
Carry out in a nitrogen environment, for annealing temperature between 850 DEG C~1050 DEG C, annealing time is between 0.5 hour to 2 hours.
Then, by the 3rd ion implanting, the launch site 113 of the first doping type is formed in base 111, such as Fig. 5 institutes
Show, wherein arrow represents the direction of ion implanting.In this embodiment, launch site 113 is n-type doping area.
During ion implanting, as set forth above, it is possible to mask PR2 be formed using photoresist layer, to limit launch site
113 pattern.Dopant enters in base 111 via the opening of mask.
Control ion implanting energy and dopant for dosage so that the bottom surface of launch site 113 and side wall are by base 111
Surround.Preferably, launch site 113 extends to the position of desired depth in base 111 from the surface of base 111.Therefore, ion is noted
The energy entered is about 60KeV~120KeV.For example, in order to form N-type launch site, P elements or arsenic element can be used to be used as and mix
Miscellaneous dose, implantation dosage 5E13/cm2~2E15/cm2。
Preferably exist, after the 3rd ion implanting, annealed, to activate the dopant in launch site 113.The annealing can
To carry out in a nitrogen environment, for annealing temperature between 850 DEG C~1050 DEG C, annealing time is between 0.5 hour to 2 hours.
As shown in figure 5, grid conductor layer 115 and gate dielectric layer 114 are stacked on above the peripheral part of the base 111, and
And extend laterally on launch site 113 and the surface of Semiconductor substrate 101.As described above, a part of peripheral part of base 111
For forming channel region, grid conductor layer 115 is located above channel region, so as to control the conducting state of channel region.
Then, passivation layer 116 is formed on the surface of semiconductor structure, is etched using mask, the shape in passivation layer 116
Into exposure the surface of launch site 113 opening, as shown in Figure 6.
When forming above-mentioned passivation layer 116, above-mentioned known deposition process can be used on the surface of semiconductor structure
Form insulating barrier.In this embodiment, passivation layer 116 is, for example, the silicon nitride layer formed by sputtering, or passes through chemical gas
The boron phosphorus silicate glass (BPSG) that mutually deposition is formed, between thickness is 600 nanometers to 1.5 microns.
Then, emission electrode 118 is formed on passivation layer 116, the emission electrode 118 is via the opening in passivation layer 116
Launch site 113 is reached, as shown in Figure 7.
On the surface of semiconductor structure, such as by sputtering, conductive material is deposited, the conductive material can at least fill
Opening.It is etched using mask, conductive layer pattern is turned into emission electrode 118.
By above-mentioned each step, in the first surface side of Semiconductor substrate 101, the front for forming semiconductor devices is tied
Structure.It should be appreciated that above-mentioned Facad structure is additionally may included in the partial pressure ring structure (not shown) formed in Semiconductor substrate 101
Deng, and the generation type of above-mentioned Facad structure is also not limited to described above, and this is well known to those skilled in the art interior
Hold, the present invention is not related to the improvement of the part, thus repeats no more.
Then, in the second surface side of Semiconductor substrate 102, reduction processing is carried out, removes section substrate material, is retained pre-
If thickness area.In this step, the thickness of Semiconductor substrate 101 is decreased to TH2 from TH1, as shown in Figure 8.
In reduction processing, chemical-mechanical planarization (CMP) can be carried out, is gone from the second surface of Semiconductor substrate 101
Except the semi-conducting material of predetermined thickness, predetermined thickness Δ TH=TH1-TH2.Preferably, after chemical-mechanical planarization, also
Wet etching can be carried out in the second surface of Semiconductor substrate 101, the wet etching course can make semiconductor lining after being thinned
The stress at bottom is effectively discharged, and can effectively eliminate the mechanical damage layer of semiconductor substrate surface, improves Semiconductor substrate
Surface roughness.
According to IGBT performance parameter come determine Semiconductor substrate 101 be thinned after thickness.With the IGBT devices of 1200V specifications
Exemplified by part, semiconductive substrate thickness can be thinned between 110~240 μm.
Then, by the 4th ion implanting, pretreating zone 120 is formed about in the second surface of Semiconductor substrate 101, such as
Shown in Fig. 9, wherein arrow represents the direction of ion implanting.In this embodiment, the 4th ion implanting be formed collecting zone it
Preceding pretreatment, for producing defect layer near collecting zone.
Control ion implanting energy and dopant for dosage so that pretreating zone 120 extends to Semiconductor substrate 101
Second surface above desired depth position.Therefore, the energy of ion implanting is about 25KeV~500KeV.The pretreating zone
120 dopant can use ion elements to include hydrogen, helium, sulphur, oxygen or selenium, and implantation dosage is about 1E11/cm2~1E15/cm2。
Preferably, the 3rd ion implanting uses H+ ion elements as dopant, Implantation Energy 400KeV, implantation dosage 1E14/
cm2。
Then, by the 5th ion implanting, the second doping type is formed about in the second surface of Semiconductor substrate 101
Collecting zone 122, as shown in Figure 10, wherein arrow represents the direction of ion implanting.In this embodiment, collecting zone 122 is mixed for p-type
Miscellaneous area, abutted with pretreating zone 120.Meanwhile the remainder of Semiconductor substrate 101 is n-type doping area, with base 111 and trap
Area 112 abuts.
Control ion implanting energy and dopant for dosage so that collecting zone 122 from Semiconductor substrate 101 second
Surface extends to the position of internal desired depth.Therefore, the energy of ion implanting is about 25KeV~100Ke.The collecting zone 122
Dopant can be about 5E12/cm using ion elements boron implantation dosage2~5E14/cm2。
Preferably exist, after the 5th ion implanting, annealed, to activate the dopant in collecting zone 122.The annealing can
To carry out in a nitrogen environment, for annealing temperature between 400 DEG C~450 DEG C, annealing time is between 0.5 hour to 2 hours.Should
Work as attention, in the annealing process that activation dopant is carried out, annealing temperature is usually above 800 DEG C, the method for the embodiment of the present invention
The annealing temperature used in collecting zone activation annealing is significantly lower than conventional activation annealing temperature.
As shown in Figure 10, pretreating zone 120 extends to the position of desired depth above the second surface of Semiconductor substrate 101
Put.A part for collecting zone 122 is overlapping with the pretreating zone 120 that previous steps are formed, as will be described, pretreatment
Area 120 will introduce defect near collecting zone 122.
Then, by above-mentioned known deposition process, collecting electrodes 124 are formed on collecting zone 122, as shown in figure 11.
In this embodiment, collecting electrodes are, for example, the metal laminated of Al/Ti/Ni/Ag.
Then, the metal level of the preset thickness region under vacuum or nitrogen protection atmosphere to the reservation and deposition enters
Row heat treatment.In pretreating zone 120 of the heat treatment near collecting zone 122, i.e. front end (the i.e. collecting zone 122 of collecting zone 122
Close to the region of base 111), defect layer 121 is produced, as shown in figure 11.
In heat treatment step, heat treatment temperature and time melt insufficient for the metal level of power semiconductor
Melt.In this embodiment, between the heat treatment temperature under described vacuum and nitrogen protection atmosphere is 350 DEG C~420 DEG C, heat
Processing time is between 10 minutes to 60 minutes.
It should be noted that in the annealing process that activation dopant is carried out, annealing temperature is usually above 800 DEG C, and the present invention is real
Heat treatment temperature of the method for example after collecting electrodes 124 are formed is applied significantly lower than conventional activation annealing temperature.
In the above-described embodiment, defect distribution is produced near collecting zone 122 by pretreating zone 120.Pretreatment can
To be obviously improved the activity ratio of the collecting zone impurity of power semiconductor under cryogenic, and then improve power semiconductor device
The conduction voltage drop of part, reduce its conduction loss.In the ion implanting of pretreatment, it is found through experiments that, wherein using hydrogen (H+)
Effect it is especially pronounced.By taking 600V IGBT products as an example, the pretreatment of H+ injection and different is respectively adopted in the product
Collecting zone impurity heat treatment temperature carries out impurity activation.
In a preferred embodiment, between the step of forming collecting zone 122 and collecting electrodes 124, the above method may be used also
To perform the 6th additional at least once ion implanting.In this embodiment, the 6th ion implanting is after collecting zone is formed
Post processing, for further changing the distribution of the defects of collecting zone 122., can be with continuous multiple 6th ion implanting
The continuous energy for changing ion implanting, the defects of to obtain the peak Distribution such as continuous.Therefore, the energy of the 6th ion implanting is about
For 200KeV~600KeV.Dopant can use ion elements to include hydrogen, helium, sulphur, oxygen or selenium, and implantation dosage is about 1E11/
cm2~1E15/cm2.Preferably, continuous 6th ion implanting three times is performed, wherein using H+ ion elements as dopant,
Implantation Energy is respectively 600KeV, 400KeV and 200KeV, and implantation dosage is respectively 4E13/cm2, so as to formed it is multiple substantially etc.
The defects of peak value but different depth area.
In this preferred embodiment, the phase is produced in collecting zone 122 by the 4th ion implanting and the 6th ion implanting
The defects of prestige, is distributed.Thus, after collecting zone 122 is formed, anneal, can also realize higher at a lower temperature
Di electricity areas impurity activation rate.
Further, in alternate embodiments, irradiation can be used to replace the 4th ion implanting and the 6th ion implanting.
By changing irradiation energy, to obtain defect peak value in desired depth position, so as to obtain and the 4th ion implanting and the
Six ion implantings enter identical effect.
Figure 12 shows the doping concentration of semiconductor devices according to an embodiment of the invention respectively and defect distribution, in figure
Junction depth represent from launch site 113 to the distance of collecting zone 122.In these embodiments, using H+ ions as dopant, with
Produce defect distribution.
As shown in figure 12, according to the semiconductor devices of second embodiment, pre-processed before collecting zone is formed, and
Repeatedly post-processed after collecting zone is formed.Launch site 113, the doping concentration of well region 112 is shown respectively in curved section 11,12
Distribution.The impurities concentration distribution of pretreating zone 120 and the impurities concentration distribution of collecting zone 122 is shown respectively in curved section 22,23.It is bent
Line segment 21 is shown after collecting electrodes 124 are formed, after the heat treatment of certain condition, in the collecting zone of semiconductor devices
One is formd in front of 122 and is distributed the defects of can accurately controlling the defects of layer 121.
Due to being obtained using multiple post processing, multiple the defects of substantially waiting peak value but different depth areas are formed, therefore, most
End form into the defects of layer have and continuous wait peak value defect distribution.Therefore, can be entered according to the semiconductor devices of second embodiment
One step improves hole when turning off and the recombination rate of electronics, reduces the turn-off time estimated turn-off power loss of device.
Figure 13 shows the heat treatment temperature of the method, semi-conductor device manufacturing method of the embodiment of the present invention and prior art with partly leading
The curve of relation between the saturation voltage drop of body device.
Method, semi-conductor device manufacturing method according to embodiments of the present invention introduces defect layer using pretreatment.Due to defect layer
Doping compensation acts on, even in can also realize higher dopant activation rate compared with low heat-treatment temperature.As illustrated, heat treatment
Temperature is decreased to 400 DEG C from 500 DEG C, and the saturation voltage drop of semiconductor devices remains in that about 1.72V.
In contradistinction to, according to the method, semi-conductor device manufacturing method of prior art not using pre-processing, in relatively low heat treatment temperature
It is relatively low to spend dopant activation rate.As illustrated, heat treatment temperature is decreased to 400 DEG C from 500 DEG C, the saturation voltage of semiconductor devices
Drop is increased to 1.84V or so from 1.65V.
By the saturation voltage drop of above-mentioned contrast different technology conditions converted products it has been confirmed that pre- using a H+ injection
The device of processing, under same heat treatment temperature, the activity ratio of its collecting zone impurity is higher than not using a H+ injection in advance
The device of processing.
The present invention uses the pretreatment of ion implanting before the injection doping of power semiconductor collecting zone impurity, can be with
The activity ratio in process annealing heat treatment of the collecting zone impurity of power semiconductor is obviously improved, and then improves semiconductor device
The conduction voltage drop of part, reduce its conduction loss；Also, handled by the ion irradiation, power semiconductor collection can be suppressed
Diffusion junction depth in electric area's impurity heat treatment process, particularly, the power semiconductor device of p type impurity doping is used for collecting zone
Part, the turn-off power loss of the device can effectively drop；Further, using more than 200KeV energy to the preset thickness area of reservation
The lower surface in domain carries out H+ ion implantings/radiation treatment at least once, and injection/irradiation energy is not twice and more than twice
Together, being formed can after having heat treatment of the defects of the defects of peak Distribution such as continuous layer, described layer by certain temperature condition
To form extra complex centre in vivo, the complex centre can play N-type impurity compensating action, reduce semiconductor devices
Minority carrier life time, so as to reach the purpose for the switching loss for further reducing semiconductor devices；Furthermore the present invention is to the pre- of reservation
After if the lower surface of thickness area carries out H+ ion implantings/radiation treatment at least once, directly retain in Semiconductor substrate
Preset thickness region lower surface deposited metal layer, then again to Semiconductor substrate retain preset thickness region and metal
Layer carries out Technology for Heating Processing, without carrying out extra Technology for Heating Processing after H+ ion implantings/irradiation, reduces technique step
Suddenly, processing cost has been saved.
In the above description, the ins and outs such as the patterning for each layer, etching are not described in detail.But
It is it will be appreciated by those skilled in the art that can be by various technological means, to form the layer of required shape, region etc..In addition,
In order to form same structure, those skilled in the art can be devised by and process as described above not fully identical side
Method.In addition, although respectively describing each embodiment more than, but it is not intended that the measure in each embodiment can not have
It is used in combination sharply.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply and deposited between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Other identical element also be present in process, method, article or equipment including key element.
For example above according to embodiments of the invention, these embodiments do not have all details of detailed descriptionthe, do not limit yet
The specific embodiment that the invention is only.Obviously, as described above, can make many modifications and variations.This specification is chosen simultaneously
These embodiments are specifically described, are in order to preferably explain the principle and practical application of the present invention, so that art
Technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention only by claims and
The limitation of its four corner and equivalent.
Claims (17)
1. a kind of manufacture method of semiconductor devices, including：
Well region is formed in the first surface of Semiconductor substrate, the Semiconductor substrate and the well region are respectively the first doping class
Type；
Gate dielectric layer is formed on the well region；
Grid conductor layer is formed on the gate dielectric layer；
The base of the second doping type, second doping type and the first doping type phase are formed in the well region
Instead；
The launch site of the first doping type is formed in the base；
Emission electrode is formed on the launch site；
Pre-processed, the region near the second surface of Semiconductor substrate forms pretreating zone；
Semiconductor substrate second surface formed the second doping type collecting zone, wherein, a part for the collecting zone with
The pretreating zone being previously formed is overlapping；
Collecting electrodes are formed on the collecting zone；And
The first heat treatment is carried out, first heat treatment activates the dopant of the pretreating zone and near the collecting zone
Formation has the defects of defect layer.
2. according to the method for claim 1, also wrapped between forms collecting zone the step of and the step of formation collecting electrodes
Include：Post-processed, defect is produced in the region that Semiconductor substrate is located near collecting zone.
3. according to the method for claim 1, wherein, the pretreatment produces the defect by ion implanting or irradiation.
4. according to the method for claim 2, wherein, the post processing produces the defect by ion implanting or irradiation.
5. the method according to claim 3 or 4, wherein, the dopant that the ion implanting uses for selected from hydrogen, helium, sulphur,
At least one of oxygen and selenium.
6. according to the method for claim 1, wherein, the Implantation Energy of the ion implanting used in pretreatment is 25KeV
~500KeV, implantation dosage 1E11/cm2~1E15/cm2。
7. according to the method for claim 2, wherein, the Implantation Energy of the ion implanting used in post processing is 200KeV
~600KeV, implantation dosage 1E11/cm2~1E15/cm2。
8. according to the method for claim 2, wherein, multiple ion implanting, more secondary ion notes are carried out in post processing
The Implantation Energy entered successively decreases, and implantation dosage is identical, so as to form multiple the defects of waiting peak value but different depth areas.
9. the method according to claim 11, wherein, between the described first temperature being heat-treated is 350 DEG C~420 DEG C, when
Between be 10 minutes to 60 minutes between.
10. according to the method for claim 1, between forms collecting zone the step of and the step of forming collecting electrodes, and also
Including the second heat treatment, second heat treatment activates the dopant of the collecting zone.
11. the method according to claim 11, wherein, between the described second temperature being heat-treated is 400 DEG C~450 DEG C,
Time is between 0.5 hour to 2 hours.
12. according to the method for claim 1, wherein, the first doping type is one kind in p-type and N-type, and second mixes
Miscellany type is the another kind in p-type and N-type.
13. according to the method for claim 1, before the step of being pre-processed, in addition to：Reduction processing is carried out, with
Reduce the thickness of the Semiconductor substrate.
14. a kind of semiconductor devices, including：
Well region near first surface in Semiconductor substrate, the Semiconductor substrate and the well region are respectively the first doping
Type；
Gate dielectric layer on the well region；
Grid conductor layer on the gate dielectric layer；
The base of the second doping type in the well region, second doping type and the first doping type phase
Instead；
The launch site of the first doping type in the base；
Emission electrode on the launch site；
Collecting zone near second surface in the Semiconductor substrate；
Defect layer, the defect layer are located in the region near the collecting zone；And
Collecting electrodes on the collecting zone；
Wherein, the region near the second surface before collecting zone is formed in Semiconductor substrate forms pretreating zone, the collection
The part in electric area is overlapping with the pretreating zone being previously formed.
15. semiconductor devices according to claim 14, wherein, the defect layer includes being selected from hydrogen, helium, sulphur, oxygen and selenium
At least one of dopant.
16. semiconductor devices according to claim 14, wherein, the defect layer includes the peak values such as multiple but different depth
The defects of area.
17. semiconductor devices according to claim 14, the first doping type is one kind in p-type and N-type, second
Doping type is the another kind in p-type and N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610104847.3A CN105609419B (en) | 2016-02-25 | 2016-02-25 | Semiconductor devices and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610104847.3A CN105609419B (en) | 2016-02-25 | 2016-02-25 | Semiconductor devices and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105609419A CN105609419A (en) | 2016-05-25 |
| CN105609419B true CN105609419B (en) | 2018-03-13 |
Family
ID=55989246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610104847.3A Active CN105609419B (en) | 2016-02-25 | 2016-02-25 | Semiconductor devices and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105609419B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712885A (en) * | 2018-12-17 | 2019-05-03 | 成都森未科技有限公司 | A kind of semiconductor devices buffering layer manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436542A (en) * | 2008-12-19 | 2009-05-20 | 北京工业大学 | Method for manufacturing insulated gate bipolar transistor with variable buffer layer concentration inner transparent collecting zone |
| CN103594466A (en) * | 2013-11-27 | 2014-02-19 | 杭州士兰集成电路有限公司 | Power semiconductor device integrating fly-wheel diode and forming method thereof |
| CN104078354A (en) * | 2013-03-26 | 2014-10-01 | 杭州士兰集成电路有限公司 | Power semiconductor device and manufacturing method thereof |
| CN205508777U (en) * | 2016-02-25 | 2016-08-24 | 杭州士兰集成电路有限公司 | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009283818A (en) * | 2008-05-26 | 2009-12-03 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2010147239A (en) * | 2008-12-18 | 2010-07-01 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
-
2016
- 2016-02-25 CN CN201610104847.3A patent/CN105609419B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436542A (en) * | 2008-12-19 | 2009-05-20 | 北京工业大学 | Method for manufacturing insulated gate bipolar transistor with variable buffer layer concentration inner transparent collecting zone |
| CN104078354A (en) * | 2013-03-26 | 2014-10-01 | 杭州士兰集成电路有限公司 | Power semiconductor device and manufacturing method thereof |
| CN103594466A (en) * | 2013-11-27 | 2014-02-19 | 杭州士兰集成电路有限公司 | Power semiconductor device integrating fly-wheel diode and forming method thereof |
| CN205508777U (en) * | 2016-02-25 | 2016-08-24 | 杭州士兰集成电路有限公司 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105609419A (en) | 2016-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI553857B (en) | Semiconductor substrate structure, semiconductor power devices, improved injection control in semiconductor power devices | |
| JP5272410B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN104769723B (en) | Groove power semiconductor field-effect transistor | |
| US9941383B2 (en) | Fast switching IGBT with embedded emitter shorting contacts and method for making same | |
| CN109841616B (en) | Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device | |
| US9443926B2 (en) | Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor | |
| US11139292B2 (en) | Conductivity modulated drain extended MOSFET | |
| CN103477439A (en) | Semiconductor device and process for production thereof | |
| WO2018082455A1 (en) | Power device and manufacturing method therefor | |
| CN107039268A (en) | The manufacture method of manufacturing silicon carbide semiconductor device and manufacturing silicon carbide semiconductor device | |
| CN103337498A (en) | BCD semiconductor device and manufacturing method thereof | |
| CN107910266A (en) | Power semiconductor and its manufacture method | |
| US20220157988A1 (en) | Power semiconductor device and fabrication method thereof | |
| WO2018000223A1 (en) | Insulated gate bipolar transistor structure and manufacturing method therefor | |
| CN107910269A (en) | Power semiconductor and its manufacture method | |
| CN114188400A (en) | NPN power SiGe bipolar transistor and manufacturing method thereof | |
| CN105609419B (en) | Semiconductor devices and its manufacture method | |
| US20180301548A1 (en) | Silicon carbide transistor | |
| JP2005101255A (en) | High breakdown-voltage semiconductor device | |
| CN107004578A (en) | Method for manufacturing the semiconductor devices for including film, semiconductor wafer | |
| CN107910268A (en) | Power semiconductor and its manufacture method | |
| US11626325B2 (en) | Method of making a silicon carbide integrated circuit | |
| CN205508777U (en) | Semiconductor device | |
| CN104347403B (en) | A kind of manufacture method of insulated gate bipolar transistor | |
| CN109148304A (en) | A kind of transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |