CN111370473A - Groove type device and preparation method thereof - Google Patents

Groove type device and preparation method thereof Download PDF

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Publication number
CN111370473A
CN111370473A CN202010211835.7A CN202010211835A CN111370473A CN 111370473 A CN111370473 A CN 111370473A CN 202010211835 A CN202010211835 A CN 202010211835A CN 111370473 A CN111370473 A CN 111370473A
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layer
medium layer
insulating medium
substrate
etching
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胡强
金涛
秦潇峰
王思亮
蒋兴莉
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Semi Future Technology Co
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Semi Future Technology Co
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

The utility model relates to a semiconductor manufacturing field, especially a trench type device and preparation method thereof, including the substrate, be provided with the body region on the substrate, be provided with the second conducting layer on the body region, be provided with first insulating medium layer in the second conducting layer, first insulating medium layer below is provided with the grid dielectric layer, and grid dielectric layer below is provided with the second insulating medium layer, first insulating medium layer, grid dielectric layer and second insulating medium layer intercommunication, the grid dielectric layer is located the body region, the second insulating medium layer is located the substrate, is provided with first conducting layer in grid dielectric layer and second insulating medium layer, the degree of depth of first conducting layer is not less than the degree of depth in body region. In the structure of the present application, the depth of the gate electrode inside the trench may be different from the depth of the trench. The structure is applied to IGBT design, the carrier injection effect can be enhanced, and the conduction loss of the IGBT can be reduced.

Description

Groove type device and preparation method thereof
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a trench type device and a preparation method thereof.
Background
In the course of the development of voltage-controlled power semiconductor devices, trenches have been introduced in order to achieve higher current densities on smaller chips. Research and practice have proved that the depth of the groove can change the carrier concentration distribution of the device in the on state. Such devices include power MOS, IGBT, etc. Next, a 600V200A IGBT is taken as an example, and as shown in fig. 2, the active region depth is fixed at 11um, the trench width is fixed at 1.5um, and the trench depths are changed to 5um, 10um, and 15um, respectively. However, it is found from the research results that as the depth of the trench increases, the distribution of internal carriers is as shown in fig. 11, and particularly, the charge accumulation effect of the outer wall of the trench increases, and the on-voltage drop of the IGBT tends to decrease.
Although the increase of the depth of the trench can effectively reduce the operating loss of the device, in the conventional trench gate structure, the electrode inside the trench also increases along with the increase of the depth of the trench, so that the potential difference near the bottom of the trench increases, the electric field on the side wall of the trench increases, and the increase of the depth of the trench is limited by the effect.
Disclosure of Invention
In order to overcome the problems in the prior art, a trench type device and a manufacturing method thereof are provided, which can ensure that the depth of an electrode inside a trench is not necessarily related to the depth of the trench, thereby effectively avoiding the above effects and further greatly improving the design space of the device.
In order to achieve the technical effects, the technical scheme of the application is as follows:
a trench device, comprising: the high-voltage switch comprises a substrate, wherein a body region is arranged on the substrate, a second conducting layer is arranged on the body region, a first insulating medium layer is arranged in the second conducting layer, a grid medium layer is arranged below the first insulating medium layer, a second insulating medium layer is arranged below the grid medium layer, the first insulating medium layer, the grid medium layer and the second insulating medium layer are communicated, the grid medium layer is located in the body region, the second insulating medium layer is located in the substrate, a first conducting layer is arranged in the grid medium layer and the second insulating medium layer, and the depth of the first conducting layer is not smaller than that of the body region.
Furthermore, a source region is arranged between the body region and the second conductive layer, and the source region is positioned below the first insulating medium layer.
Further, the substrate material includes, but is not limited to, silicon carbide, gallium nitride, gallium arsenide, or diamond, and the conductivity type is P-type or N-type.
Further, the doping concentration of the source region is higher than that of the substrate, and the doping impurities comprise phosphorus, arsenic, selenium or sulfur.
Further, the materials of the first insulating dielectric layer, the gate dielectric layer and the second insulating dielectric layer include, but are not limited to, silicon oxide, silicon nitride or aluminum oxide.
Furthermore, the first insulating medium layer, the gate medium layer and the second insulating medium layer are made of the same material.
The grid dielectric layer, the first conducting layer and the body region form a grid structure of the field effect transistor.
Further, the first conductive layer is a gate, the second conductive layer is an electrode, and the materials of the first conductive layer and the second conductive layer include, but are not limited to, polysilicon, doped polysilicon, aluminum metal, copper, titanium, tungsten, and their stacks or alloys, and alloys of the above metals and silicon.
A preparation method of a groove type device is characterized by comprising the following steps:
the method comprises the following steps: performing field oxide growth on a substrate, not limited to a silicon substrate, as shown in fig. 3;
step two: exposing a part of the field oxide layer by using a photoetching plate, and etching away to expose the substrate, as shown in FIG. 4;
step three: performing trench etching on the exposed substrate portion, as shown in fig. 5;
step four: depositing to obtain a second insulating medium layer as shown in FIG. 6;
step five: etching part of the second insulating medium layer, and reserving parts around the groove and at the bottom, as shown in FIG. 7;
step six: growing a gate dielectric layer on the side wall of the groove and the upper surface of the substrate, as shown in FIG. 8;
step seven: depositing to obtain a first conductive layer, as shown in fig. 9;
step eight: etching a part of the first conductive layer and remaining a part in the trench, as shown in fig. 10;
step nine: the gate structure is formed by conventional power MOSFET processing, and the depth of the remaining portion of the first conductive layer is not less than the thickness of the body region, as shown in fig. 1.
Further, the thickness of the hard film of the field oxide layer in the first step is 3000A-10000A;
further, the etching of the groove in the third step is dry etching;
further, the longitudinal thickness of the second insulating medium layer in the fourth step is 10000A-50000A; the second insulating dielectric layer deposition process is PECVD or LPCVD;
further, in the fifth step, wet etching is carried out on the second insulating medium layer through an etching process;
further, the etching process of the hard film of the field oxide layer in the sixth step is dry etching; the thickness of the gate dielectric layer is 100A-2000A;
further, in the seventh step, the deposition process of the first conductive layer is PECVD or LPCVD;
further, the etching process of the first conductive layer in the eighth step is dry etching;
further, the longitudinal thickness of the first insulating medium layer is 2000A-10000A; the etching process of the first insulating medium layer is dry etching or wet etching; the thickness of the second conductive layer is 1um-5um, and the deposition process is evaporation or sputtering.
The application has the advantages that:
the first conducting layer in the groove, namely the groove internal electrode, is filled with the second insulating layer between the bottom of the first conducting layer and the bottom of the groove, and the longitudinal thickness of the second insulating layer can be adjusted according to design. In the conventional trench design, only a thin gate dielectric layer is filled between the bottom of the electrode inside the trench and the bottom of the trench, and the depth of the electrode is almost the same as that of the trench. The depth of the gate electrode inside the trench may be different from the trench depth in the structure of the present application. The structure is applied to IGBT design, the carrier injection effect can be enhanced, and the conduction loss of the IGBT can be reduced. The method has the advantages that compared with the traditional groove structure, the manufacturing process is slightly changed, and an additional photomask and a layout are not needed.
Drawings
Fig. 1 is a schematic overall view of the device structure of the present application.
Fig. 2 is a schematic diagram of a prior art structure.
Fig. 3-10 are schematic views of the process structure of the present application.
FIG. 11 is a graph showing the depth of a trench and the distribution of internal carriers in the prior art.
In the drawings: 101-substrate, 102-source region, 201-body region, 301-first insulating dielectric layer, 302-gate dielectric layer, 303-second insulating dielectric layer, 401-first conducting layer, 501-second conducting layer.
Detailed Description
Example 1
The trench type device comprises a substrate 101, wherein a body region 201 is arranged on the substrate 101, a second conducting layer 501 is arranged on the body region 201, a first insulating medium layer 301 is arranged in the second conducting layer 501, a grid medium layer 302 is arranged below the first insulating medium layer 301, a second insulating medium layer 303 is arranged below the grid medium layer 302, the first insulating medium layer 301, the grid medium layer 302 and the second insulating medium layer 303 are communicated, the grid medium layer 302 is located in the body region 201, the second insulating medium layer 303 is located in the substrate 101, a first conducting layer 401 is arranged in the grid medium layer 302 and the second insulating medium layer 303, and the depth of the first conducting layer 401 is not smaller than that of the body region 201.
A source region 102 is disposed between the body region 201 and the second conductive layer 501, and the source region 102 is located below the first insulating medium layer 301.
The material of the substrate 101 includes, but is not limited to, silicon carbide, gallium nitride, gallium arsenide, or diamond, and the conductivity type is P-type or N-type.
The doping concentration of the source region 102 is higher than that of the substrate 101, and the doping impurities include phosphorus, arsenic, selenium or sulfur.
The materials of the first insulating dielectric layer 301, the gate dielectric layer 302 and the second insulating dielectric layer 303 include, but are not limited to, silicon oxide, silicon nitride or aluminum oxide. The first insulating dielectric layer 301, the gate dielectric layer 302 and the second insulating dielectric layer 303 are made of the same material.
The gate dielectric layer 302 forms a gate structure of the field effect transistor with the first conductive layer 401 and the body region 201.
The first conductive layer 401 is a gate, the second conductive layer 501 is an electrode, and the materials of the first conductive layer 401 and the second conductive layer 501 include, but are not limited to, polysilicon, doped polysilicon, aluminum metal, copper, titanium, tungsten, and their stacks or alloys, and alloys of the above metals and silicon.
Example 2
A preparation method of a groove-type device comprises the following steps:
the method comprises the following steps: performing field oxide layer growth on the substrate 101, not limited to the silicon substrate 101, as shown in fig. 3;
step two: using a photolithography mask, exposing a portion of the field oxide layer, and etching away to expose the substrate 101, as shown in fig. 4;
step three: performing a trench etch on the exposed portion of the substrate 101, as shown in fig. 5;
step four: depositing to obtain a second insulating medium layer 303, as shown in fig. 6;
step five: etching a part of the second insulating dielectric layer 303, and reserving a part around and at the bottom of the trench, as shown in fig. 7;
step six: growing a gate dielectric layer 302 on the sidewall of the trench and the upper surface of the substrate 101, as shown in fig. 8;
step seven: depositing a first conductive layer 401, as shown in fig. 9;
step eight: etching a part of the first conductive layer 401 and remaining a part in the trench, as shown in fig. 10;
step nine: the gate structure is formed by conventional power MOSFET processing and the depth of the remaining portion of the first conductive layer 401 is not less than the thickness of the body region 201, as shown in fig. 1.
In the first step, the hard film thickness of the field oxide layer is 3000A-10000A; the etching of the groove in the third step is dry etching; in the fourth step, the longitudinal thickness of the second insulating medium layer 303 is 10000A-50000A; the second insulating dielectric layer 303 is deposited by PECVD or LPCVD; etching the second insulating medium layer 303 in the step five by using an etching process; in the sixth step, the etching process of the hard film of the field oxide layer is dry etching; the thickness of the gate dielectric layer 302 is 100A-2000A; in the seventh step, the deposition process of the first conductive layer 401 is PECVD or LPCVD; in the eighth step, the etching process of the first conductive layer 401 is dry etching; the longitudinal thickness of the first insulating medium layer 301 is 2000A-10000A; the etching process of the first insulating medium layer 301 is dry etching or wet etching; the thickness of the second conductive layer 501 is 1um-5um, and the deposition process is evaporation or sputtering.
Example 3
The trench type device comprises a substrate 101, wherein a body region 201 is arranged on the substrate 101, a second conducting layer 501 is arranged on the body region 201, a first insulating medium layer 301 is arranged in the second conducting layer 501, a grid medium layer 302 is arranged below the first insulating medium layer 301, a second insulating medium layer 303 is arranged below the grid medium layer 302, the first insulating medium layer 301, the grid medium layer 302 and the second insulating medium layer 303 are communicated, the grid medium layer 302 is located in the body region 201, the second insulating medium layer 303 is located in the substrate 101, a first conducting layer 401 is arranged in the grid medium layer 302 and the second insulating medium layer 303, and the depth of the first conducting layer 401 is not smaller than that of the body region 201.
A source region 102 is disposed between the body region 201 and the second conductive layer 501, and the source region 102 is located below the first insulating medium layer 301.
The material of the substrate 101 includes, but is not limited to, silicon carbide, gallium nitride, gallium arsenide, or diamond, and the conductivity type is P-type or N-type.
The doping concentration of the source region 102 is higher than that of the substrate 101, and the doping impurities include phosphorus, arsenic, selenium or sulfur.
The materials of the first insulating dielectric layer 301, the gate dielectric layer 302 and the second insulating dielectric layer 303 include, but are not limited to, silicon oxide, silicon nitride or aluminum oxide. The first insulating dielectric layer 301, the gate dielectric layer 302 and the second insulating dielectric layer 303 are made of the same material.
The gate dielectric layer 302 forms a gate structure of the field effect transistor with the first conductive layer 401 and the body region 201.
The first conductive layer 401 is a gate, the second conductive layer 501 is an electrode, and the materials of the first conductive layer 401 and the second conductive layer 501 include, but are not limited to, polysilicon, doped polysilicon, aluminum metal, copper, titanium, tungsten, and their stacks or alloys, and alloys of the above metals and silicon.
A preparation method of a groove-type device comprises the following steps:
the method comprises the following steps: performing field oxide layer growth on the substrate 101, not limited to the silicon substrate 101, as shown in fig. 3;
step two: using a photolithography mask, exposing a portion of the field oxide layer, and etching away to expose the substrate 101, as shown in fig. 4;
step three: performing a trench etch on the exposed portion of the substrate 101, as shown in fig. 5;
step four: depositing to obtain a second insulating medium layer 303, as shown in fig. 6;
step five: etching a part of the second insulating dielectric layer 303, and reserving a part around and at the bottom of the trench, as shown in fig. 7;
step six: growing a gate dielectric layer 302 on the sidewall of the trench and the upper surface of the substrate 101, as shown in fig. 8;
step seven: depositing a first conductive layer 401, as shown in fig. 9;
step eight: etching a part of the first conductive layer 401 and remaining a part in the trench, as shown in fig. 10;
step nine: the gate structure is formed by conventional power MOSFET processing and the depth of the remaining portion of the first conductive layer 401 is not less than the thickness of the body region 201, as shown in fig. 1.
In the first step, the thickness of the hard film of the field oxide layer is 6000A; the etching of the groove in the third step is dry etching; in the fourth step, the longitudinal thickness of the second insulating medium layer 303 is 30000A; the second insulating dielectric layer 303 is deposited by PECVD or LPCVD; etching the second insulating medium layer 303 in the step five by using an etching process; in the sixth step, the etching process of the hard film of the field oxide layer is dry etching; the thickness of the gate dielectric layer 302 is 100A-2000A; in the seventh step, the deposition process of the first conductive layer 401 is PECVD or LPCVD; in the eighth step, the etching process of the first conductive layer 401 is dry etching; the longitudinal thickness of the first insulating medium layer 301 is 50000A; the etching process of the first insulating medium layer 301 is dry etching or wet etching; the second conductive layer 501 is 3um thick and the deposition process is evaporation or sputtering.

Claims (10)

1. A trench device, comprising: the high-voltage power supply comprises a substrate (101), wherein a body region (201) is arranged on the substrate (101), a second conducting layer (501) is arranged on the body region (201), a first insulating medium layer (301) is arranged in the second conducting layer (501), a grid medium layer (302) is arranged below the first insulating medium layer (301), a second insulating medium layer (303) is arranged below the grid medium layer (302), the first insulating medium layer (301), the grid medium layer (302) and the second insulating medium layer (303) are communicated, the grid medium layer (302) is located in the body region (201), the second insulating medium layer (303) is located in the substrate (101), a first conducting layer (401) is arranged in the grid medium layer (302) and the second insulating medium layer (303), and the depth of the first conducting layer (401) is not less than that of the body region (201).
2. A trench type device as claimed in claim 1, wherein: a source region (102) is arranged between the body region (201) and the second conductive layer (501), and the source region (102) is located below the first insulating medium layer (301).
3. A trench type device as claimed in claim 1, wherein: the material of the substrate (101) comprises but is not limited to silicon, silicon carbide, gallium nitride, gallium arsenide or diamond, and the conductivity type is P type or N type; the materials of the first insulating medium layer (301), the gate medium layer (302) and the second insulating medium layer (303) include, but are not limited to, silicon oxide, silicon nitride or aluminum oxide.
4. A trench type device as claimed in claim 1, wherein: the source region (102) is doped with a higher concentration than the substrate (101), and the doping impurities include phosphorus, arsenic, selenium or sulfur.
5. A trench type device as claimed in claim 1, wherein: the first conductive layer (401) is a gate, the second conductive layer (501) is an electrode, and the materials of the first conductive layer (401) and the second conductive layer (501) include, but are not limited to, polysilicon, doped polysilicon, aluminum metal, copper, titanium, tungsten, and their stacked layers or alloys, and alloys of the above metals and silicon.
6. A preparation method of a groove type device is characterized by comprising the following steps: the method comprises the following steps:
the method comprises the following steps: growing a field oxide layer on a substrate (101);
step two: exposing a part of the field oxide layer by using a photoetching plate, and etching away to expose the substrate (101);
step three: performing trench etching on the exposed substrate (101) portion;
step four: depositing to obtain a second insulating medium layer (303);
step five: etching part of the second insulating medium layer (303), and reserving parts around the groove and at the bottom;
step six: growing a gate dielectric layer (302) on the side wall of the groove and the upper surface of the substrate (101);
step seven: depositing to obtain a first conductive layer (401);
step eight: etching part of the first conductive layer (401) and reserving part in the groove;
step nine: the gate structure is formed by conventional power MOSFET fabrication processes, and the depth of the remaining portion of the first conductive layer 401 is ensured to be no less than the thickness of the body region 201.
7. The method of claim 6, wherein: in the first step, the hard film thickness of the field oxide layer is 3000A-10000A; and the etching of the groove in the third step is dry etching.
8. The method of claim 6, wherein: in the fourth step, the longitudinal thickness of the second insulating medium layer (303) is 10000A-50000A; the second insulating dielectric layer (303) is deposited by PECVD or LPCVD; and etching the second insulating dielectric layer (303) in the step five by using a wet etching process.
9. The method of claim 6, wherein: in the sixth step, the etching process of the hard film of the field oxide layer is dry etching; the thickness of the gate dielectric layer (302) is 100A-2000A; in the seventh step, the deposition process of the first conductive layer (401) is PECVD or LPCVD; and the etching process of the first conductive layer (401) in the step eight is dry etching.
10. The method of claim 6, wherein: the longitudinal thickness of the first insulating medium layer (301) is 2000A-10000A; the etching process of the first insulating medium layer (301) is dry etching or wet etching; the thickness of the second conducting layer (501) is 1um-5um, and the deposition process is evaporation or sputtering.
CN202010211835.7A 2020-03-24 2020-03-24 Groove type device and preparation method thereof Pending CN111370473A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112397479A (en) * 2020-11-25 2021-02-23 思瑞浦微电子科技（苏州）股份有限公司 Isolation capacitor and preparation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030089946A1 (en) * 2001-11-15 2003-05-15 Fwu-Iuan Hshieh Trench MOSFET having low gate charge
US20040166636A1 (en) * 2001-07-03 2004-08-26 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
TW201130052A (en) * 2010-02-26 2011-09-01 Vanguard Int Semiconduct Corp Fabrication methods for trench MOSFET
CN102194694A (en) * 2010-03-05 2011-09-21 世界先进积体电路股份有限公司 Method for manufacturing groove-type metal-oxide-semiconductor field-effect transistor
JP2012216675A (en) * 2011-03-31 2012-11-08 Toyota Motor Corp Semiconductor device and manufacturing method of the same
US20120309200A1 (en) * 2011-06-02 2012-12-06 Charlie Tay Method for fabricating a bottom oxide layer in a trench
CN109473474A (en) * 2018-11-09 2019-03-15 上海擎茂微电子科技有限公司 Insulated trench gate electrode bipolar type transistor device and its generation method
CN109712885A (en) * 2018-12-17 2019-05-03 成都森未科技有限公司 A kind of semiconductor devices buffering layer manufacturing method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040166636A1 (en) * 2001-07-03 2004-08-26 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
US20030089946A1 (en) * 2001-11-15 2003-05-15 Fwu-Iuan Hshieh Trench MOSFET having low gate charge
TW201130052A (en) * 2010-02-26 2011-09-01 Vanguard Int Semiconduct Corp Fabrication methods for trench MOSFET
CN102194694A (en) * 2010-03-05 2011-09-21 世界先进积体电路股份有限公司 Method for manufacturing groove-type metal-oxide-semiconductor field-effect transistor
JP2012216675A (en) * 2011-03-31 2012-11-08 Toyota Motor Corp Semiconductor device and manufacturing method of the same
US20120309200A1 (en) * 2011-06-02 2012-12-06 Charlie Tay Method for fabricating a bottom oxide layer in a trench
CN109473474A (en) * 2018-11-09 2019-03-15 上海擎茂微电子科技有限公司 Insulated trench gate electrode bipolar type transistor device and its generation method
CN109712885A (en) * 2018-12-17 2019-05-03 成都森未科技有限公司 A kind of semiconductor devices buffering layer manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112397479A (en) * 2020-11-25 2021-02-23 思瑞浦微电子科技（苏州）股份有限公司 Isolation capacitor and preparation method thereof

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