RU2807501C1 - Semiconductor structure and method of its manufacture - Google Patents

Abstract

FIELD: semiconductors.

SUBSTANCE: embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: base; bit lines disposed on the substrate, wherein the bit line material includes a metal-semiconductor chemical compound; semiconductor channels, each of which includes a first doped region, a channel region and a second doped region arranged in series, the first doped region being in contact with a bit line; the first dielectric layer covering the side wall surfaces of the first doped regions, between portions of the first dielectric layer covering the side walls of adjacent first doped regions on the same bit line, the first interval is provided.

EFFECT: creation of a semiconductor structure with improved electrical characteristics in the structure of a dynamic memory array.

10 cl, 35 dwg

Description

CROSS REFERENCE TO RELATED APPLICATION

[0001] This disclosure claims the benefit of Chinese Patent Application No. 202110746050.4, entitled “SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF,” filed with the National Intellectual Property Administration of China on July 1, 2021, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

[0002] The present disclosure relates, without limitation, to a semiconductor structure and a method for manufacturing the same.

BACKGROUND OF THE ART

[0003] With the increasing degree of integration of dynamic memory, it is also necessary to consider improving the electrical characteristics of small-sized functional devices when studying the arrangement of transistors and how to reduce the size of individual functional devices in the structure of the dynamic memory array.

[0004] When gate-all-around (GAA) transistors are used as dynamic memory input transistors, the area occupied by the gate transistors can be as large as 4F2 (F: smallest pattern size available under given process conditions ). In principle, this arrangement can improve density and efficiency, but the bit lines buried at the bottom of the transistors can cause high resistance at some sizes since their main component is silicon.

DISCLOSURE OF THE INVENTION

[0005] The following is an overview of the subject matter described in detail in the present disclosure, and this overview is not intended to limit the scope of the claims.

[0006] In one embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes: base; bit lines disposed on the substrate, wherein the bit line material includes a metal-semiconductor chemical compound; semiconductor channels disposed on the surfaces of the bit lines along a direction from the substrate to the bit line, the semiconductor channel including a first doped region, a channel region, and a second doped region arranged in series, the first doped region being in contact with the bit line; a first dielectric layer covering the side wall surfaces of the first doped regions, wherein a first interval is provided between portions of the first dielectric layer covering the side walls of adjacent first doped regions on the same bit line; an insulating layer covering the surfaces of the side walls of the channel regions; layer lines covering the surface of the side walls of the insulating layer away from the channel regions, and a second spacing provided between adjacent word lines; a second dielectric layer covering the side wall surfaces of the second doped regions, and a third spacing provided between portions of the second dielectric layer located on the side walls of adjacent second doped regions; and a third dielectric layer located at the first intervals, the second intervals and the third intervals.

[0007] In some embodiments of the present invention, the semiconductor structure further includes: a metal contact layer located on the upper surfaces of the second doped regions remote from the substrate, and a metal-semiconductor compound and a metal contact layer including the same metal element.

[0008] In some embodiments of the present invention, the orthogonal projection of the metal contact layer portion onto the substrate covers the orthogonal projection of the second alloyed region onto the substrate.

[0009] In some embodiments of the present invention, the semiconductor structure also includes: a transition layer located between the second doped regions and a metal contact layer, wherein the metal contact layer spans the transition layer, the transition layer and the second doped region are doped with the same doping ions type, wherein the doping concentration for the doping ion in the transition layer is greater than the doping concentration for the doping ion in the second doped region, and the doping ion is one of an N-type ion or a P-type ion.

[0010] In some embodiments of the present disclosure, the substrate, the bit line, and the semiconductor channel include the same semiconductor element.

[0011] In some embodiments of the present invention, the first doped region, the channel region, and the second doped region are doped with the same type of dopant ions, wherein the doping concentration for the dopant ion in the first doped region is the same as the doping concentration for the dopant ion in the channel region and the doping concentration for the doping ion in the second doped regions, and the doping ion is one of an N-type ion or a P-type ion.

[0012] In some embodiments of the present invention, the orthogonal projection of the channel region onto the substrate is less than the orthogonal projection of the second doped region onto the substrate, and less than the orthogonal projection of the first doped region onto the substrate.

[0013] In some embodiments of the present invention, the insulating layer and the second dielectric layer are the same film structure.

[0014] In some embodiments of the present invention, the orthogonal projection of the periphery of the insulating layer onto the substrate is less than the orthogonal projection of the periphery of the second dielectric layer onto the substrate.

[0015] In some embodiments of the present invention, the first dielectric layer includes a fourth dielectric layer and a fifth dielectric layer; wherein the fourth dielectric layer is located in the intervals between adjacent bit lines and in the intervals between adjacent first doped regions on adjacent bit lines; and the fifth dielectric layer is located on the side walls of the adjacent first doped regions on the same bit line and the side wall of the fourth dielectric layer.

[0016] In some embodiments of the present invention, a portion of the third dielectric layer located in the second intervals includes cavities.

[0017] Accordingly, in one embodiment of the present invention there is also provided a method for manufacturing a semiconductor structure, including: providing a substrate; forming parent bit lines on the substrate and forming semiconductor channels on surfaces of the parent bit lines remote from the substrate along a direction from the substrate to the parent bit line, the semiconductor channel including a first doped region, a channel region and a second doped region arranged in series; forming a first dielectric layer covering the side surfaces of the first doped regions, wherein a first interval is provided between portions of the first dielectric layer covering the side walls of adjacent first doped regions on the same original bit line; forming an insulating layer covering the surfaces of the side walls of the channel regions; forming layer lines covering the surface of the side walls of the insulating layer away from the channel regions, with a second spacing being provided between adjacent layer lines; forming a second dielectric layer covering the side wall surfaces of the second doped regions, wherein a third interval is provided between portions of the second dielectric layer located on the side walls of adjacent second doped regions; wherein the first interval, the second interval and the third interval are connected and open a portion of the original bit line; and metallizing an open portion of the original bit line to form a bit line, wherein the bit line material includes a chemical compound of a metal with a semiconductor.

[0018] In some embodiments of the present invention, after forming the layer lines and before forming the second dielectric layer, the fabrication method further includes: forming a parent transition layer on the top surfaces of the second doped regions away from the substrate through an epitaxial growth process, wherein the initial transition layer and the second doped region is doped with dopant ions of the same type, wherein the doping concentration for the dopant ion in the original transition layer is greater than the doping concentration for the dopant ion in the second doped region, wherein the dopant ion is one of an N-type ion or a P ion -type, and the orthogonal projection of the portion of the initial transition layer onto the base is greater than the orthogonal projection of the second doped region onto the base.

[0019] In some embodiments of the present invention, when metalizing the parent bit lines, the manufacturing method further includes: metalizing the parent transition layer.

[0020] In some embodiments of the present invention, forming the first dielectric layer includes:

[0021] forming the original first dielectric layer such that the original first dielectric layer surrounds the side walls of the semiconductor channels, and a fourth spacing is provided between portions of the original first dielectric layer located on the side walls of adjacent semiconductor channels on the same original bit line;

[0022] forming a first separation layer, wherein the first separation layer fills the fourth intervals, and the material of the first separation layer is different from the material of the original first dielectric layer;

[0023] etching a portion of the original first dielectric layer to expose the side walls of the second doped regions;

[0024] forming a second separating layer, wherein the second separating layer surrounds the side walls of the second alloyed regions and is located on the side wall of the first separating layer, wherein a portion of the second separating layer is located on the side walls of the second alloyed regions, and a portion of the second separating layer is located on the side the wall of the first separating layer, together forming through holes, and a portion of the original first dielectric layer is open in the lower parts of the through holes; wherein the material of the second separating layer differs from the material of the original first dielectric layer; And

[0025] removing a portion of the original first dielectric layer exposed by the through holes and located on the side walls of the channel regions, and using the remaining portion of the original first dielectric layer as the first dielectric layer.

[0026] In some embodiments of the present invention, forming the insulating layer includes:

[0027] thermally oxidizing the side walls of the open channel regions to form an insulating layer such that the insulating layer covers the side wall surfaces of the remaining portions of the channel regions and fifth spaces are provided between the insulating layer and the first separating layer.

[0028] In some embodiments of the present invention, generating layer lines includes:

[0029] forming the layer baselines such that the layer baselines fill the fifth spaces and through holes, and the layer baselines are also located between the insulating layer portions covering the side walls of the channel regions on adjacent bit baselines; And

[0030] removing portions of the original layer lines located in the through holes, while the remaining portions of the original layer lines are used as layer lines.

[0031] In some embodiments of the present invention, forming the first dielectric layer includes:

[0032] forming the original first dielectric layer such that the original first dielectric layer surrounds the side walls of the semiconductor channels, and a fourth spacing is provided between portions of the original first dielectric layer located on the side walls of adjacent semiconductor channels on the same original bit line;

[0033] forming a first separation layer, wherein the first separation layer fills the fourth intervals, and the material of the first separation layer is different from the material of the original first dielectric layer;

[0034] etching a portion of the original first dielectric layer to expose the side walls of the second doped regions and the side walls of the channel regions, wherein the remaining portion of the original first dielectric layer is used as the first dielectric layer.

[0035] In some embodiments of the present invention, forming the insulating layer and forming the second dielectric layer includes:

[0036] forming a protective layer covering the side walls of the second alloyed regions and the side walls of the channel regions, wherein a sixth interval is provided between the protective layer and the first separating layer, wherein a portion of the protective layer on the side walls of the channel regions is an insulating layer, and a portion of the protective layer, covering the side walls of the second doped regions is the second dielectric layer.

[0037] In some embodiments of the present invention, generating layer lines includes:

[0038] forming the layer baselines such that the layer baselines fill the sixth intervals, and the layer baselines are also located between the protective layer portions covering the side wall portions of the semiconductor channels on adjacent bit baselines; And

[0039] removing portions of the original layer lines, wherein the remaining portions of the original layer lines are used as layer lines, with only the layer lines surrounding only the side wall of the insulating layer located on the side walls of the channel regions.

[0040] Other aspects of the present disclosure will become apparent upon reading and understanding of the drawings and the following embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings included in and forming a part of this specification illustrate embodiments of the present disclosure and are used in conjunction with the present specification to explain the principles of embodiments of the present disclosure. In these drawings, like reference numerals are used to represent like elements. The drawings in the following description refer only to a portion of the embodiments of the present disclosure and not to all of them. Those skilled in the art can create other drawings based on these drawings without creative effort.

[0042] One or more embodiments are illustrated in the accompanying drawings, and these exemplary descriptions do not constitute limitations on the embodiments. Components having the same reference numerals in the drawings are designated as like components, and the drawings are not limited to scale unless otherwise indicated.

[0043] In FIG. 1-35 are schematic drawings of a semiconductor structure corresponding to steps of a method for manufacturing a semiconductor structure according to one embodiment of the present disclosure.

IMPLEMENTATION OF THE INVENTION

[0044] As mentioned in the Background Art section, there is currently a need to improve the electrical performance of small-sized functional devices in a semiconductor structure while increasing the degree of integration of the semiconductor structure.

[0045] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing it. The semiconductor structure on the base is provided with vertical circular gate (GAA) transistors, and the bit lines are arranged between the base and the GAA transistors, thereby forming a three-dimensional (3D) layer-stacked semiconductor structure, which increases the degree of integration of the semiconductor structure. In addition, since the bit line material includes a chemical compound of a metal with a semiconductor, the resistance of the bit lines is reduced to obtain improved electrical characteristics of the semiconductor structure.

[0046] Embodiments of the present disclosure are described in detail below with reference to the drawings. Those skilled in the art will appreciate that embodiments of the present invention have provided numerous technical details to make the present invention more understandable. However, even without these technical details, as well as various changes and modifications made based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0047] In one embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure proposed in this embodiment of the present disclosure is described in detail below with reference to the drawings. In FIG. 1 to 5 are schematic views showing block diagrams corresponding to a semiconductor structure according to this embodiment of the present disclosure. In FIG. 1 is a schematic view showing a block diagram corresponding to a semiconductor structure according to this embodiment of the present invention; In FIG. 2 is a schematic sectional view representing the structure shown in FIG. 1 taken along the first section direction AA1; In FIG. 3 is another schematic sectional view showing the structure shown in FIG. 1 taken along the first section direction AA1; In FIG. 4 is a schematic sectional view showing the structure shown in FIG. 1 taken along the second section direction BB1; and FIG. 5 is another schematic view showing a block diagram corresponding to a semiconductor structure according to this embodiment of the present invention.

[0048] With reference to FIG. 1-5, the semiconductor structure includes: a base 11; bit lines 104 arranged on base 11, wherein the material of bit line 104 includes a metal-semiconductor chemical compound; semiconductor channels 105 located on the surfaces of the bit lines 104, wherein the semiconductor channel 105 includes a first doped region I, a channel region II, and a second doped region III arranged sequentially along the Z direction from the substrate 11 to the bit line 104, wherein the first doped region I is in contact with the 104 bit line; a first dielectric layer 113 covering side wall surfaces of the first doped regions I, wherein a first interval is provided between portions of the first dielectric layer 113 covering the side walls of adjacent first doped regions I on the same bit line 104; an insulating layer 106 covering the surfaces of the side walls of the channel regions II; layer lines 107 covering the surface of the side walls of the insulating layer 106 away from the channel regions II, with a second interval provided between adjacent layer lines 107; a second dielectric layer 123 covering the side wall surfaces of the second doped regions II, wherein a third interval is provided between portions of the second dielectric layer 123 located on the side walls of adjacent second doped regions II; and a third dielectric layer 133 located in the first intervals, second intervals and third intervals.

[0049] The semiconductor structure is provided with vertical circular gate (GAA) transistors, and bit lines 104 are located between the base 11 and the GAA transistors, thereby forming a three-dimensional (3D) layered semiconductor structure, which increases the degree of integration of the semiconductor structure.

[0050] Below with reference to FIG. 1-5 this semiconductor is described in more detail.

[0051] In this embodiment, the base material 11 may be a single element semiconductor material or a crystalline inorganic mixed semiconductor material. The single element semiconductor material may be silicon or germanium, and the crystalline inorganic mixed semiconductor material may be silicon carbide, silicon germanium material, gallium arsenide, or indium gallium material. In addition, the base 11 is doped with ions of the first type.

[0052] In some embodiments of the present invention, the substrate 11, bit lines 104, and semiconductor channels 105 include the same semiconductor element such that the semiconductor channels 105 and bit lines 104 can be formed using the same film structure. The film structure is composed of a semiconductor element such that the semiconductor channels 105 and bit lines 104 are combined with each other, which prevents defects in the interface state between the semiconductor channel 105 and the bit line 104 and improves the performance of the semiconductor structure.

[0053] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, or indium. In the example, both bit lines 104 and semiconductor channels 105 include silicon. In other examples, both the bit lines and the semiconductor channels may include germanium. Alternatively, both bit lines and semiconductor channels include silicon and germanium. Alternatively, both bit lines and semiconductor channels include silicon and carbon. Alternatively, both the bit lines and the semiconductor channels include arsenic and gallium. Alternatively, both the bit lines and the semiconductor channels include gallium and indium.

[0054] The bit line material 104 includes a metal-semiconductor chemical compound 114. The metal-semiconductor chemical compound 114 has a lower resistivity compared to the non-metallized semiconductor material. Thus, compared to semiconductor channel 105, bit line 104 has a lower resistivity. This reduces the resistance of the bit line 104 and the contact resistance between the bit line 104 and the first doped region I, and thus further improves the electrical performance of the semiconductor structure. In addition, the resistivity of the 104 bit line is also smaller than the resistivity of the 11 base.

[0055] In some examples, the region of bit line 104 immediately below the first doped region I is made of a semiconductor material, and the region of bit line 104 not covered by the first doped region I is made of a metal-semiconductor compound. As the size of the device continues to decrease and the manufacturing process parameters are adjustable, the portion of the 104 bit line region directly below the first doped region I is made of a semiconductor material, and the remaining portion of the 104 bit line region directly below the first doped region I can also be made of a metal compound with a semiconductor. The "remaining area" as used herein is located on the periphery of the "area portion".

[0056] In the example with reference to FIG. 2, a plurality of metal-semiconductor chemical compounds 114 in the same bit line 104 are spaced apart from each other. In another example, with reference to FIG. 3, a plurality of metal-semiconductor chemical compounds 114 in the same bit line 104 are connected to each other. In FIG. 3 shows that only the edges of adjacent metal-semiconductor chemical compounds 114 directly contact each other for bonding. In practice, the contact area between adjacent metal-semiconductor chemical compounds 114 may be larger, and the contact area between adjacent metal-semiconductor chemical compounds 114 is not limited in this case.

[0057] In other examples, an entire line of bits may be made from only a metal-semiconductor chemical compound.

[0058] In the case where the semiconductor element is silicon as an example, the metal-semiconductor chemical compound 114 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide .

[0059] In this embodiment, a plurality of bit lines 104 may be formed based on 11, separated from each other, and each of the bit lines 104 may be in contact with at least one first doped region I. In FIG. 1-4 show four separate bit lines 104, each of the bit lines 104 contacting four first I doped regions. The number of bit lines 104 and the number of first I doped regions contacting each of the bit lines 104 can be reasonably set in accordance with actual electrical requirements.

[0060] The bit line 104 is doped with the second type of ions, and the base 11 is doped with the first type of ions. The second type ion is different from the first type ion, with the first type ion and the second type ion being one of an N-type ion or a P-type ion. Thus, the bit line 104 and the base 11 form a PN junction, which helps prevent leakage from the bit line 104, which further improves the electrical performance of the semiconductor structure. In yet other embodiments, the base 11 may not be doped with a first type of ion.

[0061] The N-type ion is at least one of an arsenic ion, a phosphorus ion or an antimony ion, and the P-type ion is at least one of a boron ion, an indium ion or a gallium ion.

[0062] In some embodiments of the present invention, the first doped region I, channel region II, and second doped region III of the semiconductor channel 105 are doped with the same type of ion, i.e. ion of the second type. The concentration of the dopant ion in the first doped region I is equal to the concentration of the dopant ion in the channel region II and the second doped region III.

[0063] Thus, the device formed by the semiconductor channel 105 is a junctionless transistor. In other layers, the types of doping ions in the first doped region I, channel region II and second doped region III are the same, for example, an N-type ion, and the dopant ions in the first doped region I, channel region II and the second doped region III may be the same . However, the term “junctionless” in this document refers to the absence of a PN junction, i.e. there is no PN junction in the transistor formed by the semiconductor channel 105, and the doping concentrations of the doping ions in the first doped region I, the channel region II and the second doped region III are the same. Such advantages include: on the one hand, there is no need to perform additional alloying in the first alloyed region I and the second alloyed region III, which eliminates the problem that the alloying process in the first alloyed region I and the second alloyed region III is difficult to control , especially as the transistor size further decreases, if the first doped region I and the second doped region III are further doped, it is more difficult to control the doping concentration; on the other hand, since the device is a junctionless transistor, it avoids the use of ultra-high gradient source/drain doping process to create ultra-high gradient PN junction in the nanoscale range, so problems such as threshold voltage drift and increased leakage current can be avoided, caused by sudden changes in doping concentration, and the short channel effect can be easily suppressed, so that the device can operate in the range of several nanometers, and this design further improves the degree of integration and electrical performance of the semiconductor structure. The expression “additional doping” herein refers to doping performed to ensure that the types of doping ions in the first doped region I and the second doped region III are different from the types of doping ions in the channel region II.

[0064] In some examples, the doping concentration for the second type of ion in the semiconductor channel 105 is from 1×10 ¹⁹ atoms/cm ³ to 1×10 ²⁰ atoms/cm ³ . Along the Z direction from the base 11 to the bit line 104, the height of the semiconductor channel 105 is from 100 nm to 150 nm, and the height of the first doped region I, the channel region II and the second doped region III is from 30 nm to 50 nm.

[0065] In this embodiment, the orthogonal projection of channel region II onto the substrate 11 is less than the orthogonal projection of the second doped region III onto the substrate 11, and is smaller than the orthogonal projection of the first doped region I onto the substrate 11. Thus, channel region II may be formed with a smaller cross-sectional area perpendicular to the Z direction from the bit line 104 to the semiconductor channel 105. As a result, the subsequently formed line of layers can better control the channel region II, thereby contributing to the on-off or turn-off control of the circular gate transistor (GAA). In still other embodiments, the orthogonal projections of the first doped region, the channel region, and the second doped region onto the substrate may be equal. Alternatively, the orthogonal projections of the channel region and the second doped region onto the substrate are smaller than the orthogonal projection of the first doped region onto the substrate.

[0066] In some examples, the width W and length L of channel region II in a section perpendicular to the Z direction do not exceed 10 nm, and this ensures that the line of layers that is subsequently formed will drive channel region II well.

[0067] The first dielectric layer 113 may include a fourth dielectric layer 143 and a fifth dielectric layer 153. The fourth dielectric layer 143 is located in the spaces between adjacent bit lines 104 and in the spaces between adjacent first I doped regions on adjacent bit lines 104. A fifth dielectric layer 153 is located on the side walls of adjacent first doped regions I on the same bit line 104 and on the side wall of a fourth dielectric layer 143. The first dielectric layer 113 is configured to achieve electrical isolation between adjacent semiconductor channels 105 and adjacent bit lines 104.

[0068] In some examples, the material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 are the same, and both the material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 may be silicon oxide. In still other embodiments, the material of the fourth dielectric layer and the material of the fifth dielectric layer may also be different if the materials of the fourth dielectric layer and the fifth dielectric layer are materials with good insulating effect.

[0069] In this embodiment, the orthogonal projection of the periphery of the insulating layer 106 onto the substrate 11 is less than the orthogonal projection of the periphery of the second dielectric layer 123 onto the substrate 11, i.e. with reference to FIG. 2 and 4, compared with the outer wall of the second dielectric layer 123, distant from the semiconductor channel 105, while the outer wall of the insulating layer 106, remote from the semiconductor channel 105, is closer to the semiconductor channel 105. In addition, compared with the outer wall of the first dielectric layer 113, remote from the semiconductor channel 105, the outer wall of the insulating layer 106, remote from the semiconductor channel 105, is also closer to the semiconductor channel 105. The material of the insulating layer 106 is silicon oxide.

[0070] In yet other embodiments, the insulating layer and the second dielectric layer may be the same film structure, i.e. the insulating layer and the second dielectric layer can be formed in the same process step. The insulating layer material and the second dielectric layer material include at least one of silicon oxide or silicon nitride.

[0071] The first interval, the second interval and the third interval are connected to each other.

[0072] In some examples with reference to FIGS. 2-4, the orthogonal projection of the first interval on the base 11 coincides with the orthogonal projection of the second interval on the base 11. The third dielectric layer 133 fills the first intervals, the second intervals and the third intervals, with the upper surface of the third dielectric layer 133, remote from the basis 11, located above than the surface of the second alloyed region III, distant from the base 11.

[0073] In some examples with reference to FIGS. 5, in a portion of the third dielectric layer 133 located at the second intervals, cavities 109 are provided. In other layers, in addition to the third dielectric layer 133, a cavity 109 is also provided between adjacent layer lines 107 to reduce the capacitance formed between adjacent layer lines 107, thus , improving the electrical characteristics of the semiconductor structure. In other examples, cavities may be provided not only in a portion of the third dielectric layer located in the second intervals, but also may be provided in a portion of the third dielectric layer located in the first intervals or in a portion of the third dielectric layer located in the third intervals.

[0074] The semiconductor structure may also include: a metal contact layer 108 located on the upper surfaces of the second doped regions III remote from the substrate 11, wherein the metal contact layer 108 contains the same metal element as the metal-semiconductor compound 114. The metal element includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.

[0075] Due to the metal element in the metal contact layer 108, when the bottom electrode of the capacitive structure is subsequently formed on the metal contact layer 108, the metal contact layer 108 forms an ohmic contact with the bottom electrode. In this way, the bottom electrode is prevented from directly contacting the semiconductor material to form contact with the Schottky barrier. The ohmic contact design reduces the contact resistance between the second doping region III and the bottom electrode, reduces the power consumption of the semiconductor structure, and suppresses the resistive-capacitance (RC) delay effect, thereby improving the electrical performance of the semiconductor structure. In addition, from the point of view of the manufacturing process, since the metal contact layer 108 and the metal-semiconductor chemical compound 114 contain the same metal element, it is conducive to the formation of the metal contact layer 108 and the formation of the metal-semiconductor chemical compounds 114 in the bit lines 104 in one stage of the process.

[0076] In some embodiments of the present invention, the orthogonal projection of a portion of the metal contact layer 108 onto the substrate 11 covers the orthogonal projection of the second alloyed region III onto the substrate 11. Thus, the contact area between the metal contact layer 108 and the bottom electrode is increased, resulting in a contact resistance between the metal contact layer 108 and the bottom electrode is reduced, and thus the electrical performance of the semiconductor structure is improved.

[0077] The semiconductor structure may also include: a transition layer 118 located between the second doped regions III and a metal contact layer 108 at portions of the top surfaces of the second doped regions III. The metal contact layer 108 covers the remaining surface portion of the transition layer 118. The transition layer 118 and the second doped region III are doped with the same type of ions, and the doping concentration for the doping ion in the transition layer 118 is greater than that in the second doped region III. Thus, the resistance of the transition layer 118 is less than the resistance of the second doped region III, which further reduces the electrical transmission resistance between the second doped region III and the bottom electrode.

[0078] In still other embodiments, the semiconductor structure may not include a transition layer, and the top surfaces of the second doped regions are provided only with a metal contact layer.

[0079] The semiconductor structure may also include capacitive structures (not shown in the drawings), the capacitive structures being disposed on a surface formed by the metal contact layer 108 and the third dielectric layer 133 together.

[0080] Thus, vertical circular gate transistors (GAAs) are provided on the base 11, and bit lines 104 are arranged between the base 11 and the GAA transistors, thereby forming a three-dimensional (3D) layer-stacked semiconductor structure, which increases the degree of integration of the semiconductor structure. The bit line 104 material includes a metal-semiconductor chemical compound 114 that reduces the resistance of the bit line 104 and the contact resistance between the bit line 104 and the first doped region I, further improving the electrical performance of the semiconductor structure. The device formed by the semiconductor channel 105 is a junctionless transistor that avoids the use of an ultra-high gradient drain-source doping process. Therefore, it is possible to prevent problems such as threshold voltage drift and increase in leakage current caused by sudden changes in doping concentration, and to easily suppress the short channel effect. This design further enhances the degree of integration and electrical performance of the semiconductor structure.

[0081] Accordingly, in another embodiment of the present disclosure, a method for manufacturing a semiconductor structure that can be used to manufacture the above-mentioned semiconductor structure is also provided.

[0082] In FIG. 1-35 are schematic cross-sectional views corresponding to steps of a method for manufacturing a semiconductor structure proposed in yet another embodiment. The method for manufacturing a semiconductor structure proposed in this embodiment will be described in detail below with reference to the drawings, and parts similar to or corresponding to those mentioned in the above embodiment will not be described again here.

[0083] With reference to FIG. 6-9 provide a substrate 11, wherein bit baselines 124 are formed on the core 11, and semiconductor channels 105 are formed on the surfaces of the bit baselines 124 remote from the substrate 11. The semiconductor channel 105 includes a first doped region I, a channel region II and a second doped region III arranged in sequence along the direction from the base 11 to the bit reference line 124.

[0084] Providing the base 11 and generating the base bit lines 124 and semiconductor channels 105 from the base 11 includes:

[0085] With reference to FIG. 6 provide a substrate 110. The type of material of the substrate 110 may be a single element semiconductor material or a crystalline inorganic mixed semiconductor material. The single element semiconductor material may be silicon or germanium, and the crystalline inorganic mixed semiconductor material may be silicon carbide, silicon germanium material, gallium arsenide, or indium gallium material.

[0086] The substrate 110 includes: a base 11, wherein the base 11 is doped with a first type of ions; and a source semiconductor layer 10 provided on the base 11.

[0087] The original semiconductor layer 10 is doped and annealed. The parent semiconductor layer 10 is doped with a second type of ion so as to subject the parent semiconductor layer 10 to subsequent etching to form parent bit lines 124 and semiconductor channels 105. The second type ion is different from the first type ion, with the first type ion and the second type ion respectively are one of an N-type ion or a P-type ion.

[0088] Doping treatment can be accomplished by high temperature diffusion or ion implantation. When the original semiconductor layer 10 is doped by ion implantation, the annealing temperature during annealing treatment is from 800°C to 1000°C.

[0089] In this embodiment, the doping concentration for the second type ion in the original semiconductor layer 10 is from 1×10 ¹⁹ atoms/cm ³ to 1×10 ²⁰ atoms/cm ³ , and along the direction from the original semiconductor layer 10 to the substrate 11 the depth doping for the second type ion in the original semiconductor layer 10 is from 150 nm to 250 nm. In addition, the first type ions are P-type ions, and the second type ions are N-type ions. In yet other embodiments, the first type ion may be an N-type ion, and the second type ion may be a P-type ion.

[0090] The buffer layer 120 and the barrier layer 130 are sequentially deposited layer by layer on the side of the parent semiconductor layer 10 away from the substrate 11. In some examples, the buffer layer 120 and the barrier layer 130 may be formed through a deposition process. The material of the buffer layer 120 is silicon oxide, and the material of the barrier layer 130 is made of silicon nitride.

[0091] In some embodiments of the present disclosure, silicon nitride may be deposited using a chemical vapor deposition process to form a barrier layer 130. The silicon nitride film layer oxidizes very slowly, allowing the substrate 100 located beneath the silicon nitride film layer to be protected. and preventing oxidation of the substrate 100.

[0092] In some examples, substrate 110 is a silicon substrate. Due to the large mismatch between the lattice constant and thermal expansion coefficient of silicon nitride and the lattice constant and thermal expansion coefficient of the silicon substrate, if silicon nitride is directly formed on the silicon substrate, the defect density at the interface between silicon nitride and silicon is large, so that a trap for silicon nitride is easily formed. carriers or recombination center, affecting the mobility of silicon carriers and thus the performance and life of the semiconductor structure. In addition, the stress of the silicon nitride film is large, and it can easily crack when directly deposited on a silicon substrate. Thus, silicon oxide is deposited as a buffer layer 120 before deposition of silicon nitride onto the silicon substrate, thereby improving the performance and life of the semiconductor structure.

[0093] With continued reference to FIG. 6, a first mask layer 102 is formed on the barrier layer 130, wherein the first mask layer 102 includes a plurality of first slots b separated from each other. The length of the first b slot along the longitudinal direction X of the first b slots corresponds to the length of the bit line that will be generated subsequently.

[0094] With reference to FIG. 7, the barrier layer 130, the buffer layer 120 and the original semiconductor layer 10 are etched using the first mask layer 102 as a mask, and a plurality of first slots a are formed and the first mask layer 102 is removed.

[0095] In this embodiment, the depth of the first groove a along the Z direction perpendicular to the surface of the base 11 is from 250 nm to 300 nm. Since the depth of the first groove a is greater than the doping depth of the second type of ions in the original semiconductor layer 10, it helps to allow the original semiconductor layer 10 doped with the second type of ions to be etched so as to facilitate the subsequent formation of semiconductor channels and bit lines with a high concentration of ion doping second type.

[0096] With reference to FIG. 8, a fourth dielectric layer 143 is formed in the first slots a.

[0097] In this embodiment, the fourth dielectric layer 143 may be formed as follows: A deposition process is carried out to form a fourth dielectric film covering the upper surface of the barrier layer 130 and filling the first slots. The fourth dielectric film is chemically and mechanically aligned until the top surface of the barrier layer 130 is exposed, and the remaining portion of the fourth dielectric film is used as the fourth dielectric layer 143. The material of the fourth dielectric film includes silicon oxide.

[0098] In some embodiments of the present invention, a second mask layer 112 is formed on the top surface formed by the fourth dielectric layer 143 and the remaining portion of the substrate 110 such that the second mask layer 112 includes a plurality of second slots c separated from each other. The length of the second slot c along the longitudinal direction Y of the second slot c corresponds to the length of the layer line to be formed subsequently.

[0099] In this embodiment, with reference to FIG. 6 and 8, the longitudinal direction X of the first slot b is perpendicular to the longitudinal direction Y of the second slot c. Thus, the final formed semiconductor channels 105 correspond to the 4F2 arrangement, which further enhances the degree of integration of the semiconductor structure. In yet other embodiments, the longitudinal direction of the first slot intersects the longitudinal direction of the second slot, and the internal angle between them may not be 90°.

[00100] In some embodiments of the present invention, the ratio of the width of the first slot b along the Y direction to the width of the second slot c along the X direction is 2 to 1 to allow through holes to subsequently be formed exposing the first dielectric layer surrounding the side walls of the channel areas II, which facilitates the subsequent formation of the first spaces for the production of layer lines. In some examples, the width of the first slot b along the Y direction is equal to the width of the second slot c along the X direction, and the distance between adjacent first slots b is equal to the distance between adjacent second slots c. On the one hand, a plurality of semiconductor channels formed subsequently are arranged regularly, which further improves the degree of integration of the semiconductor structure; on the other hand, the first mask layer 102 and the second mask layer 112 can be formed using the same mask, which helps reduce the manufacturing cost of the semiconductor structure.

[00101] In this embodiment, both of the first mask layer 102 and the second mask layer 112 may be formed using self-aligned quadruple patterning technology (SAQP) or self-aligned technology. double patterning technology (SADP).

[00102] With reference to FIG. 9, the original semiconductor layer 10 (shown in FIG. 6) and the fourth dielectric layer 143 are etched using the second mask layer 112 as a mask and form a plurality of second slots d, original bit lines 124, and semiconductor channels 105. The depth of the second slot d along the Z direction perpendicular to the surface of the base 11 is less than the depth of the first groove a. Thus, when the bit lines 124 are formed, a plurality of semiconductor channels 105 separated from each other are formed on the side of the bit line 124 away from the substrate 11, with the bit line 124 being in contact with the first doped regions I of the semiconductor channels 105. The second one is removed. mask layer 112.

[00103] In some examples, the depth of the second slot d is from 100 nm to 150 nm. Since the doping depth of the second type ions in the original semiconductor layer 10 is from 150 nm to 250 nm, most or all of the original semiconductor layer 10 doped with the second type ions is converted into semiconductor channels 105 after two etchings.

[00104] In addition, the material of the substrate 110 is silicon, and the material of the fourth dielectric layer 143 is silicon oxide. When etching the original semiconductor layer 10 and the fourth dielectric layer 143 using the second masking layer 112 as a mask, the etching rate for silicon oxide is faster than for silicon. Therefore, the sidewall portion of the 124-bit original line is open.

[00105] To achieve electrical isolation between adjacent parent bit lines 124 and adjacent semiconductor channels 105, after etching the parent semiconductor layer 10 and the fourth dielectric layer 143 using the second masking layer 112 as a mask, the remaining portion of the fourth dielectric layer 143 is located in the intervals between the adjacent parent lines 124 bits and in the intervals between adjacent semiconductor channels 105.

[00106] The types of doping ions in the first doped region I, channel region II and second doped region III are the same, for example, the doping ion is an N-type ion, and the doping concentrations of the doping ion in the first doped region I, channel region II and second doped region III are the same. In other layers, the device formed by the semiconductor channel 105 is a junctionless transistor. The dopant ion in the first doped region I, the channel region II and the second doped region III may be the same. Thus, there is no need for additional doping of the first doped region I and the second doped region III, and as a result, the problem that the doping process in the first doped region I and the second doped region III is difficult to control is avoided. The doping concentration becomes particularly difficult to control as the transistor size is further reduced by further doping the first doped region I and the second doped region III. In addition, since the device is a junctionless transistor, it does not require the use of an ultra-high gradient source-drain doping process to create an ultra-high gradient PN junction in the nanoscale range. Therefore, it is possible to eliminate problems such as threshold voltage drift and increased leakage current caused by sudden changes in doping concentration, and to easily suppress the short-channel effect so that the device is still capable of operating in the sub-nanometer range. This design further enhances the degree of integration and electrical performance of the semiconductor structure. The expression “additional doping” herein refers to doping performed to ensure that the types of doping ions in the first doped region I and the second doped region III are different from the types of doping ions in the channel region II.

[00107] In some embodiments of the present invention, the semiconductor channels 105 form circular gate transistors (GAAs) perpendicular to the top surfaces of the bit source lines 124 away from the substrate 11, thereby forming a three-dimensional (3D) layered semiconductor structure. The circular gate transistors are designed to be small in size without negatively affecting the electrical performance of the circular gate transistors, which increases the degree of integration of the semiconductor structure.

[00108] In this embodiment, the first mask layer 102 and the second mask layer 112 are used to simultaneously generate bit source lines 124 and semiconductor channels 105 through two etching processes. On the one hand, it is conducive to adjusting the size of the semiconductor channel 105 by adjusting the sizes of the first slot b and the second slot c, and forming the semiconductor channels 105 with high-precision dimensions; on the other hand, the 124 bit original lines and the semiconductor channels 105 are formed by etching the original semiconductor layer 10. In other words, the 124 bit original lines and the semiconductor channels 105 are formed using the same film structure, so that the 124 bit original lines and the semiconductor channels 105 combined. This prevents interface defects between the original bit lines 124 and the semiconductor channels 105 and improves the performance of the semiconductor structure. In addition, after etching the original semiconductor layer 10 using the first mask layer 102 as a mask in the first slots, a fourth dielectric layer 143 is also formed. This prepares the subsequent formation of a gap between the side wall of the channel region II and the first separation layer and facilitates the subsequent formation of the first gap to prepare the layer line.

[00109] In FIG. 10-35, a first dielectric layer 113 is shown covering the side wall surfaces of the first doped regions I, and a first spacing is provided between portions of the first dielectric layer 113 covering the side walls of adjacent first doped regions I on the same bit reference line 124. An insulating layer 106 is formed covering the surfaces of the side walls of the channel regions II. Layer lines 107 are formed covering the side wall surface of the insulating layer 106 away from the channel regions II, and a second spacing is provided between adjacent layer lines 107. A second dielectric layer 123 is formed covering the surfaces of the side walls of the second doped regions III, and a third spacing is provided between portions of the second dielectric layer 123 on the side walls of adjacent second doped regions III. The first interval, the second interval and the third interval are connected and partially open the original 124 bit line. Metallization of open source lines (124) bits is performed to form lines (104) bits. The bit line material 104 includes a metal-semiconductor chemical compound 114.

[00110] In FIG. 12 is a schematic cross-sectional view of the structure shown in FIG. 11 taken along the first section direction AA1, and in FIG. 13 is a schematic sectional view of the structure shown in FIG. 11 taken along the second section direction BB1. Below, in accordance with the requirements of the description, one or both of a schematic sectional view along the first sectional direction AA1 and a schematic sectional view along the second sectional direction BB1 will be discussed. When referring to only one drawing, that drawing is a schematic sectional view along the first section direction AA1. When referring to the two drawings simultaneously, the first drawing is a schematic sectional view along the first sectional direction AA1, and the second drawing is a schematic sectional view along the second sectional direction BB1.

[00111] In some examples, with reference to FIG. 10-27, the formation of the first dielectric layer 113, the insulating layer 106, the layer lines 107 and the second dielectric layer 123 includes:

[00112] With reference to FIG. 10-11, form the original first dielectric layer 113a. The original first dielectric layer 113a surrounds the side walls of the semiconductor channels 105. A fourth spacing e is provided between portions of the original first dielectric layer 113a located on the side walls of adjacent semiconductor channels 105 on the same original bit line 124.

[00113] With reference to FIG. 10, form a fifth dielectric film 103. The fifth dielectric film 103 conformally covers the side walls and bottoms of the second slots d (with reference to FIG. 9), and is also located on the upper surfaces of the barrier layer 130 and the fourth dielectric layer 143.

[00114] With reference to FIG. 10 and 11, the fifth dielectric film 103 is subjected to a maskless dry etching process until the barrier layer 130 is exposed. During the same etching time, different areas of the fifth dielectric film 103 are etched to the same thickness and form the fifth dielectric layer 153.

[00115] With reference to FIG. 11-13, a fourth dielectric layer 143 is located on the side walls of the second slots d (shown in FIG. 9), and a fourth dielectric layer 143 is located in the spaces between adjacent semiconductor channels 105. The fourth dielectric layer 143 and the fifth dielectric layer 153 together form the original first dielectric layer 113a, and a fourth interval e is provided between portions of the fifth dielectric layer 153 located on the side wall of the second slots d.

[00116] The material of the fourth dielectric layer 143 is the same as the material of the fifth dielectric layer 153, which is convenient for jointly removing a portion of the fourth dielectric layer 143 and a portion of the fifth dielectric layer 153 corresponding to the side walls of the channel regions II by an etching process to form thus the cavities between the side wall of the channel region II and the first separating layer to be formed subsequently, which facilitates the subsequent formation of spaces for the preparation of layer lines. The material of the fourth dielectric layer 143 and the material of the fifth dielectric layer 153 are silicon oxide.

[00117] In still other embodiments, the material of the fourth dielectric layer and the material of the fifth dielectric layer may also be different, provided that the material of the fourth dielectric layer and the material of the fifth dielectric layer are materials with good insulating properties, and thus part of the fourth dielectric layer and part of the fifth dielectric layer corresponding to the side walls of the channel regions can be removed in stages.

[00118] With reference to FIG. 14, form the first separation layer 163. The first separation layer 163 fills the fourth intervals e, and the material of the first separation layer 163 and the material of the original first dielectric layer 113a are different.

[00119] The first release layer 163 may be formed as follows: A first release film is formed through a deposition process covering the top surface of the barrier layer 130 and filling the fourth spaces e. The first release film, barrier layer 130, buffer layer 120, and original first dielectric layer 113a are chemically and mechanically aligned until the top surfaces of the second doped regions III are exposed. The remainder of the first release film is used as the first release layer 163. The material of the first release film includes silicon nitride.

[00120] With reference to FIG. 15, the original first dielectric layer 113a is partially etched away to expose the side walls of the second doped regions III.

[00121] With reference to FIG. 16-19, where in FIG. 17 is a top view of FIG. 16, in FIG. 18 is a schematic sectional view along the third section direction CC1, and FIG. 19 is a schematic sectional view along the second section direction BB1.

[00122] A second separating layer 173 is formed. The second separating layer 173 surrounds the side walls of the second alloy regions III and is located on the side wall of the first separating layer 163. A portion of the second separating layer 173 located on the side walls of the second alloy regions III and a portion of the second separating layer 173 located on the side wall of the first separation layer 163 define through holes f. The original first dielectric layer 113a is exposed at the lower portions of the through holes f. The material of the second separation layer 173 and the material of the original first dielectric layer 113a are different.

[00123] In some embodiments of the present invention, with reference to FIG. 18 and 19, the second separating layer 173 covers the top surface of the fifth dielectric layer 153 and the top surface portion of the fourth dielectric layer 143 surrounding the side walls of the second doped regions III. The through holes f expose a portion of the upper surface of the fourth dielectric layer 143.

[00124] In this embodiment, the second release layer 173 may be formed as follows: In the deposition process, a second release film is formed to conformally cover the surface formed by the semiconductor channels 105, the original first dielectric layer 113a, and the first release layer 163. The second release film is subjected to the process maskless dry etching until the top surfaces of the second doped regions are exposed III. During the same etching time, different areas of the second release film are etched to the same thickness and a second release layer 173 is formed exposing the first release layer 163. The material of the second release layer 173 includes silicon nitride.

[00125] Moreover, in the first mask layer 102 and the second mask layer 112 mentioned above, the ratio of the width of the first slot b along the Y direction to the width of the second slot c along the X direction is 2 to 1. When forming the second separation layer 173, this helps ensure that the second separating layer 173 fills the gap between adjacent semiconductor channels 105 on the same 124 bit reference line, but does not fill the gap between adjacent semiconductor channels 105 on adjacent 124 bit reference lines, thereby allowing through-holes f to be formed exposing the portion the top surface of the fourth dielectric layer 143, which facilitates subsequent removal of a portion of the original first dielectric layer 113a using the through holes f.

[00126] With reference to FIG. 20-22, a portion of the original first dielectric layer 113a located on the side walls of the channel regions II exposed through the through holes f is removed, and the remaining portion of the original first dielectric layer 113a is used as the first dielectric layer 113a.

[00127] Since the through holes f expose a portion of the upper surface of the first dielectric layer 113, and the material of the first dielectric layer 113 is different from the material of the second dielectric layer 123 and the material of the third dielectric layer 133, an etching solution can be introduced into the through holes f to remove the first dielectric portion layer 113 located on the side walls of the channel regions II, through a wet etching process, and maintaining a portion of the first dielectric layer 113 located on the side walls of the first doped regions I.

[00128] In addition, the first spacer layer 163 and the second spacer layer 173 together form a support frame. The support frame is in contact with the second doped regions III and partially buried in the first dielectric layer 113. In the wet etching process, on the one hand, the support frame has the function of supporting and fixing the semiconductor channels 105, and when the etching solution flows, a compressive force is generated, acting on the semiconductor channels 105, which helps prevent pressure on the semiconductor channels 105 that would cause them to tilt or shift, thereby improving the stability of the semiconductor structure; on the other hand, the support frame covers the side walls of the second alloyed regions III, which helps prevent the etching solution from damaging the second alloyed regions III.

[00129] After removing a portion of the original first dielectric layer 113a located on the side walls of the channel regions II, second spaces g are formed between the channel regions II and the first spacer layer 163, wherein the through hole f and the second space g jointly form a cavity structure h.

[00130] With reference to FIG. 23 and 24, the side walls of the open channel regions II are thermally oxidized to form an insulating layer 106. The insulating layer 106 covers the side wall surfaces of the remaining portions of the channel regions II, and fifth intervals i are provided between the insulating layer 106 and the first separation layer 163.

[00131] In some embodiments of the present invention, with reference to FIG. 24, fifth slots i are also located between portions of the insulating layer 106 on the side walls of adjacent semiconductor channels 105 on adjacent bit reference lines 124.

[00132] During the thermal oxidation treatment, since the top surfaces of the second doped regions III are also exposed, the portions of the second doped regions III close to the top surfaces and portions of the channel regions II are converted into the insulating layer 106. Thus, the orthogonal projection of the channel region II onto base 11 is smaller than the orthogonal projection of the second doped region III onto the base 11 and smaller than the orthogonal projection of the first doped region I onto the base 11. Thus, the channel regions II can be formed with a smaller cross-sectional area taken in a direction perpendicular to the Z direction from the reference line 124 bits per 105 semiconductor channel, without the need for an etching process. In this way, the subsequently formed layer lines can better control the II channel regions, thereby contributing to the on/off control of circular gate transistors (GAAs). The material of the insulating layer 106 is silicon oxide. In still other embodiments, the insulating layer covering the side wall surfaces of the channel regions may also be formed through a deposition process.

[00133] In this embodiment, a portion of the insulating layer 106 on the top surfaces of the remaining portions of the second alloyed regions III is removed in a subsequent process. In still other embodiments, the portion of the insulating layer on the top surfaces of the remaining portions of the second alloyed regions may be removed after thermal oxidation treatment, leaving only the portion of the insulating layer covering the side wall surfaces of the remaining portions of the channel regions.

[00134] With continued reference to FIG. 23 and 24, the orthogonal projection of the periphery of the insulating layer 106 onto the substrate 11 is less than the orthogonal projection of the periphery of the second separation layer 173 onto the substrate 11. In other layers, compared with the outer wall of the second separation layer 173 away from the semiconductor channels 105, the outer wall of the insulating layer 106, away from the semiconductor channels 105, is closer to the semiconductor channels 105. Thus, fifth intervals i may be formed between the insulating layer 106 and the first separation layer 163, so that layer lines to be formed subsequently may surround a portion of the insulating layer 106, located on the side walls of channel areas II. In addition, compared with the outer wall of the first dielectric layer 113 (shown in FIG. 20) away from the semiconductor channels 105, the outer wall of the insulating layer 106 away from the semiconductor channels 105 may also be closer to the semiconductor channels 105.

[00135] With reference to FIG. 25-27, form the original lines of the layers. The layer baseline fills the fifth space i and the through hole f, with the layer baselines also located between portions of the insulating layer 106 on the side walls of the channel areas II on adjacent bit baselines 124. The portion of the original layer line located in the through hole f is removed, and the remaining portion of the original layer line is used as the layer line 107. The layer precursors may be formed through a deposition process, and the layer precursor material includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[00136] The original layer line fills the cavity structure h (shown in FIG. 20) in a self-leveling manner. After removing the portion of the original layer line located in the through hole f, the layer line 107 with a precise size and self-aligning can be formed. Thus, there is no need to specify the size of the layer line 107 by an etching process, which simplifies the production of the layer lines 107. In addition, it is possible to obtain small-sized layer lines 107 by adjusting the size of the fifth interval i.

[00137] With reference to FIG. 28, after completion of the formation of the layer lines 107, a third spacer layer 183 is formed. The third spacer layer 183 fills the through holes f (shown in FIG. 26).

[00138] In this embodiment, the third separating layer 183 can be formed as follows: A third separating film is formed by a deposition process covering the upper surface of a portion of the insulating layer 106 located on the upper surfaces of the second alloyed regions III and filling the through holes f. The third release layer is chemically and mechanically leveled until the top surface of a portion of the insulating layer 106 is exposed, and the remaining portion of the third release film is used as the third release layer 183. The material of the third release film is the same as the material of the first release layer. and a second separating layer, and includes silicon nitride. In still other embodiments, the third release film may also be chemically and mechanically aligned until the top surfaces of the second doped regions are exposed. With other layers, a portion of the insulating layer located on the upper surfaces of the second alloyed regions is simultaneously removed, and the remaining portion of the third release film is used as a third release layer.

[00139] With continued reference to FIG. 28, a portion of the insulating layer 106 located on the upper surfaces of the second alloyed regions III is removed. On the top surfaces of the second doped regions III, a parent transition layer 128 is formed through an epitaxial growth process. The orthogonal projection of a portion of the parent transition layer 128 onto the substrate 11 covers the orthogonal projection of the second doped region III onto the substrate 11.

[00140] In addition, during the epitaxial growth process, the original transition layer 128 is further doped with the same type of dopant ion as in the second doped regions III. The doping concentration for the doping ion in the initial transition layer 128 is greater than the concentration for the doping ion in the second doped regions III, so the resistance of the initial transition layer 128 is less than the resistance of the second doped regions III.

[00141] On the one hand, the use of the epitaxial growth process is conducive to improving the continuity between the second doped regions III and the original transition layer 128, reducing contact defects caused by different lattice characteristics or lattice dislocations, reducing contact resistance caused by contact defects, and improving the transport ability and carrier movement speeds, thereby improving the conductivity between the second doped regions III and the original transition layer 128, to reduce the heat generated during operation of the semiconductor structure; on the other hand, the use of the epitaxial growth process helps to increase the orthogonal projection of the initial transition layer 128 onto the substrate 11, which makes the area of the orthogonal projection of the portion of the initial transition layer 128 onto the substrate 11 greater than the area of the orthogonal projection of the second doped region III onto the substrate 11. Initial transition layer may subsequently be used as a mask to prevent etching of the second dielectric layer surrounding the side walls of the second doped regions III to expose the second doped regions III to provide the desired protective effect of the subsequently formed second dielectric layer on the second doped regions III.

[00142] With reference to FIG. 28 and 29, the first separation layer 163, the second separation layer 173 and the third separation layer 183 are etched using the original transition layer 128 as a mask to expose the side walls of the second doped regions III. The top surface of the remaining portion of the first separation layer 163 is located no higher than the top surface of the layer line 107. The orthogonal projection of a portion of the original transition layer 128 onto the substrate 11 covers the orthogonal projection of the second doped region III onto the substrate 11 to prevent damage to the semiconductor channels 105 during etching.

[00143] With reference to FIG. 30, a second dielectric film is formed to conformally cover the surface of the original transition layer 128, the side walls of the second doped regions III, the top surfaces of the layer lines 107, and the top surface of the first spacer layer 163 (shown in FIG. 29). The second dielectric layer is chemically and mechanically leveled until the surface of the original transition layer 128 is exposed, and the remaining portion of the second dielectric layer 123 is etched using the original transition layer 128 as a mask. The area of the orthogonal projection of the portion of the original transition layer 128 onto the substrate 11 is greater than the area of the orthogonal projection of the second doped region III onto the substrate 11. Therefore, when the portion of the second dielectric film located on the surface of the original transition layer 128, the upper surface of the first separating layer 163, and portions of the upper surfaces are removed layers lines 107, the portion of the second dielectric film directly opposite the orthogonal projection of the original transition layer 128 onto the base 11 is protected from etching. Thus, a second dielectric layer 123 is formed surrounding the side walls of the second doped regions III, the second dielectric layer 123 having a desired protective effect on the second doped regions III. The second dielectric film may be formed through a deposition process.

[00144] In some embodiments of the present invention, with reference to FIG. 30, the remainder of the first separation layer 163 is removed to expose the top surfaces of the original bit lines 124.

[00145] In yet other embodiments, the first spacer layer, the second spacer layer, and the third spacer layer are etched using the original transition layer as a mask to expose the original bit lines and sidewalls of the second doped regions. The side walls of the exposed second doped regions are thermally oxidized to form a second dielectric layer.

[00146] With reference to FIG. 1-4, the open source bit lines 124 and the source transition layer 128 are metalized to form the 104 bit lines. The bit line material 104 includes a metal-semiconductor chemical compound 114.

[00147] A metal layer is formed on the surface of the source transition layer 128 and the top surfaces of the source bit lines 124 to provide a metal element for the sequentially generated bit lines. A metal layer is also located on exposed surface areas of the second dielectric layer 123, layer lines 107, and first dielectric layer 113. The metal layer material includes at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[00148] Annealing is performed to convert a portion of the thickness of the original transition layer 128 into a metal contact layer 108 and a portion of the thickness of the original bit line 124 (shown in FIG. 30) into a 104 bit line.

[00149] After the 104 bit lines are formed, the remaining portion of the metal layer is removed.

[00150] In some embodiments, during annealing, the metal layer reacts with the parent transition layer 128 and the parent bit lines 124. A portion of the thickness of the original transition layer 128 is converted into a metal contact layer 108, and a portion of the thickness of the original bit line 124 is converted into a bit line 104. In the example with reference to FIG. 2, a plurality of metal-semiconductor chemical compounds 114 in the same bit line 104 are spaced apart. In another example, with reference to FIG. 3, a plurality of metal-semiconductor chemical compounds 114 in the same bit line 104 are connected to each other.

[00151] In yet other embodiments, the total thickness of the original transition layer may be converted to a metal contact layer, and the total thickness of the original bit line may be converted to a bit line.

[00152] In still other embodiments, when the original transition layer is not formed on the top surfaces of the second doped regions, the portion of the insulating layer on the top surfaces of the second doped regions is not first removed, and subsequently only the original bit lines are metalized. After the bit lines are formed, a portion of the insulating layer on the top surfaces of the second alloyed regions is removed. With reference to FIG. 30 and FIG. 1-4, form a third dielectric layer 133. The third dielectric layer 133 fills the first spacing between adjacent portions of the first dielectric layer 113, the second spacing between adjacent layer lines 107, and the third spacing between adjacent portions of the second dielectric layer 123 to provide electrical isolation between adjacent semiconductor channels. 105 and adjacent lines 107 layers. In some examples, with reference to FIG. 5, when the third dielectric layer 133 is formed, a cavity may be formed in a portion of the third dielectric layer 133 in the second interval.

[00153] In other examples, with reference to FIG. 10-14 and 31-35, the first dielectric layer 113, the insulating layer 106, the layer lines 107 and the second dielectric layers 123 are formed as follows:

[00154] With reference to FIG. 10-14, form the original first dielectric layer 113a. The original first dielectric layer 113a surrounds the side walls of the semiconductor channels 105. A fourth spacing e is provided between portions of the original first dielectric layer 113a located on the side walls of adjacent semiconductor channels 105 on the same original bit line 124. A first separation layer 163 is formed. The first separation layer 163 fills the fourth intervals e, and the material of the first separation layer 163 is different from the material of the original first dielectric layer 113a.

[00155] The formation of the original first dielectric layer 113a and the first separation layer 163 is the same as in the above example and will not be repeated herein.

[00156] With reference to FIG. 31, the original first dielectric layer 113a (shown in FIG. 14) is partially etched to expose the side walls of the second doped regions III and channel regions II, and the remaining portion of the original first dielectric layer 113a is used as the first dielectric layer 113.

[00157] With reference to FIG. 32-33, form a protective layer 116 covering the side walls of the second alloyed regions III and the side walls of the channel regions II. Between the protective layer 116 and the first separation layer 163, sixth k intervals are provided. The portion of the protective layer 116 on the side walls of the channel regions II is an insulating layer 106, and the portion of the protective layer 116 covering the side walls of the second doped regions III is a second dielectric layer 123.

[00158] In some embodiments of the present invention, with reference to FIG. 33, a sixth slot k is also located between portions of the guard layer 116 on the side walls of adjacent semiconductor channels 105 on adjacent bit baselines 124.

[00159] In this embodiment, the material of the semiconductor channel 105 is silicon, and the protective layer 116 is formed as follows: The side walls of the channel regions II and the side walls and top surfaces of the open second doped regions III are thermally oxidized so that the protective layer 116 covers the surfaces of the side the walls of the remaining portions of the channel regions II, the remaining portions of the second doped regions III, and the upper surfaces of the remaining portions of the second doped regions III. In still other embodiments, a protective layer covering the side walls of the channel regions, as well as the side walls and top surfaces of the second alloyed regions, may also be formed through a deposition process.

[00160] By thermally oxidizing the side walls of channel regions II and the exposed second doped regions III, channel regions II and second doped regions III are partially converted into the protective layer 116. The orthogonal projections of the channel region II and the second doped region III onto the substrate 11 are less than the orthogonal projection the first doped region I onto the substrate 11. Thus, the channel regions II and the second doped regions III can be formed with a smaller cross-sectional area in a direction perpendicular to the Z direction from the original bit line 124 to the semiconductor channel 105, without the need for an etching process. In this way, the subsequently formed layer lines can better control the II channel regions, thereby contributing to the on/off control of circular gate transistors (GAAs).

[00161] In this embodiment, a portion of the protective layer 116 on the top surfaces of the remaining portions of the second alloyed regions III is removed in a subsequent process. In still other embodiments, the portion of the protective layer on the top surfaces of the remaining portions of the second alloyed regions may be removed after thermal oxidation, leaving only the portion of the protective layer covering the side wall surfaces of the remaining portions of the channel regions and the remaining portions of the second alloyed regions.

[00162] With reference to FIG. 34-35, form the original lines of the layers. Layer seed lines fill the sixth k intervals, with layer seed lines also located between portions of the protective layer 116 on the sidewall portions of semiconductor channels 105 on adjacent bit seed lines 124. The original layer line is partially removed, and the remaining portion of the original layer line is used as the layer line 107. The layer lines 107 surround only the side wall of the portion of the insulating layer 106 located on the side walls of the channel regions II. The layer precursors may be formed through a deposition process, and the layer precursor material includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[00163] The original layer lines fill the sixth k intervals with self-alignment, which contributes to the formation of precisely sized layer lines 107 with self-alignment.

[00164] After completing the formation of the lines 107 layers, a third separation layer is formed, a source transition layer is formed, the source transition layer and the source bit lines are metalized to form a metal contact layer and bit lines, and a third dielectric layer is formed, which are the same as those mentioned steps in the above examples, the descriptions of which will not be repeated here.

[00165] In some embodiments of the present invention, capacitive structures (not shown in the drawings) are formed on the surface formed by the metal contact layer 108 and the third dielectric layer 133. In yet other embodiments, the metal contact layer may not be formed. After removing the portion of the insulating layer located on the upper surfaces of the second doped regions, capacitive structures are formed directly on the surface formed by the second doped regions and the third dielectric layer.

[00166] Thus, the first dielectric layer 113 and the second dielectric layer 123 are formed, and the first dielectric layer 113 is etched using the second dielectric layer 123 as a mask to form cavity structures of a certain shape. Layer lines 107 are formed to precise dimensions in these self-aligning cavity structures through a deposition process. There is no need to specify the size of the layer line 107 through the etching process, and thus the formation of the layer lines 107 is simplified. In addition, it is possible to obtain a small-sized layer line 107 by adjusting the size of the cavity structure. In addition, by metallizing the original bit lines 124 and the initial transition layer 128, the resistance of the final formed bit lines 104 and the metal contact layer 108 is reduced. Thus, an ohmic contact is formed between the metal contact layer 108 and the capacitive structures, avoiding direct contact between the capacitive structures and semiconductor material with the formation of contact with the Schottky barrier. This design reduces the contact resistance between the second doped regions III and the capacitive structures and reduces power consumption during operation of the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.

[00167] In the description of this invention, references to terms such as “embodiment”, “exemplary embodiment”, “certain embodiments”, “schematic embodiment” and “example” mean that a particular feature, structure, material or feature described in combination with the embodiment(s) or example(s) are included in at least one embodiment(s) or example of the present invention.

[00168] In this specification, the schematic expression of the above terms does not necessarily refer to the same embodiment or example. Moreover, the particular feature, structure, material, or characteristic described may be suitably combined into any one or more embodiments or examples.

[00169] It should be noted that in the description of this disclosure, terms such as “center”, “top”, “bottom”, “left”, “right”, “vertical”, “horizontal”, “inner” and “outer” , indicate orientation or position relationships based on the drawings. These terms are intended merely for convenience in describing the present invention and to simplify the description, and are not intended to indicate or imply that said device or element must have a particular orientation and must be designed and operated in a particular orientation. Therefore, these terms should not be construed as limiting the present invention.

[00170] Terms such as “first” and “second” as used in the present disclosure may be used to describe various structures, but the structures are not limited to these terms. Instead, these terms are intended only to distinguish one element from another.

[00171] The same elements in one or more drawings are designated by like reference numerals. For clarity, various details in the drawings are not to scale. In addition, some well-known details may not be shown. For brevity, the structure obtained by performing several steps can be shown in a single drawing. To make the present disclosure clearer, many specific details of the present disclosure, such as structure, material, size, processing, and device technology, are described below. However, those skilled in the art will understand that the present disclosure may not be implemented in accordance with these specific details.

[00172] Finally, it should be noted that the above embodiments are intended merely to explain the technical solutions of the present invention and not to limit the present invention. Although the present invention has been described in detail with reference to the above embodiments, it will be appreciated by those skilled in the art that they may nevertheless modify the technical solutions described in the above embodiments or make equivalent substitutions for some or all of the technical features. specified therein, without deviating from the essence of the corresponding technical solutions from the scope of protection of technical solutions in the embodiments of the present invention.

INDUSTRIAL APPLICABILITY

[00173] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing it. The semiconductor structure is provided with vertical circular gate transistors (GAAs) arranged on the base, and the bit lines are arranged between the base and the circular gate transistors (GAAs), thereby forming a three-dimensional (3D) layer-stacked semiconductor structure, which increases the degree of integration of the semiconductor structure. In addition, since the bit line is made of a metal-semiconductor chemical compound, the resistance of the bit line is reduced to improve the electrical performance of the semiconductor structure.

Claims (11)

1. Semiconductor structure containing: a base; bit lines disposed on a substrate, wherein the bit line material comprises a metal-semiconductor chemical compound; semiconductor channels located on the surfaces of the bit lines along a direction from the substrate to the bit line, the semiconductor channel comprising a first doped region, a channel region and a second doped region arranged in series, the first doped region being in contact with the bit line; a first dielectric layer covering the side wall surfaces of the first doped regions, wherein a first interval is provided between portions of the first dielectric layer covering the side walls of adjacent first doped regions on the same bit line; an insulating layer covering the surfaces of the side walls of the channel regions; layer lines covering the side surface of the insulating layer away from the channel regions, with a second spacing provided between adjacent layer lines; a second dielectric layer covering the side wall surfaces of the second doped regions, wherein a third interval is provided between portions of the second dielectric layer located on the side walls of adjacent second doped regions; and a third dielectric layer located at the first intervals, the second intervals and the third intervals. 2. The semiconductor structure according to claim 1, also containing: a metal contact layer located on the upper surfaces of the second doped regions at a distance from the base, wherein the chemical compound of the metal with the semiconductor and the metal contact layer contain the same metal element, and the orthogonal projection a portion of the metal contact layer onto the substrate covers an orthogonal projection of the second doped region onto the substrate, wherein the semiconductor structure also includes: a transition layer located between the second doped regions and the metal contact layer, wherein the metal contact layer encloses the transition layer, the transition layer and the second doped region are doped doping ion of the same type, wherein the doping concentration for the doping ion in the transition layer is greater than the doping concentration for the doping ion in the second doped region, and the doping ion is one of an N-type ion or a P-type ion. 3. The semiconductor structure according to claim 1, wherein the first doped region, the channel region and the second doped region are doped with doping ions of the same type, and the doping concentration for the doping ion in the first doped region is the same as the doping concentration for a dopant ion in the channel region; and a doping concentration for the dopant ion in the second doped region, wherein the dopant ion is one of an N-type ion or a P-type ion. 4. The semiconductor structure according to claim 1, wherein the orthogonal projection of the channel region onto the substrate is less than the orthogonal projection of the second doped region onto the substrate, and less than the orthogonal projection of the first doped region onto the substrate. 5. The semiconductor structure according to claim 1, wherein the first dielectric layer contains a fourth dielectric layer and a fifth dielectric layer; wherein the fourth dielectric layer is located in the intervals between adjacent bit lines and in the intervals between adjacent first doped regions on adjacent bit lines; and the fifth dielectric layer is located on the side walls of the adjacent first doped regions on the same bit line and the side wall of the fourth dielectric layer. 6. The semiconductor structure according to claim 1, in which the section of the third dielectric layer located in the second intervals contains cavities. 7. A method for manufacturing a semiconductor structure, including: providing a base; forming parent bit lines on the substrate and forming semiconductor channels on surfaces of the parent bit lines remote from the substrate along a direction from the substrate to the parent bit line, the semiconductor channel comprising a first doped region, a channel region and a second doped region arranged in series; forming a first dielectric layer covering the side wall surfaces of the first doped regions, wherein a first interval is provided between portions of the first dielectric layer covering the side walls of adjacent first doped regions on the same original bit line; forming an insulating layer covering the surfaces of the side walls of the channel regions; forming layer lines covering the surface of the side walls of the insulating layer away from the channel regions, with a second spacing being provided between adjacent layer lines; forming a second dielectric layer covering the side wall surfaces of the second doped regions, wherein a third interval is provided between portions of the second dielectric layer located on the side walls of adjacent second doped regions; wherein the first interval, the second interval and the third interval are connected and open a portion of the original bit line; and metallizing an open portion of the original bit line to form a bit line, wherein the bit line material comprises a metal-semiconductor chemical compound. 8. The method for manufacturing a semiconductor structure according to claim 7, after forming the layer lines and before forming the second dielectric layer, also including: forming a parent transition layer on the top surfaces of second doped regions away from the substrate through an epitaxial growth process such that the parent transition layer and the second doped region are doped with the same type of doping ion, wherein the doping concentration for the dopant ion in the parent transition layer is greater, than the doping concentration for the doping ion in the second doped region, wherein the doping ion is one of an N-type ion or a P-type ion, and the orthogonal projection of the portion of the original transition layer onto the substrate is greater than the orthogonal projection of the second doped region onto the substrate, and at metallization of the original bit lines; the manufacturing method further includes: metallization of the initial transition layer. 9. The method of manufacturing a semiconductor structure according to claim 7, according to which the formation of the first dielectric layer includes: forming the original first dielectric layer in such a way that the original first dielectric layer surrounds the side walls of the semiconductor channels, and between the sections of the original first dielectric layer located on the side walls adjacent semiconductor channels on the same original bit line, a fourth slot is provided; forming a first separation layer, wherein the first separation layer fills the fourth intervals, and the material of the first separation layer is different from the material of the original first dielectric layer; etching a portion of the original first dielectric layer until the side walls of the second doped regions are exposed; forming a second separating layer, wherein the second separating layer surrounds the side walls of the second alloyed regions and is located on the side wall of the first separating layer, wherein a portion of the second separating layer is located on the side walls of the second alloyed regions, and a portion of the second separating layer is located on the side wall of the first separating layer layer, together forming through holes, and a portion of the original first dielectric layer is open in the lower parts of the through holes; wherein the material of the second separating layer differs from the material of the original first dielectric layer; and removing a portion of the original first dielectric layer exposed by the through holes and located on the side walls of the channel regions, and using the remaining portion of the original first dielectric layer as the first dielectric layer, wherein forming the insulating layer includes: thermally oxidizing the side walls of the open channel regions to form the insulating layer such that the insulating layer covers the surfaces of the side walls of the remaining sections of the channel regions, and fifth intervals are provided between the insulating layer and the first separating layer, wherein the formation of layer lines includes: forming the initial layer lines in such a way that the initial layer lines fill the fifth intervals and through holes and bit baselines are also located between portions of the insulating layer covering the side walls of the channel regions on adjacent bit baselines; and removing portions of the original layer lines located in the through holes, with the remaining portions of the original layer lines being used as layer lines. 10. The method of manufacturing a semiconductor structure according to claim 7, according to which the formation of the first dielectric layer includes: forming the original first dielectric layer in such a way that the original first dielectric layer surrounds the side walls of the semiconductor channels, and between the areas of the original first dielectric layer located on the side walls adjacent semiconductor channels on the same original bit line, a fourth slot is provided; forming a first separation layer, wherein the first separation layer fills the fourth intervals, and the material of the first separation layer is different from the material of the original first dielectric layer; and etching a portion of the original first dielectric layer to expose the side walls of the second doped regions and the side walls of the channel regions, wherein the remaining portion of the original first dielectric layer is used as the first dielectric layer, wherein forming the insulating layer and forming the second dielectric layer includes: forming a protective layer covering the side walls of the second alloyed regions and the side walls of the channel regions, wherein a sixth interval is provided between the protective layer and the first separating layer, wherein the portion of the protective layer on the side walls of the channel regions is an insulating layer, and the portion of the protective layer covering the side walls of the second alloyed regions , is a second dielectric layer, wherein forming the layer lines includes: forming the original layer lines such that the original layer lines fill the sixth intervals, and the original layer lines are also located between portions of the protective layer covering the side wall portions of the semiconductor channels on adjacent original bit lines; and removing portions of the original layer lines, wherein the remaining portions of the original layer lines are used as layer lines, the layer lines surrounding only a side wall of the insulating layer located on the side walls of the channel regions.