CN112397479A - Isolation capacitor and preparation method thereof - Google Patents
Isolation capacitor and preparation method thereof Download PDFInfo
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- CN112397479A CN112397479A CN202011339496.7A CN202011339496A CN112397479A CN 112397479 A CN112397479 A CN 112397479A CN 202011339496 A CN202011339496 A CN 202011339496A CN 112397479 A CN112397479 A CN 112397479A
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- 238000002955 isolation Methods 0.000 title claims abstract description 62
- 239000003990 capacitor Substances 0.000 title claims abstract description 51
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 9
- 230000002035 prolonged effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an isolation capacitor and a preparation method thereof, the isolation capacitor comprises a substrate, a first electrode plate and a second electrode plate which are positioned on the substrate, a first dielectric layer positioned between the first electrode plate and the substrate, and a second dielectric layer positioned between the second electrode plate and the first electrode plate, the second electrode plate is positioned above the first electrode plate, the second electrode plate comprises a second main body part and a second extension part which extends outwards from the second main body part, and the second extension part is bent outwards along the direction far away from the first electrode plate. The edge of the electrode plate of the isolation capacitor is provided with the bent extension part, so that the edge electric field concentration effect of the electrode is greatly reduced, and the service life of the isolation capacitor is prolonged; the preparation process of the isolation capacitor is completely compatible with the traditional CMOS process, only one low-cost photomask is added, and the design difficulty of the high-voltage isolation circuit is greatly reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor isolation chips, and particularly relates to an isolation capacitor and a preparation method thereof.
Background
Digital isolators are in wide-ranging use because in harsh motor application environments, the use is not only required to be able to withstand high voltage transients, preventing data from being distorted by interference, but also to eliminate the effect of high voltage on the service life of the isolator. Three isolation methods exist in the market: the high-voltage capacitor isolation has received wide attention due to advantages of low cost, low power consumption, high temperature resistance, long service life, no influence of an external magnetic field, easy integration into a traditional CMOS (complementary metal oxide semiconductor) process and the like, and more manufacturers and scientific research institutions are put into research and development of the high-voltage isolation capacitor.
The reliability of a digital isolator (mainly the reliability of a high-voltage isolation capacitor) in the prior art is a technical problem which puzzles manufacturers at home and abroad. The high voltage isolation capacitor is generally a plate capacitor, and as shown in fig. 1, includes a lower electrode plate 11 'and an upper electrode plate 12', with a thick dielectric layer therebetween, and the dielectric layer is usually made of silicon dioxide. In the middle position of the lower electrode plate 11 ' and the upper electrode plate 12 ', the electric field lines are parallel from top to bottom, but at the edge of the upper electrode plate 12 ' which is applied with high voltage, the electric field lines are the most dense at the edge of the electrode plates because the metal electrode plates are approximately at right angles, and the electric field concentration effect is obvious. Under the condition of high voltage and high field intensity for long-term work, the edge of the capacitor electrode plate is most easily punctured, so that the service life of the whole high-voltage isolation capacitor is shortened.
Therefore, in view of the above technical problems, it is desirable to provide an isolation capacitor and a method for manufacturing the same.
Disclosure of Invention
The invention aims to provide an isolation capacitor and a preparation method thereof, which are used for reducing the electric field concentration effect at the edge of a polar plate.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
the utility model provides an isolation capacitor, isolation capacitor includes the substrate, is located first electrode board and second electrode board on the substrate, is located first dielectric layer between first electrode board and the substrate, and is located second dielectric layer between second electrode board and the first electrode board, and second electrode board is located first electrode board top, second electrode board includes the second main part and from the outside second extension that extends of second main part, the outside crooked setting of direction along keeping away from first electrode board of second extension.
In one embodiment, the second main body portion and the first electrode plate are disposed opposite to each other in the vertical direction.
In one embodiment, the thickness of the second extending portion is equal to the thickness of the second main body portion.
In one embodiment, the substrate is a silicon substrate.
In one embodiment, the first dielectric layer and/or the second dielectric layer is a silicon dioxide dielectric layer.
The technical scheme provided by another embodiment of the invention is as follows:
a preparation method of an isolation capacitor comprises the following steps:
s1, providing a substrate, and sequentially forming a first dielectric layer, a first electrode plate and a second dielectric layer on the substrate;
s2, forming a light shield on the second dielectric layer to expose the second dielectric layer in the area right above the first electrode plate;
s3, forming grooves in the second dielectric layer by etching through an isotropic etching process, wherein the grooves comprise a first groove located in a region right above the first electrode plate and a second groove located at the side of the first groove, and the bottom of the second groove is bent outwards in a direction away from the first electrode plate;
s4, removing the photomask on the second medium layer;
and S5, forming a second electrode plate in the groove, wherein the second electrode plate comprises a second main body part positioned in the first groove and a second extension part positioned in the second groove.
In an embodiment, in the isotropic etching process of step S3, the lateral etching rate is equal to the longitudinal etching rate, and the depth of the first trench in the trenches is equal to the width of the second trench.
In an embodiment, in the step S5, the thickness of the second extending portion is equal to the thickness of the second main body portion.
In one embodiment, the substrate is a silicon substrate.
In one embodiment, the first dielectric layer and/or the second dielectric layer is a silicon dioxide dielectric layer.
Compared with the prior art, the invention has the following advantages:
the edge of the electrode plate of the isolation capacitor is provided with the bent extension part, so that the edge electric field concentration effect of the electrode is greatly reduced, and the service life of the isolation capacitor is prolonged;
the preparation process of the isolation capacitor is completely compatible with the traditional CMOS process, only one low-cost photomask is added, and the design difficulty of the high-voltage isolation circuit is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of electric field distribution of a high voltage isolation capacitor in the prior art;
FIG. 2 is a schematic structural diagram of an isolation capacitor according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of the electric field distribution of the isolation capacitor according to the first embodiment of the present invention;
FIGS. 4a to 4e are process flow diagrams of a method for fabricating an isolation capacitor according to a first embodiment of the present invention;
fig. 5a to 5e are process flow diagrams of a method for manufacturing an isolation device according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
The invention discloses an isolation capacitor, which comprises a substrate, a first electrode plate and a second electrode plate which are positioned on the substrate, a first dielectric layer positioned between the first electrode plate and the substrate, and a second dielectric layer positioned between the second electrode plate and the first electrode plate, wherein the second electrode plate is positioned above the first electrode plate, the second electrode plate comprises a second main body part and a second extension part which extends outwards from the second main body part, and the second extension part is bent outwards along the direction far away from the first electrode plate.
The invention also discloses a preparation method of the isolation capacitor, which comprises the following steps:
s1, providing a substrate, and sequentially forming a first dielectric layer, a first electrode plate and a second dielectric layer on the substrate;
s2, forming a light shield on the second dielectric layer to expose the second dielectric layer in the area right above the first electrode plate;
s3, forming a groove on the second dielectric layer through an isotropic etching process, wherein the groove comprises a first groove located in the area right above the first electrode plate and a second groove located at the side of the first groove, and the bottom of the second groove is bent outwards in the direction far away from the first electrode plate;
s4, removing the photomask on the second medium layer;
and S5, forming a second electrode plate in the groove, wherein the second electrode plate comprises a second main body part positioned in the first groove and a second extension part positioned in the second groove.
The isolation capacitor and the isolation device of the present invention are further described with reference to the following embodiments.
Referring to fig. 2, the isolation capacitor in the first embodiment of the present invention includes a substrate 10, a first electrode plate (lower electrode plate) 21 and a second electrode plate (lower electrode plate) 22 disposed on the substrate 10, a first dielectric layer 31 disposed between the first electrode plate 21 and the substrate 10, and a second dielectric layer 32 disposed between the second electrode plate 22 and the first electrode plate 21.
Referring to fig. 3, in the present embodiment, the second electrode plate 22 is located above the first electrode plate 21, the first electrode plate 21 is in a flat plate shape, the second electrode plate 22 includes a second main body portion 221 and a second extending portion 222 extending outward from the second main body portion, the second main body portion 221 is in a flat plate shape, the second extending portion 222 is in a curved shape, and the second extending portion 222 is disposed in an outward curved shape along a direction away from the first electrode plate 21.
Preferably, the second main body portion 221 and the first electrode plate 21 in this embodiment are disposed opposite to each other in an up-down direction, and the thickness of the second extension portion 222 is equal to that of the second main body portion 221.
In this embodiment, the substrate 10 is a silicon substrate, the first dielectric layer 31 and the second dielectric layer 32 are both silicon dioxide dielectric layers, the first electrode plate 21 and the second electrode plate 22 may be metal electrode plates with the same or different materials, and in other embodiments, the substrate material and the dielectric layer material may also be other materials, which are not described herein again.
Correspondingly, as shown in fig. 4a to 4e, the method for manufacturing the isolation capacitor in this embodiment specifically includes:
1. referring to fig. 4a, a substrate 10 is provided, and a first dielectric layer 31, a first electrode plate 21, and a second dielectric layer 32 are sequentially formed on the substrate 10, in this embodiment, the substrate is a silicon substrate, and the first dielectric layer and the second dielectric layer are both silicon dioxide dielectric layers.
2. Referring to fig. 4b, a mask 40 is formed on the second dielectric layer to expose the second dielectric layer 32 in the region directly above the first electrode plate 21.
3. Referring to fig. 4c, a trench 50 is etched on the second dielectric layer 32 by an isotropic etching process, the trench 50 includes a first trench 51 located in a region directly above the first electrode plate and a second trench 52 located beside the first trench, and a bottom of the second trench 52 is bent outward in a direction away from the first electrode plate.
Preferably, in the isotropic etching process of this embodiment, the lateral etching rate is equal to the longitudinal etching rate, and the depth of the first trench 51 in the trench formed by etching is equal to the width of the second trench 52.
4. Referring to fig. 4d, the mask 40 on the second dielectric layer 32 is removed.
5. Referring to fig. 4e, the second electrode plate 22 is formed in the trench 50, and the second electrode plate 22 includes a second main portion 221 located in the first trench 51 and a second extension portion 222 located in the second trench 52.
In this embodiment, since the depth of the first trench 51 is equal to the width of the second trench 52, the thickness of the second extension portion 222 is equal to the thickness of the second main body portion 221, and the width of the second extension portion 222 is equal to the depth of the first trench 51 in the formed electrode plate.
Referring to fig. 5a to 5e, the isolation device in the second embodiment of the present invention includes an isolation capacitor (right side of the dashed line) and an isolation circuit (left side of the dashed line), the structure of the isolation capacitor is completely the same as that of the isolation capacitor in the first embodiment, and the isolation circuit includes a substrate 10, a plurality of metal conductive layers 61 located on the substrate 10, a conductive pillar 62, and a dielectric layer (including a first dielectric layer 31 and a second dielectric layer 32).
The preparation method of the isolation device in the embodiment comprises the following steps:
1. referring to fig. 5a, a substrate 10 is provided, a first dielectric layer 31, a first electrode plate 21, and a second dielectric layer 32 are sequentially formed on the substrate 10, and meanwhile, a metal conductive layer 61 and a conductive pillar 62 are synchronously formed on the substrate 10.
2. Referring to fig. 5b, a mask 40 is formed on the second dielectric layer in the isolation capacitor region and the region above the isolation circuit to expose the second dielectric layer 32 in the region directly above the first electrode plate 21.
3. Referring to fig. 5c, a trench 50 is etched on the second dielectric layer 32 by an isotropic etching process, the trench 50 includes a first trench 51 located in a region directly above the first electrode plate and a second trench 52 located beside the first trench, and a bottom of the second trench 52 is bent outward in a direction away from the first electrode plate.
4. Referring to fig. 5d, the mask 40 on the second dielectric layer 32 is removed.
5. Referring to fig. 5e, the second electrode plate 22 is formed in the trench 50, and the second electrode plate 22 includes a second main portion 221 located in the first trench 51 and a second extension portion 222 located in the second trench 52. Meanwhile, a metal conductive layer 61 of the top layer is simultaneously formed on the top layer of the isolated circuit region.
Therefore, the preparation process of the isolation capacitor in the embodiment is completely compatible with the traditional CMOS process, only one low-cost photomask is added, and the design difficulty of the high-voltage isolation circuit is greatly reduced.
Compared with the electric field distribution diagram of the isolation capacitor in the prior art and the isolation capacitor in the first embodiment of the invention, the electric field distribution diagram of the isolation capacitor in the prior art shows that the edge electric field concentration effect is greatly reduced by adding the second extending part which is bent upwards at the edge of the second electrode plate, so that the edge electric field intensity is close to the electric field intensity in the middle of the electrode plate, and the reliability of the whole isolation capacitor is improved.
It should be understood that, in the present invention, an extending portion which is bent upwards is provided at the edge of the second electrode plate (upper electrode plate) so as to reduce the edge electric field concentration effect of the upper electrode plate, and the solution is also applicable to the first electrode plate (lower electrode plate), and in other embodiments, an extending portion which is bent downwards is provided at the edge of the first electrode plate so as to reduce the edge electric field concentration effect of the lower electrode plate.
According to the technical scheme, the invention has the following beneficial effects:
the edge of the electrode plate of the isolation capacitor is provided with the bent extension part, so that the edge electric field concentration effect of the electrode is greatly reduced, and the service life of the isolation capacitor is prolonged;
the preparation process of the isolation capacitor is completely compatible with the traditional CMOS process, only one low-cost photomask is added, and the design difficulty of the high-voltage isolation circuit is greatly reduced.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. The utility model provides an isolation capacitor, its characterized in that, isolation capacitor includes the substrate, is located first plate electrode and second plate electrode on the substrate, is located first dielectric layer between first plate electrode and the substrate, and is located the second dielectric layer between second plate electrode and the first plate electrode, and the second plate electrode is located first plate electrode top, the second plate electrode includes second main part and the outside second extension that extends from the second main part, the outside crooked setting of direction along keeping away from first plate electrode of second extension.
2. The isolation capacitor of claim 1, wherein the second body portion is disposed opposite the first electrode plate in a vertical direction.
3. An isolation capacitor as claimed in claim 1 or 2, wherein the thickness of the second extension portion is equal to the thickness of the second main body portion.
4. The isolation capacitor of claim 1 wherein the substrate is a silicon substrate.
5. The isolation capacitor of claim 1, wherein the first dielectric layer and/or the second dielectric layer is a silicon dioxide dielectric layer.
6. A preparation method of an isolation capacitor is characterized by comprising the following steps:
s1, providing a substrate, and sequentially forming a first dielectric layer, a first electrode plate and a second dielectric layer on the substrate;
s2, forming a light shield on the second dielectric layer to expose the second dielectric layer in the area right above the first electrode plate;
s3, forming grooves in the second dielectric layer by etching through an isotropic etching process, wherein the grooves comprise a first groove located in a region right above the first electrode plate and a second groove located at the side of the first groove, and the bottom of the second groove is bent outwards in a direction away from the first electrode plate;
s4, removing the photomask on the second medium layer;
and S5, forming a second electrode plate in the groove, wherein the second electrode plate comprises a second main body part positioned in the first groove and a second extension part positioned in the second groove.
7. The method as claimed in claim 6, wherein in the isotropic etching process of step S3, the lateral etching rate is equal to the longitudinal etching rate, and the depth of the first trench is equal to the width of the second trench.
8. The manufacturing method according to claim 7, wherein in the step S5, a thickness of the second extending portion is equal to a thickness of the second main body portion.
9. The production method according to claim 6, wherein the substrate is a silicon substrate.
10. The method according to claim 6, wherein the first dielectric layer and/or the second dielectric layer is a silicon dioxide dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011339496.7A CN112397479B (en) | 2020-11-25 | 2020-11-25 | Isolation capacitor and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011339496.7A CN112397479B (en) | 2020-11-25 | 2020-11-25 | Isolation capacitor and preparation method thereof |
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| CN112397479A true CN112397479A (en) | 2021-02-23 |
| CN112397479B CN112397479B (en) | 2022-07-22 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023241069A1 (en) * | 2022-06-17 | 2023-12-21 | 无锡华润上华科技有限公司 | Semiconductor device and preparation method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104515640A (en) * | 2013-10-08 | 2015-04-15 | 无锡华润上华半导体有限公司 | Capacitive MEMS (micro-electromechanical system) pressure sensor |
| CN109473486A (en) * | 2018-10-18 | 2019-03-15 | 上海华虹宏力半导体制造有限公司 | A kind of capacitor arrangement and preparation method thereof |
| CN111370473A (en) * | 2020-03-24 | 2020-07-03 | 成都森未科技有限公司 | Groove type device and preparation method thereof |
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2020
- 2020-11-25 CN CN202011339496.7A patent/CN112397479B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104515640A (en) * | 2013-10-08 | 2015-04-15 | 无锡华润上华半导体有限公司 | Capacitive MEMS (micro-electromechanical system) pressure sensor |
| CN109473486A (en) * | 2018-10-18 | 2019-03-15 | 上海华虹宏力半导体制造有限公司 | A kind of capacitor arrangement and preparation method thereof |
| CN111370473A (en) * | 2020-03-24 | 2020-07-03 | 成都森未科技有限公司 | Groove type device and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023241069A1 (en) * | 2022-06-17 | 2023-12-21 | 无锡华润上华科技有限公司 | Semiconductor device and preparation method therefor |
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