JP2009200335A - Substrate, substrate with epitaxial layer, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate, a substrate with epitaxial layer, and a semiconductor device, which is capable of attaining the improvement of characteristics. <P>SOLUTION: A semiconductor device 1 includes a substrate 2 as a hexagonal SiC substrate of which the off angle θ in the <1-100> direction of ä0001} plane exceeds 0°, and is 8° or less, a withstand voltage retention layer 22 and a p region 23 as an SiC epitaxially grown layer formed in the surface of the substrate 2, an oxide film 26 as an insulating layer formed in the surfaces of the withstand voltage retention layer 22 and the p region 23, and an n<SP>+</SP>region 24 as a conductive region formed in a position adjacent to the above region for supplying electrons which flow to an interface (MOS interface) between the region (upper layer of the p region 23) under the oxide film 26 and the oxide film 26. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a substrate, a substrate with an epitaxial layer, and a semiconductor device. More specifically, the present invention relates to a substrate containing SiC in which an insulating film is formed on the surface of the substrate or the substrate with an epitaxial layer, a substrate with an epitaxial layer, and a semiconductor device.

Conventionally, a SiC substrate and a semiconductor device using the SiC substrate are known (for example, Japanese Patent Publication No. 2003-502857: hereinafter referred to as Patent Document 1). In Patent Document 1, when an SiC epitaxial growth layer is formed on the main surface of a SiC substrate whose (0001) plane is inclined at an off angle of 6 ° or more and 10 ° or less in the <1-100> direction, SiC epitaxial growth having excellent characteristics is achieved. You are going to be able to get a layer.
Japanese translation of PCT publication No. 2003-502857

  However, the inventors described in the above cited reference 1 in a semiconductor device in which an insulating film is formed on the SiC epitaxial growth layer as described above and electrons are allowed to flow to the interface between the insulating film and the SiC epitaxial growth layer. Further, in the range of the off angle, the characteristics of the semiconductor device (for example, the value of mobility of electrons as carriers) are still insufficient, and further improvement is required.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a substrate, a substrate with an epitaxial layer, and a semiconductor device capable of improving characteristics.

  The substrate with an epitaxial layer according to the present invention includes a hexagonal SiC substrate having an off angle θ in the <1-100> direction of the {0001} plane of 0 ° to 8 ° and SiC formed on the surface of the SiC substrate. An epitaxial growth layer and an insulating film formed on the surface of the SiC epitaxial growth layer are provided. In this way, in the state where a plurality of fine steps having the (0001) plane as the upper surface of the terrace are formed on the surface of the SiC epitaxial growth layer, the angle between the extension direction of the steps and the off-angle direction is substantially vertical. In addition, the area of one terrace upper surface ((0001) plane) can be made relatively large by making the off angle θ relatively small. And, in the SiC epitaxial growth layer formed on the hexagonal SiC substrate, the oxidation rate of the (0001) plane is the slowest and stable as in the case of the SiC substrate. Therefore, when an insulating film is formed on the (0001) plane, In addition, it is easy to form an insulating film (for example, an oxide film), and the interface state density at the boundary portion (MOS interface) between the insulating film and the SiC epitaxial growth layer can be reduced. Therefore, when, for example, a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed using the above substrate with an epitaxial layer, the performance of the MOSFET is improved by utilizing a MOS interface having excellent quality (for example, excellent carrier mobility). be able to.

  The substrate with an epitaxial layer according to the present invention is formed on the surface of a hexagonal SiC substrate having a {0001} plane as a main surface, a SiC epitaxial growth layer formed on the main surface of the SiC substrate, and a SiC epitaxial growth layer. And an insulating film. In this case, a MOS interface having a large area and a low interface state density can be obtained by forming an insulating film on the SiC epitaxial growth layer having the slowest oxidation rate and the stable (0001) plane as a surface. For this reason, when, for example, a SiC MOSFET is formed using the substrate with an epitaxial layer, a MOSFET with excellent performance can be realized.

In the substrate with an epitaxial layer, the conductive impurity concentration in a region located below the insulating film in the SiC epitaxial growth layer may be 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. In this case, a substrate with an epitaxial layer suitable for manufacturing a semiconductor device (for example, MOSFET) can be obtained. Here, the reason why the conductive impurity concentration is set to 1 × 10 ¹³ / cm ³ or more is that the lower limit of the impurity concentration obtained by optimizing the epi growth conditions is the above value. The conductive impurity concentration is set to 1 × 10 ¹⁸ / cm ³ or less because the channel layer having a higher concentration than the impurity concentration of the epitaxial layer-attached substrate (epi substrate) can be formed by ion implantation. This is because the upper limit of the concentration. The conductive impurity concentration is preferably 1 × 10 ¹⁴ / cm ³ or more and 5 × 10 ¹⁷ / cm ³ or less, more preferably 1 × 10 ¹⁵ / cm ³ or more and 5 × 10 ¹⁶ / cm ³ or less.

  In the substrate with an epitaxial layer, the thickness of the SiC epitaxial growth layer may be not less than 0.5 μm and not more than 100 μm. In this case, a substrate with an epitaxial layer suitable for manufacturing a semiconductor device can be obtained. Here, the reason why the thickness of the SiC epitaxial growth layer is set to 0.5 μm or more is that the minimum thickness that is not affected by the substrate is the above value. The reason why the thickness of the SiC epitaxial growth layer is set to 100 μm or less is that the upper limit at which the surface after the epitaxial film formation can maintain a mirror surface is the above numerical value.

  A substrate according to the present invention includes a hexagonal SiC substrate having an off angle θ of 0 ° to 8 ° in the <1-100> direction of the {0001} plane, and an insulating film formed on the surface of the SiC substrate. Prepare. In this case, since the off-angle direction is <1-100>, the extension of the steps is performed in a state where a plurality of fine steps having the (0001) plane as the upper surface of the terrace are formed on the surface of the SiC substrate. The angle between the current direction and the off-angle direction can be made substantially vertical, and the area of one terrace upper surface ((0001) plane) can be made relatively large by making the off-angle θ relatively small. Further, since the oxidation rate of the (0001) plane is the slowest and stable in a hexagonal SiC substrate, when an insulating film is formed on the (0001) plane, it is easy to form an insulating film (for example, an oxide film). In addition, the density of interface trap states (interface state density) at the boundary between the insulating film and the SiC substrate can be reduced. Therefore, when, for example, a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed using the substrate, the performance of the MOSFET can be improved by utilizing a MOS interface of excellent quality (for example, excellent carrier mobility). .

  A substrate according to the present invention includes a hexagonal SiC substrate having a {0001} plane as a main surface and an insulating film formed on the main surface of the SiC substrate. In this case, by forming the insulating film on the stable (0001) surface having the slowest oxidation rate, an interface having a large area and a low interface state density (for example, a MOS interface) can be obtained. For this reason, when, for example, a SiC MOSFET is formed using the substrate, a MOSFET with excellent performance can be realized.

In the substrate, a conductive impurity concentration in a region located below the insulating film in the SiC substrate may be 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. In this case, a substrate suitable for manufacturing a semiconductor device (for example, MOSFET) can be obtained. Here, the reason why the conductive impurity concentration is set to 1 × 10 ¹³ / cm ³ or more is that the lower limit of the impurity concentration obtained by optimizing the epi growth conditions is the above value. The conductive impurity concentration is set to 1 × 10 ¹⁸ / cm ³ or less because of the upper limit of the impurity concentration that can form a channel layer having a higher concentration than the impurity concentration in the epitaxial substrate by ion implantation. .

  The semiconductor device according to the present invention includes a hexagonal SiC substrate having an off angle θ in the <1-100> direction of the {0001} plane of 0 ° to 8 °, and an SiC epitaxial growth layer formed on the surface of the SiC substrate. And an insulating film formed on the surface of the SiC epitaxial growth layer, and a conductive region formed at a position adjacent to the region for supplying electrons flowing to the interface between the region under the insulating film and the insulating film .

  In this way, in the state where a plurality of fine steps having the (0001) plane as the upper surface of the terrace are formed on the surface of the SiC substrate and the surface of the SiC epitaxial growth layer, the extending direction of the steps is the off-angle direction. The angle can be made substantially vertical, and the area of one terrace upper surface ((0001) plane) can be made relatively large by making the off angle θ relatively small. And by forming an insulating film on such a terrace upper surface, the interface state density in the boundary part (interface) of a SiC epitaxial growth layer and an insulating film can be reduced. Therefore, the mobility of electrons flowing from the conductive region to the interface can be improved, so that a semiconductor device having excellent characteristics can be realized.

  A semiconductor device according to the present invention includes a hexagonal SiC substrate having an off angle θ of 0 ° to 8 ° in the <1-100> direction of the {0001} plane, and an insulating film formed on the surface of the SiC substrate. In order to supply electrons flowing to the interface between the region under the insulating film and the insulating film, a conductive region formed at a position adjacent to the region is provided.

  In this way, in the state where a plurality of fine steps having the (0001) plane as the upper surface of the terrace are formed on the surface of the SiC substrate, the angle formed by the step extension direction and the off-angle direction is substantially vertical. In addition, the area of one terrace upper surface ((0001) plane) can be made relatively large by making the off angle θ relatively small. And by forming an insulating film on such a terrace upper surface, the interface state density in the boundary part (interface) between a SiC substrate and an insulating film can be reduced. Therefore, the mobility of electrons flowing from the conductive region to the interface can be improved, so that a semiconductor device having excellent characteristics can be realized.

  A semiconductor device according to the present invention includes a hexagonal SiC substrate having a {0001} plane as a main surface, a SiC epitaxial growth layer formed on the surface of the SiC substrate, and an insulating film formed on the surface of the SiC epitaxial growth layer. In order to supply electrons flowing to the interface between the region under the insulating film and the insulating film, a conductive region formed at a position adjacent to the region is provided.

  A semiconductor device according to the present invention includes a hexagonal SiC substrate having a {0001} plane as a main surface, an insulating film formed on the surface of the SiC substrate, a region under the insulating film, and the insulating film. In order to supply electrons flowing to the interface, a conductive region formed at a position adjacent to the region is provided.

  In this case, by forming the insulating film on the stable (0001) surface having the slowest oxidation rate, an interface having a large area and a low interface state density can be obtained. For this reason, a semiconductor device with excellent performance can be realized. The semiconductor device may be a MOSFET.

  As described above, when the substrate according to the present invention or the substrate with an epitaxial layer is used, an interface having a large area and a low interface state density (interface between the SiC substrate or SiC epitaxial growth layer and the insulating film) can be realized. The characteristics of a semiconductor device that allows carriers to flow through can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic sectional view showing a first embodiment of a semiconductor device according to the present invention. A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 1, a semiconductor device 1 according to the present invention is a vertical DiMOSFET (Double Implanted Metal-Oxide-Field-Effect Transistor), which includes a substrate 2, a buffer layer 21, a breakdown voltage holding layer 22, and a p region 23. , N ⁺ region 24, p ⁺ region 25, oxide film 26, source electrode 11 and upper source electrode 27, gate electrode 10, and drain electrode 12 formed on the back side of substrate 2. Specifically, the buffer layer 21 made of silicon carbide is formed on the surface of the substrate 2 made of silicon carbide (SiC) whose conductivity type is n. As the substrate 2, a 4H—SiC substrate which is a hexagonal SiC substrate is used. Buffer layer 21 is n-type in conductivity type and has a thickness of 0.5 μm, for example. In addition, the concentration of the n-type conductive impurity in the buffer layer 21 can be set to 5 × 10 ¹⁷ cm ⁻³ , for example.

A breakdown voltage holding layer 22 is formed on the buffer layer 21. The breakdown voltage holding layer 22 is made of silicon carbide of n-type conductivity, and has a thickness of 10 μm, for example. In addition, a value of 5 × 10 ¹⁵ cm ⁻³ can be used as the concentration of the n-type conductive impurity in the breakdown voltage holding layer 22 as the SiC epitaxial growth layer.

On the surface layer of the breakdown voltage holding layer 22, p regions 23 having a p-type conductivity are formed at intervals. Inside the p region 23, an n ⁺ region 24 is formed in the surface layer of the p region 23. A p ⁺ region 25 is formed at a position adjacent to the n ⁺ region 24. From the n ⁺ region 24 in one p region 23 to the p region 23, the breakdown voltage holding layer 22 exposed between the two p regions 23, the other p region 23, and the n ⁺ region 24 in the other p region 23 An oxide film 26 is formed as an insulating film so as to extend up to.

A gate electrode 10 is formed on the oxide film 26. Further, the source electrode 11 is formed on the n ⁺ region 24 and the p ⁺ region 25. An upper source electrode 27 is formed on the source electrode 11. In the substrate 2, the drain electrode 12 is formed on the back surface opposite to the surface on which the buffer layer 21 is formed.

The substrate 2 of the semiconductor device 1 shown in FIG. 1 is a hexagonal SiC substrate (specifically, a 4H—SiC substrate) having an off angle θ of 0 ° to 8 ° in the <1-100> direction of the (0001) plane. ). That is, the semiconductor device 1 includes a substrate 2 as a hexagonal SiC substrate having an off angle θ of 0 ° to 8 ° in the <1-100> direction of the {0001} plane, and SiC formed on the surface of the substrate 2. The breakdown voltage holding layer 22 and the p region 23 as an epitaxial growth layer, the oxide film 26 as an insulating film formed on the surface of the breakdown voltage holding layer 22 and the p region 23, and the region below the oxide film 26 (the upper layer of the p region 23) ) And an oxide film 26, an n ⁺ region 24 is provided as a conductive region formed at a position adjacent to the region. By setting the off-angle direction to the <1-100> direction in this way, at least in the interface region with the oxide film 26 in the surface of the breakdown voltage holding layer 22 which is an SiC epitaxial growth layer, it is shown in FIGS. Thus, a stepped terrace having the (0001) plane as the upper surface is formed on the surface of the p region 23. FIG. 2 is a schematic plan view showing a terrace formed on the surface of the breakdown voltage holding layer in the semiconductor device shown in FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG.

  2 and 3, boundary 13 extends in a direction substantially perpendicular to the <1-100> direction indicated by arrow 18 on the surface of breakdown voltage holding layer 22 of semiconductor device 1 shown in FIG. 1. In addition, a structure is formed in which the upper stage side 16 of the terrace and the lower stage side 17 of the terrace are arranged in a stepped manner with the boundary 13 in between. As shown in FIGS. 2 and 3, in the semiconductor device 1 according to the present invention, the off angle θ in the <1-100> direction of the (0001) plane of the substrate 2 is greater than 0 ° and equal to or less than 8 °. Thus, the terrace boundary 13 extends in a direction substantially perpendicular to the <1-100> direction indicated by the arrow 18 with good linearity. This is greatly different from an off-angle substrate in which the off-angle direction that has been often used conventionally is the <11-20> direction.

  Here, with reference to FIG. 4 and FIG. 5, the structure of the terrace in the case of using the conventional SiC substrate whose <11-20> direction is the off-angle direction will be briefly described. 4 is formed on the surface of the breakdown voltage holding layer when a semiconductor device having the same configuration as that of the semiconductor device shown in FIG. 1 is formed using a SiC substrate with the off-angle direction being the <11-20> direction. It is a plane schematic diagram which shows a terrace. FIG. 5 is a schematic cross-sectional view taken along line VV in FIG. 4 and 5 correspond to FIGS. 2 and 3, respectively.

  Referring to FIGS. 4 and 5, the semiconductor device using the SiC substrate with the <11-20> direction as the off-angle direction is formed on the surface of the breakdown voltage holding layer 22 in the same manner as the semiconductor device 1 shown in FIG. 1. A terrace structure as shown in FIGS. 4 and 5 is formed. However, as illustrated in FIGS. 4 and 5, the extending direction of the terrace boundary 13 intersects the <11-20> direction that is the off-angle direction indicated by the arrow 19. Therefore, the upper stage side 16 and the lower stage side 17 of the terrace have a configuration in which the boundary portion thereof meanders greatly, and the planar shape of the upper surface of one terrace is a polygonal shape in which the outer peripheral portion of the planar shape meanders. . On the other hand, in the semiconductor device according to the present invention shown in FIGS. 2 and 3, the planar shape of the upper surface of the upper stage side 16 and the lower stage side 17 of the terrace is substantially rectangular (rectangular). Alternatively, a region in which carriers move, such as a channel region of the semiconductor device, can be easily formed on the upper surface of the lower side 17. 4 and 5, the terrace boundary 13 is substantially straight (off angle) as shown in FIGS. 2 and 3, compared to the case where the boundary 13 meanders (has a zigzag boundary 13). Therefore, in the semiconductor device 1 shown in FIG. 1, the interface state density at the interface between the breakdown voltage holding layer 22 and the oxide film 26 can be further reduced. Is possible. As a result, in the semiconductor device 1 shown in FIG. 1, the mobility of carriers in the vicinity of the interface can be improved as compared with the structure shown in FIGS.

  FIG. 6 is a flowchart for explaining a method of manufacturing the semiconductor device shown in FIG. 7 to 10 are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG. A manufacturing method of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.

  First, as shown in FIG. 6, a substrate preparation step (S10) is performed. Here, a hexagonal SiC substrate (4H—SiC substrate) having an off angle θ in the <1-100> direction of the (0001) plane of 0 ° to 8 ° is prepared as the substrate 2 (see FIG. 1). Such a substrate can be obtained by, for example, a method of cutting a substrate from an ingot having a (0001) plane as a main surface in a <1-100> direction at a predetermined angle of 0 ° to 8 ° in an off angle θ. it can.

Next, a buffer layer forming step (S20) is performed. Specifically, the buffer layer 21 is made of silicon carbide of n-type conductivity, and for example, an epitaxial layer having a thickness of 0.5 μm is formed. At this time, for example, SiH ₄ gas and C ₃ H ₈ gas are used as source gases for forming the buffer layer. For example, a value of 5 × 10 ¹⁷ cm ⁻³ can be used as the concentration of the conductive impurity in the buffer layer 21.

Next, an epitaxial layer forming step (S30) is performed. Specifically, the breakdown voltage holding layer 22 is formed on the buffer layer 21. As the breakdown voltage holding layer 22, a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method. In this epitaxial layer forming step (S30), for example, SiH ₄ gas and C ₃ H ₈ gas can be used as source gases. In this way, a structure as shown in FIG. 7 is obtained.

For example, a value of 10 μm can be used as the thickness of the breakdown voltage holding layer 22. Further, as the concentration of the n-type conductive impurity in the breakdown voltage holding layer 22, for example, a value of 5 × 10 ¹⁵ cm ⁻³ can be used. Moreover, the thickness of the pressure | voltage resistant holding layer 22 is good also as 0.5 micrometer or more and 100 micrometers or less.

Next, an injection step (S40) is performed. Specifically, p region 23 (see FIG. 8) is formed by implanting p-type impurity into breakdown voltage holding layer 22 using an oxide film formed by photolithography and etching as a mask. To do. Further, after removing the used oxide film, an oxide film having a new pattern is formed again by photolithography and etching. Then, using the oxide film as a mask, an n-type conductive impurity is implanted into a predetermined region, thereby forming an n ⁺ region 24 (see FIG. 8). Further, by using a similar method, a p ⁺ region 25 (see FIG. 8) is formed by implanting a p-type conductive impurity. Note that the concentration of the conductive impurity in the p region 23 is 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less, preferably 1 × 10 ¹⁴ / cm ³ or more and 5 × 10 ¹⁷ / cm ³ or less. Preferably, it can be 1 × 10 ¹⁵ / cm ³ or more and 5 × 10 ¹⁶ / cm ³ or less.

  After such an implantation step (S40), an activation annealing process is performed. As this activation annealing treatment, for example, argon gas is used as an atmospheric gas, and conditions such as a heating temperature of 1700 ° C. and a heating time of 30 minutes can be used. In this way, the structure shown in FIG. 8 is obtained.

Next, a gate insulating film formation step (S50) is performed. Specifically, an oxide film 26 is formed so as to cover the breakdown voltage holding layer 22, the p region 23, the n ⁺ region 24, and the p ⁺ region 25. As a condition for forming this oxide film 26, for example, dry oxidation (thermal oxidation) may be performed. As conditions for this dry oxidation, conditions such as a heating temperature of 1200 ° C. and a heating time of 30 minutes can be used. In this way, the structure shown in FIG. 9 is obtained.

Next, an electrode forming step (S60) is performed. Specifically, a resist film having a pattern is formed on the oxide film 26 by using a photolithography method. Using this resist film as a mask, portions of oxide film 26 located on n ⁺ region 24 and p ⁺ region 25 are removed by etching. Thereafter, a conductor film such as a metal is formed on the resist film and inside the opening formed in the oxide film 26 so as to be in contact with the n ⁺ region 24 and the p ⁺ region 25. Thereafter, by removing the resist film, the conductor film located on the resist film is removed (lifted off). Here, for example, nickel (Ni) can be used as the conductor. As a result, the source electrode 11 can be obtained as shown in FIG. In addition, it is preferable to perform the heat processing for alloying here. Specifically, for example, an argon (Ar) gas that is an inert gas is used as the atmosphere gas, and a heat treatment (alloying treatment) is performed with a heating temperature of 950 ° C. and a heating time of 2 minutes.

  Thereafter, the upper source electrode 27 (see FIG. 1) is formed on the source electrode 11. Further, the gate electrode 10 is formed on the oxide film 26 as a gate insulating film. Further, the drain electrode 12 (see FIG. 1) is formed on the back surface of the substrate 2. In this way, the semiconductor device shown in FIG. 1 can be obtained.

  Further, a 4H—SiC substrate having a (0001) plane as a main surface may be used as the substrate 2. That is, the semiconductor device 1 is formed on the main surface of the substrate 2 and the substrate 2 composed of a 4H—SiC substrate having a (0001) plane as a main surface as a hexagonal SiC substrate having a {0001} plane as a main surface. P region 23 as an SiC epitaxial growth layer, and oxide film 26 as an insulating film formed on the surface of p region 23. Such a substrate 2 can be obtained, for example, by a method of cutting a substrate from an ingot having a (0001) plane as a main surface. Here, the (0001) plane as the main surface means that the off-angle in any direction of the (0001) plane is 1 ° or less, preferably 0.5 ° or less, more preferably 0 °. . Further, by using an SiC substrate having such a (0001) plane as the main surface, there can be almost no terrace step at the interface between the breakdown voltage holding layer 22 and the oxide film 26. The interface state density of can be further reduced. For this reason, the carrier mobility in the vicinity of the interface can be improved as compared with the structure shown in FIGS.

As a method for manufacturing a semiconductor device using a 4H—SiC substrate having the (0001) plane as the main surface as the substrate 2 as described above, the manufacturing method shown in FIG. 6 can be basically used. However, in the buffer layer forming step (S20) and the epitaxial layer forming step (S30), it is important to suppress, for example, two-dimensional nucleation and maintain step flow epi. For this purpose, the surface of the substrate 2 is flattened by etching with H ₂ or HCl gas before epitaxial growth, and the epitaxial growth temperature is 1500 ° C. or higher and 1700 ° C. or lower, more preferably 1550 because it is possible to further suppress the mixing of polytypes. A condition is used in which the step flow is maintained by maintaining the temperature within the range of from 0 ° C. to 1650 ° C. and suppressing the epitaxial growth rate to 10 μm or less.

(Embodiment 2)
FIG. 11 is a schematic cross-sectional view showing a second embodiment of the semiconductor device according to the present invention. Referring to FIG. 11, the first embodiment of the semiconductor device according to the present invention will be described.

A semiconductor device 1 shown in FIG. 11 is a lateral MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as a silicon carbide semiconductor device, which includes a substrate 2, a buffer layer 21, an epitaxial layer 3, a p-type layer 4, n ⁺ Regions 5 and 6, p ⁺ region 25, oxide film 8, gate electrode 10, source electrode 11, and drain electrode 12. Specifically, the semiconductor device 1 includes a substrate 2 made of silicon carbide (SiC). A buffer layer 21 made of silicon carbide is formed on the substrate 2. An epitaxial layer 3 made of silicon carbide is formed on the buffer layer 21. A p-type layer 4 made of silicon carbide is formed on the epitaxial layer 3.

N ⁺ regions 5 and 6 are formed on the surface of the p-type layer 4 at intervals. An oxide film 8 as a gate insulating film is formed on the channel region between n ⁺ regions 5 and 6. A gate electrode 10 is formed on the oxide film 8. A source electrode 11 and a drain electrode 12 are formed on each of the n ⁺ regions 5 and 6. As the substrate 2, a 4H—SiC substrate which is a hexagonal SiC substrate is used. The substrate 2 contains n-type conductive impurities. More specifically, the semiconductor device 1 is formed on the surface of the substrate 2, which is a hexagonal SiC substrate having an off angle θ of 0 ° to 8 ° in the <1-100> direction of the {0001} plane, and the surface of the substrate 2. P-type layer 4 as the SiC epitaxial growth layer formed, oxide film 8 as an insulating film formed on the surface of p-type layer 4, and a region under oxide film 8 (under oxide film 8 in p-type layer 4) N ⁺ region 5 as a conductive region formed at a position adjacent to the region located below oxide film 8 of p-type layer 4 in order to supply electrons flowing to the interface between oxide region 8 and the region located). 6.

The epitaxial layer 3 made of silicon carbide formed on the buffer layer 21 is an undoped layer. The p-type layer 4 formed on the epitaxial layer 3 contains p-type conductive impurities. The n ⁺ regions 5 and 6 are implanted with n-type conductive impurities.

Oxide films 7 and 8 are formed so as to cover p-type layer 4 and n ⁺ regions 5 and 6. Openings are formed in the oxide films 7 and 8 in regions located on the n ⁺ regions 5 and 6. Inside the opening, a source electrode 11 and a drain electrode 12 electrically connected to each of the n ⁺ regions 5 and 6 are formed. A gate electrode 10 is disposed on the oxide film 8 that acts as a gate insulating film. The channel length, which is the distance between n ⁺ regions 5 and 6, can be about 100 μm, for example. Further, the channel width can be, for example, about twice the channel length (about 200 μm).

  A substrate 2 constituting the semiconductor device 1 shown in FIG. 11 has a hexagonal crystal in which the off angle θ in the <1-100> direction of the (0001) plane is greater than 0 ° and equal to or less than 8 °, as in the semiconductor device shown in FIG. This is a system SiC substrate (specifically, a 4H—SiC substrate). In this way, at least in the interface region with the oxide film 8 in the surface of the p-type layer 4 that is an SiC epitaxial growth layer, a step-like shape with the (0001) plane as shown in FIGS. A terrace can be formed on the surface of the p-type layer 4. As a result, similarly to the semiconductor device 1 shown in FIG. 1, the carrier mobility in the vicinity of the interface between the oxide film 8 and the p-type layer 4 can be improved.

  12 to 16 are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG. With reference to FIGS. 12-16, the manufacturing method of Embodiment 2 of the semiconductor device by this invention is demonstrated.

  The manufacturing method of the semiconductor device 1 shown in FIG. 11 basically includes the same steps as the manufacturing method of the semiconductor device shown in FIG. Specifically, first, as shown in FIG. 6, a substrate preparation step (S10) is performed. In this step, specifically, a hexagonal SiC substrate (4H-SiC substrate) having an off angle θ in the <1-100> direction of the (0001) plane of more than 0 ° and not more than 8 ° is used as the substrate 2 (see FIG. 11). ) Prepare as.

  Next, a buffer layer forming step (S20) is performed. As the process conditions in this step (S20), the same conditions as those in the buffer layer forming step (S20) in the semiconductor device manufacturing method shown in FIG. 6 can be used. As a result, the buffer layer 21 (see FIG. 12) made of silicon carbide can be formed on the main surface of the substrate 2.

  Next, an epitaxial layer forming step (S30) is performed. Specifically, as shown in FIG. 12, an undoped silicon carbide epitaxial layer 3 is formed on the buffer layer 21 using an epitaxial growth method. In this way, the structure shown in FIG. 12 is obtained.

Next, an implantation step (S40) is performed in the same manner as in the method for manufacturing the semiconductor device shown in FIG. Specifically, first, a p-type layer 4 is formed as shown in FIG. 13 by injecting a conductive impurity (for example, aluminum (Al)) having p-type conductivity into the epitaxial layer 3. The conductive impurity concentration in the p-type layer 4 can be set to 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. Next, n ⁺ regions 5 and 6 are formed as shown in FIG. 14 by implanting an impurity having n type conductivity. As the n-type conductive impurity, for example, phosphorus (P) can be used. Next, a p ⁺ region 25 is formed as shown in FIG. 14 by implanting a p-type conductive impurity. For example, aluminum can be used as the p-type conductive impurity.

In forming the n ⁺ regions 5 and 6 and the p ⁺ region 25, any conventionally known method can be used. For example, after forming an oxide film so as to cover the upper surface of the p-type layer 4, an opening having the same planar shape pattern as the planar shape pattern of the region where the n ⁺ regions 5 and 6 are to be formed by photolithography and etching Is formed on the oxide film. Further, conductive impurities are implanted using the oxide film on which this pattern is formed as a mask. In this way, the n ⁺ regions 5 and 6 described above can be formed. Further, the p ⁺ region 25 can be formed by injecting a p-type conductive impurity using the same method.

  Thereafter, an activation annealing process for activating the implanted impurities is performed. As conditions for this activation annealing treatment, for example, the same conditions as the activation annealing treatment in the method for manufacturing the semiconductor device shown in FIG. 6 can be used.

Next, as shown in FIG. 6, a gate insulating film forming step (S50) is performed. Specifically, after sacrificial oxidation treatment is performed on the upper surfaces of the p-type layer 4, the n ⁺ regions 5 and 6 and the p ⁺ region 25, an oxide film 7 as a gate insulating film is formed as shown in FIG.

Next, an electrode formation step (S60) is performed as shown in FIG. Specifically, a resist film having a pattern is formed on the oxide film 7 by photolithography. Using this resist film as a mask, oxide film 7 is partially removed to form opening 15 in a region located above n ⁺ regions 5 and 6 and p ⁺ region 25. Inside the opening 15, a conductor film to be the source electrode 11 and the drain electrode 12 is formed as shown in FIG. This conductor film is formed with the above-described resist film remaining. Thereafter, the resist film is removed, and the conductor film located on the oxide film 7 is removed (lifted off) together with the resist film, thereby forming the source electrode 11 and the drain electrode 12 as shown in FIG. it can. At this time, the oxide film 8 (a part of the oxide film 7 shown in FIG. 15) located between the source electrode 11 and the drain electrode 12 becomes a gate insulating film of the semiconductor device to be formed.

  Thereafter, a gate electrode 10 (see FIG. 11) is further formed on the oxide film 8 acting as a gate insulating film. As a method for forming the gate electrode 10, the following method can be used. For example, a resist film having an opening pattern located in a region on the oxide film 8 is formed in advance, and a conductor film constituting the gate electrode 10 is formed so as to cover the entire surface of the resist film. Then, by removing the resist film, the conductor film other than the portion of the conductor film to be the gate electrode 10 is removed (lifted off). As a result, the gate electrode 10 is formed as shown in FIG. In this way, a semiconductor device as shown in FIG. 11 can be obtained.

  Further, a 4H—SiC substrate having a (0001) plane as a main surface may be used as the substrate 2. That is, the semiconductor device 1 is formed on the main surface of the substrate 2 and the substrate 2 composed of a 4H—SiC substrate having a (0001) plane as a main surface as a hexagonal SiC substrate having a {0001} plane as a main surface. A p-type layer 4 as an SiC epitaxial growth layer and an oxide film 8 as an insulating film formed on the surface of the p-type layer 4 are provided. Such a substrate 2 can be obtained, for example, by a method of cutting a substrate from an ingot having a (0001) plane as a main surface. Further, by using an SiC substrate having such a (0001) plane as the main surface, there can be almost no terrace step at the interface between the p-type layer 4 and the oxide film 8. The interface state density of can be further reduced. For this reason, the carrier mobility in the vicinity of the interface can be improved as compared with the structure shown in FIGS.

  The semiconductor device manufacturing method using the 4H—SiC substrate having the (0001) plane as the main surface as the substrate 2 as described above is basically the same method as the semiconductor device manufacturing method shown in FIG. be able to. However, in the buffer layer formation step (S20) and the epitaxial layer formation step (S30), the process conditions for forming an epitaxial growth layer on the (0001) plane shown in the first embodiment of the present invention are applied.

  The semiconductor device shown in FIGS. 1 and 11 may be manufactured using an epitaxial layer-attached substrate 20 as shown in FIG. 17, for example. FIG. 17 is a schematic perspective view showing a substrate with an epitaxial layer according to the present invention.

  As shown in FIG. 17, the substrate with an epitaxial layer 20 according to the present invention has a hexagonal SiC substrate (4H−) with an off angle θ in the <1-100> direction of the (0001) plane exceeding 0 ° and not more than 8 °. (SiC substrate) or a substrate 2 which is a hexagonal SiC substrate (4H-SiC substrate) having a (0001) plane as a main surface, and SiC as an SiC epitaxial growth layer formed on the main surface of the substrate 2 An epitaxial layer 3 and an oxide film 7 as an insulating film formed on the epitaxial layer 3 are provided. A buffer layer 21 as shown in FIGS. 1 and 11 may be formed between the epitaxial layer 3 and the substrate 2. Conventionally known processes such as an impurity implantation process, an etching process for forming an opening in the oxide film 7, a film forming process and an etching process for forming an electrode are performed on the substrate 20 with an epitaxial layer. By carrying out, a semiconductor device as shown in FIGS. 1 and 11 may be manufactured.

  Further, by performing steps (S10) to (S50) in the manufacturing method shown in FIG. 6, that is, an impurity region necessary for the semiconductor device is formed by an implantation step, and then oxide film 7 is formed to form an epitaxial layer. The attached substrate 20 may be obtained.

(Embodiment 3)
FIG. 18 is a schematic cross-sectional view showing a third embodiment of the semiconductor device according to the present invention. With reference to FIG. 18, a semiconductor device according to a first embodiment of the present invention will be described.

The semiconductor device 1 shown in FIG. 18 is a lateral MOSFET and basically has the same configuration as the semiconductor device 1 shown in FIG. 11, but directly on the substrate 2 with the p-type layer 4, the n ⁺ region 5, 6. The difference is that a p ⁺ region 25 is formed. That is, the semiconductor device 1 includes a substrate 2 that is a hexagonal SiC substrate having an off angle θ of 0 ° to 8 ° in the <1-100> direction of the {0001} plane, and an insulation formed on the surface of the substrate 2. To supply electrons flowing to the interface between the oxide film 8 and the oxide film 8 and the region under the oxide film 8 (region located under the oxide film 8 in the p-type layer 4 formed on the substrate 2). , And n ⁺ regions 5 and 6 as conductive regions formed at positions adjacent to the region. As shown in FIG. 18, oxide film 8 is in contact with p-type layer 4 and n ⁺ regions 5 and 6 formed by implantation into substrate 2 made of SiC. Then, at the contact interface between the oxide film 8 and the p-type layer 4, a stepped terrace having the (0001) plane as an upper surface as shown in FIGS. 2 and 3 is formed on the surface of the p-type layer 4. . Such a terrace is formed, for example, by etching the substrate surface at a high temperature of 1500 ° C. or higher in an H ₂ or HCl atmosphere, or by forming a Si layer on the substrate surface and performing a heat treatment at 1400 ° C. or higher. Also by the semiconductor device 1 shown in FIG. 18, the same effect as that of the semiconductor device 1 shown in FIG. 11 can be obtained.

  FIG. 19 is a flowchart for explaining a method of manufacturing the semiconductor device shown in FIG. With reference to FIG. 19, the manufacturing method of Embodiment 3 of the semiconductor device by this invention is demonstrated.

  As shown in FIG. 19, a substrate preparation step (S10) is first performed. Here, similarly to the method for manufacturing the semiconductor device shown in FIG. 6, a hexagonal SiC substrate (4H-SiC substrate) in which the off angle θ in the <1-100> direction of the (0001) plane is greater than 0 ° and equal to or less than 8 °. ) Is prepared as a substrate 2 (see FIG. 18).

Next, an injection step (S40) is performed. Specifically, first, a p-type layer 4 is formed as shown in FIG. 18 by injecting a conductive impurity (for example, aluminum (Al)) having p-type conductivity into the substrate 2. The conductive impurity concentration in the p-type layer 4 can be set to 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. Next, n ⁺ regions 5 and 6 shown in FIG. 18 are formed by implanting an impurity having n type conductivity. Next, a p ⁺ region 25 is formed as shown in FIG. 18 by implanting a p-type conductive impurity.

When forming the n ⁺ regions 5 and 6 and the p ⁺ region 25, any conventionally known method can be used as in the method of manufacturing the semiconductor device shown in FIG. For example, after an oxide film is formed so as to cover the main surface of the substrate 2, an opening having the same planar shape pattern as the planar shape pattern of the region where the n ⁺ regions 5 and 6 are to be formed is formed by photolithography and etching. An oxide film is formed. Further, conductive impurities are implanted into the substrate 2 using the oxide film on which this pattern is formed as a mask. In this way, the n ⁺ regions 5 and 6 described above can be formed. Further, the p ⁺ region 25 can be formed by injecting a p-type conductive impurity into the substrate 2 using a similar method.

  Thereafter, an activation annealing process for activating the implanted impurities is performed. As conditions for this activation annealing treatment, for example, the same conditions as the activation annealing treatment in the method for manufacturing the semiconductor device shown in FIG. 6 can be used.

Next, a gate insulating film formation step (S50) is performed. Specifically, after sacrificial oxidation treatment is performed on the upper surfaces of the p-type layer 4, the n ⁺ regions 5 and 6, and the p ⁺ region 25, an oxide film as a gate insulating film is formed.

  Next, an electrode forming step (S60) is performed. In this electrode formation step (S60), the same step as the electrode formation step in the method for manufacturing the semiconductor device shown in FIG. 11 can be used. As a result, the source electrode 11, the drain electrode 12, and the gate electrode 10 can be formed as shown in FIG.

Further, a 4H—SiC substrate having a (0001) plane as a main surface may be used as the substrate 2. That is, the semiconductor device 1 shown in FIG. 18 includes a substrate 2 that is a 4H—SiC substrate having a (0001) plane as a main surface as a hexagonal SiC substrate having a {0001} plane as a main surface, In order to supply the oxide film 8 formed on the surface as an insulating film, and electrons flowing to the interface between the oxide film 8 and a region under the oxide film 8 (region located under the oxide film 8 in the p-type layer 4). , And n ⁺ regions 5 and 6 as conductive regions formed at positions adjacent to the above regions. Such a substrate 2 can be obtained, for example, by a method of cutting a substrate from an ingot having a (0001) plane as a main surface. Further, by using an SiC substrate having such a (0001) plane as the main surface, there can be almost no terrace step at the interface between the p-type layer 4 and the oxide film 8. The interface state density of can be further reduced. For this reason, the carrier mobility in the vicinity of the interface can be improved as compared with the structure shown in FIGS.

  The semiconductor device manufacturing method using the 4H—SiC substrate having the (0001) plane as the main surface as the substrate 2 as described above is basically the same method as the semiconductor device manufacturing method shown in FIG. be able to.

  The semiconductor device shown in FIG. 18 may be manufactured using, for example, a substrate 30 as shown in FIG. FIG. 20 is a schematic perspective view showing a substrate according to the present invention.

  As shown in FIG. 20, the substrate 30 according to the present invention has a hexagonal SiC substrate (4H-SiC substrate) having an off angle θ in the <1-100> direction of the (0001) plane of 0 ° to 8 °. Or a substrate 2 which is a 4H—SiC substrate having a (0001) plane as a main surface, and an oxide film 7 as an insulating film formed on the main surface of the substrate 2. Conventionally known processes such as an impurity implantation process, an etching process for forming an opening in the oxide film 7, a film forming process for forming an electrode, and an etching process are performed on such a substrate 30. Thus, a semiconductor device as shown in FIG. 18 may be manufactured.

  Further, by performing steps (S10) to (S50) in the manufacturing method shown in FIG. 19, that is, an impurity region necessary for the semiconductor device is formed by an implantation step, and then oxide film 7 is formed to form substrate 30. You may get

In the substrate 20 with an epitaxial layer shown in FIG. 17, the conductive impurity concentration in the region located under the oxide film 7 in the epitaxial layer 3 is 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. May be. In this case, for example, a substrate 20 with an epitaxial layer suitable for manufacturing a semiconductor device such as a MOSFET can be obtained. The conductive impurity concentration is preferably 1 × 10 ¹⁴ / cm ³ or more and 5 × 10 ¹⁷ / cm ³ or less, more preferably 1 × 10 ¹⁵ / cm ³ or more and 5 × 10 ¹⁶ / cm ³ or less.

  In the substrate 20 with an epitaxial layer, the thickness of the epitaxial layer 3 may be not less than 0.5 μm and not more than 100 μm. In this case, the substrate 20 with an epitaxial layer suitable for manufacturing a semiconductor device can be obtained.

In the substrate 30 illustrated in FIG. 20, the conductive impurity concentration in the region located under the oxide film 7 in the substrate 2 may be 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less. In this case, the board | substrate 30 suitable for manufacture of MOSFET etc. can be obtained.

  In the substrate 30, the substrate 20 with an epitaxial layer, and the semiconductor device 1, the value of the off angle θ of the substrate 2 exceeds 0 ° is off in order to increase the area of the upper surface of one terrace. This is because it is advantageous to make the angle θ as small as possible. The reason why the upper limit of the off angle θ is set to 8 ° is that if the off angle θ is up to about 8 °, sufficient characteristics (carrier mobility) at the MOS interface when the MOSFET is formed can be obtained. It is.

  In the substrate 30, the substrate with epitaxial layer 20, and the semiconductor device 1, the off angle θ may be 0.5 ° or more and 6 ° or less. Here, the off-angle θ is set to 0.5 ° or more. If the off-angle θ is 0.5 ° or more, the substrate 2 having a flat surface is relatively difficult to be affected by the warp and unevenness of the substrate 2. This is because it is relatively easy to prepare. Further, the upper limit of the off angle θ is set to 6 ° when the off angle θ exceeds 6 ° when the MOS interface characteristics are improved (the carrier mobility is improved) when the off angle θ is 6 ° or less. This is because the size of the terrace becomes smaller and the value of the interface state density becomes larger.

  In the substrate 30, the substrate 20 with an epitaxial layer, and the semiconductor device 1, the off angle θ of the substrate 2 may be 1 ° or more. Here, the reason why the off-angle θ is set to 1 ° or more is that a uniform and flat substrate 2 can be obtained relatively easily if the off-angle θ is set to 1 ° or more.

  In the substrate 30, the substrate 20 with an epitaxial layer, and the semiconductor device 1, the off angle θ of the substrate 2 may be 2 ° or more. This is because when the off-angle θ is 2 ° or more, a uniform and flat substrate 2 can be easily obtained.

  In the substrate 30, the substrate 20 with an epitaxial layer, and the semiconductor device 1, the off angle θ of the substrate 2 may be 3 ° or more and 5 ° or less. When the range of the off angle θ is limited in this way, the epitaxial layer 3 and the oxide films 7 and 26 made of SiC can be stably formed on the surface of the substrate 2.

  In the substrate 30 or the substrate 20 with an epitaxial layer or the semiconductor device 1, the off-angle direction of the {0001} plane is the <1-100> direction. The direction in which the {0001} plane is inclined is < Within a range of 1-100> direction ± 7.5 ° (range of 15 ° centered on <1-100> direction), more preferably within a range of <1-100> direction ± 5 ° of SiC substrate (<1- In the range of 10 ° centered on the 100> direction), more preferably in the range of ± 1 ° to the <1-100> direction of the SiC substrate (range of 5 ° around the <1-100> direction). Means that

  In addition, when describing a crystal plane and a crystal direction, when describing a negative numerical value, it is common to indicate a bar on the numerical value, but the claims, description, abstract, drawings of the present application In FIG. 4, for convenience, “− (minus)” is added before the numerical value.

  The semiconductor device according to the present invention has been described by taking the MOSFET as an example as described above. However, the present invention may be applied to semiconductor devices having other configurations, such as an IGBT (Insulated Gate Bipolar Transistor) and a GTO (Gate Turn Off Thyristor). Can be applied.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is particularly advantageously applied to a semiconductor device in which an insulating film is formed on a semiconductor layer and carriers such as electrons move on the interface between the semiconductor layer and the insulating film.

1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a schematic plan view showing a terrace formed on the surface of a pressure resistant holding layer in the semiconductor device shown in FIG. 1. It is a cross-sectional schematic diagram in line segment III-III of FIG. A plane showing a terrace formed on the surface of the breakdown voltage holding layer when a semiconductor device having the same configuration as that of the semiconductor device shown in FIG. 1 is formed using a SiC substrate having an off-angle direction of <11-20> direction. It is a schematic diagram. It is a cross-sectional schematic diagram in line segment VV of FIG. 2 is a flowchart for explaining a method of manufacturing the semiconductor device shown in FIG. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a cross-sectional schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a cross-sectional schematic diagram which shows Embodiment 2 of the semiconductor device by this invention. FIG. 12 is a schematic cross sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 11. FIG. 12 is a schematic cross sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 11. FIG. 12 is a schematic cross sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 11. FIG. 12 is a schematic cross sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 11. FIG. 12 is a schematic cross sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 11. It is a perspective schematic diagram which shows the board | substrate with an epitaxial layer according to this invention. It is a cross-sectional schematic diagram which shows Embodiment 3 of the semiconductor device by this invention. 19 is a flowchart for explaining a manufacturing method of the semiconductor device shown in FIG. 18; It is a perspective schematic diagram which shows the board | substrate according to this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2, 30 board | substrate, 3 epitaxial layer, 4 p-type layer, 5, 6, 24 n ⁺ area | region, 7, 8, 26 oxide film, 10 gate electrode, 11 source electrode, 12 drain electrode, 13 boundary, 15 opening, 16 upper side, 17 lower side, 18, 19 arrow, 20 substrate with epitaxial layer, 21 buffer layer, 22 breakdown voltage holding layer, 23 p region, 25 p ⁺ region, 27 upper source electrode.

Claims (17)

A hexagonal SiC substrate having an off angle θ in the <1-100> direction of the {0001} plane of 0 ° to 8 °,
A SiC epitaxial growth layer formed on the surface of the SiC substrate;
A substrate with an epitaxial layer, comprising: an insulating film formed on a surface of the SiC epitaxial growth layer.   The substrate with an epitaxial layer according to claim 1, wherein the off-angle is not less than 0.5 ° and not more than 6 °.   The substrate with an epitaxial layer according to claim 1, wherein the off-angle is 1 ° or more and 6 ° or less.   The substrate with an epitaxial layer according to claim 1, wherein the off-angle is 3 ° or more and 5 ° or less. A hexagonal SiC substrate having a {0001} plane as a main surface;
A SiC epitaxial growth layer formed on the main surface of the SiC substrate;
A substrate with an epitaxial layer, comprising: an insulating film formed on a surface of the SiC epitaxial growth layer. The conductive impurity concentration of the region located under the insulating film in the SiC epitaxial growth layer is 1 × 10 ¹³ / cm ³ or more and 1 × 10 ¹⁸ / cm ³ or less, according to claim 1. Substrate with epitaxial layer.   The substrate with an epitaxial layer according to claim 1, wherein a thickness of the SiC epitaxial growth layer is 0.5 μm or more and 100 μm or less. A hexagonal SiC substrate having an off angle θ in the <1-100> direction of the {0001} plane of 0 ° to 8 °,
A substrate comprising an insulating film formed on a surface of the SiC substrate.   The substrate according to claim 8, wherein the off angle is not less than 0.5 ° and not more than 6 °.   The substrate according to claim 8, wherein the off angle is not less than 1 ° and not more than 6 °.   The substrate according to claim 8, wherein the off-angle is 3 ° or more and 5 ° or less. A hexagonal SiC substrate having a {0001} plane as a main surface;
A substrate comprising an insulating film formed on a main surface of the SiC substrate. The conductive impurity concentration in the region located under the insulating film is 1 × ¹⁰ 18 / cm ³ or less 1 × ¹⁰ 13 / cm ³ or more in the SiC substrate, according to any one of claims 8 to 12 substrate. A hexagonal SiC substrate having an off angle θ in the <1-100> direction of the {0001} plane of 0 ° to 8 °,
A SiC epitaxial growth layer formed on the surface of the SiC substrate;
An insulating film formed on the surface of the SiC epitaxial growth layer;
A semiconductor device comprising: a conductive region formed at a position adjacent to the region for supplying electrons flowing to an interface between the region under the insulating film and the insulating film. A hexagonal SiC substrate having an off angle θ in the <1-100> direction of the {0001} plane of 0 ° to 8 °,
An insulating film formed on the surface of the SiC substrate;
A semiconductor device comprising: a conductive region formed at a position adjacent to the region for supplying electrons flowing to an interface between the region under the insulating film and the insulating film. A hexagonal SiC substrate having a {0001} plane as a main surface;
A SiC epitaxial growth layer formed on the main surface of the SiC substrate;
An insulating film formed on the surface of the SiC epitaxial growth layer;
A semiconductor device comprising: a conductive region formed at a position adjacent to the region for supplying electrons flowing to an interface between the region under the insulating film and the insulating film. A hexagonal SiC substrate having a {0001} plane as a main surface;
An insulating film formed on the main surface of the SiC substrate;
A semiconductor device comprising: a conductive region formed at a position adjacent to the region for supplying electrons flowing to an interface between the region under the insulating film and the insulating film.

Images