JP2012038771A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-quality and low-cost semiconductor device and a manufacturing method thereof.SOLUTION: A semiconductor device manufacturing method comprises: a step of preparing a substrate in which a silicon carbide layer such as a withstand voltage layer having a surface substantially including a {0-33-8} face is formed on a principal face; a step (S1) of injecting a conductive impurity into the silicon carbide layer; and a step (S2) of performing heat treatment for activating the injected conductive impurity. In the step of performing the heat treatment, the surface of the silicon carbide layer is exposed to an atmosphere gas for the heat treatment.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to a semiconductor device using an inclined surface formed in a silicon carbide layer and including a predetermined crystal plane, and a manufacturing method thereof.

  Conventionally, it has been proposed to use silicon carbide (SiC) as a material for a semiconductor device. For example, in Patent Document 1 (Japanese Patent Laid-Open No. 2001-68428), since a semiconductor element is formed using silicon carbide, an ion implantation method is used as a method for controlling the conductivity type and the carrier concentration in a selected region. It is disclosed. In Patent Document 1, activation annealing is performed in a state where a protective film made of diamond-like carbon or the like is formed on the surface of silicon carbide in order to prevent surface roughness from occurring in activation annealing after ion implantation. Techniques to do this are disclosed.

JP 2001-68428 A

  As disclosed in Patent Document 1, in activation annealing after ion implantation in silicon carbide, the annealing temperature becomes relatively high. Therefore, in order to obtain a high-quality semiconductor device, a protective film is formed. Therefore, it was considered essential to prevent the occurrence of surface roughness. However, since the protective film is formed only for the activation annealing and the protective film is removed after the activation annealing, the number of manufacturing steps of the silicon carbide semiconductor device is increased. This contributed to an increase in manufacturing costs.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a high-quality and low-cost semiconductor device and a manufacturing method thereof.

  As a result of earnest research, the inventor conducted the activation annealing after ion implantation on the surface of silicon carbide which is substantially a {0-33-8} plane (so-called semipolar plane). As a result, the inventors obtained new knowledge that surface roughness hardly occurs even if a protective film is not formed on the surface.

  In the method of manufacturing a semiconductor device according to the present invention based on the knowledge of the present inventors as described above, a silicon carbide layer having a surface substantially including a {0-33-8} plane is formed on the main surface. A step of preparing the substrate, a step of injecting conductive impurities into the silicon carbide layer, and a step of performing a heat treatment for activating the injected conductive impurities. In the step of performing the heat treatment, the surface of the silicon carbide layer is exposed to an atmosphere gas for performing the heat treatment. Here, the surface which is substantially the {0-33-8} plane means that the crystal plane constituting the surface is the {0-33-8} plane and the crystal constituting the surface It means that the surface is a surface having an off angle with respect to the {0-33-8} plane in the <1-100> direction of -3 ° or more and 3 ° or less. The “off angle with respect to the {0-33-8} plane in the <1-100> direction” means an orthogonal projection of the normal of the end face to the plane extending in the <1-100> direction and the <0001> direction. , The angle formed with the normal of the {0-33-8} plane, the sign is positive when the orthographic projection approaches parallel to the <1-100> direction, and the orthographic projection is < The case of approaching parallel to the 0001> direction is negative.

  In this way, since it is not necessary to form a protective film (cap layer) during activation annealing after ion implantation for silicon carbide, the manufacturing process of the semiconductor device can be simplified as compared with the case of forming the protective film. Therefore, the manufacturing cost of the semiconductor device can be reduced.

  A semiconductor device according to the present invention includes a substrate having a main surface, and a silicon carbide layer formed on the main surface of the substrate and including an end face inclined with respect to the main surface. The end face substantially includes a {0-33-8} plane. The end face includes a conductive impurity implantation region (ion implantation region).

  In this way, in the activation annealing after injecting the conductive impurities to the end face, the activation annealing can be performed without forming a protective film, so that a semiconductor device with reduced manufacturing costs can be obtained. Obtainable.

  In addition, since the end face of the silicon carbide layer is substantially the {0-33-8} plane, by making these end faces that are so-called semipolar planes into an ion implantation area, the ion implantation area Can be used as a channel region (active region) of the semiconductor device, for example. Here, the end face is a stable crystal face, and high channel mobility can be obtained. Therefore, a high-quality semiconductor that exhibits higher channel mobility when used in a channel region configured by ion implantation of the end face than when other crystal planes (for example, (0001) plane) are used as the channel region. A device can be realized. Further, since the end face substantially includes the {0-33-8} plane, a step (step) is formed on the end face as in the case where the crystal orientation of the end face deviates from the {0-33-8} plane. The occurrence of problems such as a large number and a decrease in channel mobility can be suppressed.

  According to the present invention, a high-quality semiconductor device can be obtained at low cost.

4 is a flowchart for explaining a method for manufacturing a semiconductor device according to the present invention; 4 is a flowchart for explaining a specific example of a method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a schematic cross-sectional view of Embodiment 1 of a semiconductor device according to the present invention manufactured using the method for manufacturing a semiconductor device shown in FIG. 2. It is a cross-sectional schematic diagram of the modification of Embodiment 1 of the semiconductor device by this invention manufactured using the manufacturing method of the semiconductor device shown in FIG. It is a plane schematic diagram which shows Embodiment 2 of the semiconductor device by this invention. It is a cross-sectional schematic diagram in line segment VI-VI of FIG. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic perspective view for illustrating a method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for explaining a modification of the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. FIG. 7 is a schematic cross-sectional view for explaining a modification of the method for manufacturing the semiconductor device shown in FIGS. 5 and 6. It is a cross-sectional schematic diagram which shows Embodiment 3 of the semiconductor by this invention. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. FIG. 19 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 18. It is a cross-sectional schematic diagram which shows the reference example of the semiconductor device by this invention. FIG. 28 is a schematic cross-sectional view showing a modified example of the semiconductor device shown in FIG. 27.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
With reference to FIG. 1, the manufacturing method of the semiconductor device by this invention is demonstrated.

  In the method of manufacturing a semiconductor device according to the present invention, first, a step of preparing a substrate on which a silicon carbide layer having a surface substantially including a {0-33-8} plane is formed on a main surface is performed. Then, as shown in FIG. 1, an ion implantation step (S1), which is a step of implanting conductive impurities into the silicon carbide layer, is performed. Thereafter, an annealing step (S2) for performing a heat treatment for activating the implanted conductive impurities is performed. In the annealing step (S2), the surface including the {0-33-8} plane of the silicon carbide layer is exposed to an atmosphere gas for performing heat treatment. That is, the protective film considered to be essential in the conventional annealing process is not formed on the surface of the silicon carbide layer.

  In this case, it is not necessary to form a protective film (cap layer) in advance when performing the annealing step (S2) after ion implantation for the silicon carbide layer. The manufacturing process can be simplified. Therefore, the manufacturing cost of the semiconductor device can be reduced.

  Here, as the conditions for the annealing step (S2), for example, an inert gas (argon gas) atmosphere, an atmospheric pressure condition, a heating temperature of 1700 ° C., and a heating time of 30 minutes can be used. When, for example, phosphorus ions are implanted into the silicon carbide layer whose surface is the {0-33-8} plane, after performing RCA cleaning, the above annealing process is performed without forming a cap layer. Macro steps (surface roughness) were hardly observed on the surface. For example, a scanning electron microscope (SEM) can be used for the observation of the surface.

  When performing the annealing treatment as described above, if the surface of silicon carbide is a surface having a predetermined off angle from the (0001) surface as in the conventional case, surface annealing occurs due to the annealing treatment. Prior to the annealing treatment, a protective film (for example, a carbon cap obtained by graphitizing a resist film by heat treatment or a carbon cap obtained by depositing carbon by a sputtering method) is formed to cover the surface. In the presence of this protective film, annealing is performed under the above conditions, and then the protective film is removed (for example, by performing a heat treatment such as a heating temperature of 900 ° C. in an oxygen atmosphere and a heating time of 30 minutes). The treatment for removing the carbon cap). However, according to the present invention, it is not necessary to perform the protective film forming step and the protective film removing step which are conventionally required. Therefore, according to the present invention, as described above, the manufacturing process of the semiconductor device can be simplified.

A specific example of the semiconductor device manufacturing method described above will be described with reference to FIGS.
Referring to FIG. 2, the method of manufacturing the semiconductor device in the present embodiment shown in FIG. 3 is a method of manufacturing an insulated gate bipolar transistor (IGBT) which is a vertical semiconductor device. A step of preparing a substrate (S10) is performed. In this step (S10), referring to FIG. 3, substrate 1 made of single crystal silicon carbide and having a p-type conductivity is prepared. The crystal plane orientation of the main surface of the substrate 1 is substantially a {0-33-8} plane, preferably a {0-33-8} plane.

  Next, an epitaxial growth step (S20) is performed. In this step (S20), referring to FIG. 3, a p-type epitaxial layer 36, which is a p-type buffer layer made of silicon carbide on one main surface of substrate 1 by epitaxial growth, and a breakdown voltage which is a drift layer. The holding layer 2 is formed sequentially. The plane orientation of the upper surface of the breakdown voltage holding layer 2 is substantially a {0-33-8} plane.

Next, an ion implantation step (S30) is performed. In this step (S30), referring to FIG. 3, first, ion implantation for forming p type body layer 3 which is a well region is performed. Specifically, for example, p-type body layer 3 is formed by implanting Al (aluminum) ions into breakdown voltage holding layer 2. Next, ion implantation for forming n-type source contact layer 4 is performed. Specifically, for example, P (phosphorus) ions are implanted into the p-type body layer 3 to form the n-type source contact layer 4 in the p-type body layer 3 that is a well region. Further, ion implantation for forming the contact region 5 having the p-type conductivity is performed. Specifically, for example, Al ions are implanted into the p-type body layer 3 to form the p-type contact region 5 in the p-type body layer 3. The ion implantation can be performed, for example, by forming a mask layer made of silicon dioxide (SiO ₂ ) on the main surface of the breakdown voltage holding layer 2 and having an opening in a desired region where ion implantation is to be performed.

  Next, an activation annealing step (S40) is performed. In this step (S40), a heat treatment is performed in which the substrate including the withstand voltage holding layer 2 on which the ion implantation has been performed is heated to 1700 ° C. in an inert gas atmosphere such as argon and held for 30 minutes. Thereby, the impurities implanted in the step (S30) are activated. In this step (S40), no protective film or the like is particularly formed on the upper surface of the breakdown voltage holding layer 2 on which the above-described ion implantation is performed, and the upper surface is exposed to the annealing atmosphere. ing. And since the surface of the pressure | voltage resistant holding | maintenance layer 2 becomes a {0-33-8} surface substantially, surface roughness hardly generate | occur | produces by the said activation annealing.

  Next, an oxide film forming step (S50) is performed. In this step (S50), for example, a heat treatment is performed on the substrate on which the breakdown voltage holding layer 2 has been formed after the activation annealing step is heated to 1300 ° C. and held for 60 minutes in an oxygen atmosphere. Thus, the oxide film (gate insulating film 8) shown in FIG. 3 is formed.

  Next, an electrode formation step (S60) is performed. In this step (S60), gate electrode 9 made of polysilicon which is doped with impurities to form a conductor is formed by, for example, CVD. Further, an opening 11 as shown in FIG. 3 is formed in the gate insulating film 8 in a region located on the n-type source contact layer 4 and the p-type contact region 5. As a method for forming the opening 11, any conventionally known method can be used. Next, for example, a nickel (Ni) film formed by vapor deposition is heated to be silicided, thereby forming an emitter contact electrode (source electrode 12) and a collector electrode (drain electrode 112). Next, an emitter wiring (source wiring electrode 13) made of Al as a conductor is formed as shown in FIG. With the above procedure, the semiconductor device 101 in this embodiment is completed.

  A semiconductor device 101 according to the present invention formed by the above manufacturing method is an insulated gate bipolar transistor (IGBT) which is a vertical semiconductor device, and includes a single crystal substrate 1 and a p-type epitaxial layer which is a buffer layer. 36, drift layer (breakdown voltage holding layer 2), p-type body layer 3, n-type source contact layer 4, p-type contact region 5, gate insulating film 8, emitter contact electrode (source electrode 12) and emitter wiring (source wiring) Electrode 13), gate electrode 9 and collector electrode (drain electrode 112) formed on the back side of substrate 1 are provided. Specifically, a p-type epitaxial layer 36 made of silicon carbide is formed on the surface of substrate 1 made of silicon carbide having a p-type conductivity. The p-type epitaxial layer 36 has a p-type conductivity and has a thickness of 0.5 μm, for example. A breakdown voltage holding layer 2 is formed on the p-type epitaxial layer 36. The breakdown voltage holding layer 2 is made of silicon carbide of n-type conductivity, and has a thickness of 10 μm, for example.

  A p-type body layer 3 having a p-type conductivity is formed on the surface of the breakdown voltage holding layer 2 at a distance from each other. Inside the p-type body layer 3, an n-type source contact layer 4 is formed on the surface layer of the p-type body layer 3. A p-type contact region 5 is formed at a position adjacent to the n-type source contact layer 4. The p-type body layer 3, the breakdown voltage holding layer 2 exposed between the two p-type body layers 3, the other p-type body layer 3, and the other one from above the n-type source contact layer 4 in one p-type body layer 3 A gate insulating film 8, which is an oxide film, is formed so as to extend onto the n-type source contact layer 4 in the p-type body layer 3. A gate electrode 9 is formed on the gate insulating film 8. A source electrode 12 is formed on the n-type source contact layer 4 and the p-type contact region 5. A source wiring electrode 13 is formed on the source electrode 12. In the substrate 1, the drain electrode 14 is formed on the back surface that is the surface opposite to the surface on which the p-type epitaxial layer 36 is formed.

  Thus, since the main surface of the breakdown voltage holding layer 2 that is a silicon carbide layer is substantially a {0-33-8} plane, the breakdown voltage holding is performed in the activation annealing step (S40) shown in FIG. An annealing treatment can be performed without forming a protective film covering the surface of the layer 2. Therefore, it is possible to realize a semiconductor device with a lower manufacturing cost than when the protective film is formed. In addition, since the channel region is formed by ion implantation on the {0-33-8} plane, a high-quality semiconductor device exhibiting high channel mobility can be realized.

  Another specific example of the above-described method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. Note that the semiconductor device shown in FIG. 4 is another example of the semiconductor device in this embodiment, and is a vertical DiMOSFET (Double Implanted MOSFET).

  Referring to FIG. 2, the method for manufacturing the semiconductor device in the present embodiment shown in FIG. 4 is a method for manufacturing a vertical DiMOSFET which is a vertical semiconductor device, and first a step of preparing a silicon carbide substrate. (S10) is performed. In this step (S10), with reference to FIG. 4, substrate 1 made of single crystal silicon carbide and having n type conductivity, for example, is prepared. The crystal plane orientation of the main surface of the substrate 1 is substantially a {0-33-8} plane, preferably a {0-33-8} plane.

  Next, an epitaxial growth step (S20) is performed. In this step (S20), with reference to FIG. 4, breakdown voltage holding layer 2 made of silicon carbide and having n type conductivity is formed on one main surface of substrate 1 by epitaxial growth. The plane orientation of the upper surface of the breakdown voltage holding layer 2 is substantially a {0-33-8} plane. A buffer layer may be formed between breakdown voltage holding layer 2 and silicon carbide substrate 1. As the buffer layer, for example, an epitaxial layer made of n-type silicon carbide and having a thickness of 0.5 μm, for example, may be formed.

Next, an ion implantation step (S30) is performed. In this step (S30), referring to FIG. 4, first, ion implantation for forming p type body layer 3 which is a well region is performed. Specifically, for example, p-type body layer 3 is formed by implanting Al (aluminum) ions into breakdown voltage holding layer 2. Next, ion implantation for forming n-type source contact layer 4 is performed. Specifically, for example, P (phosphorus) ions are implanted into the p-type body layer 3 to form the n-type source contact layer 4 in the p-type body layer 3 that is a well region. The ion implantation can be performed, for example, by forming a mask layer made of silicon dioxide (SiO ₂ ) on the main surface of the breakdown voltage holding layer 2 and having an opening in a desired region where ion implantation is to be performed.

  Next, an activation annealing step (S40) is performed. In this step (S40), in the same manner as in step (S40) in the method for manufacturing the semiconductor device shown in FIG. 3, the substrate including the withstand voltage holding layer 2 on which the above-described ion implantation is performed is placed in an inert gas atmosphere such as argon. Inside, a heat treatment is performed by heating to 1700 ° C. and holding for 30 minutes. Thereby, the impurities implanted in the step (S30) are activated. In this step (S40), no protective film or the like is particularly formed on the upper surface of the breakdown voltage holding layer 2 on which the above-described ion implantation is performed, and the upper surface is exposed to the annealing atmosphere. ing. And since the surface of the pressure | voltage resistant holding | maintenance layer 2 becomes a {0-33-8} surface substantially, surface roughness hardly generate | occur | produces by the said activation annealing.

  Next, an oxide film forming step (S50) is performed. In this step (S50), for example, a heat treatment is performed on the substrate on which the breakdown voltage holding layer 2 has been formed after the activation annealing step is heated to 1300 ° C. and held for 60 minutes in an oxygen atmosphere. As a result, the oxide film (gate insulating film 8) shown in FIG. 4 is formed.

  Next, an electrode formation step (S60) is performed. In this step (S60), gate electrode 9 (see FIG. 4) made of polysilicon, which is a conductor added with impurities, is formed by, for example, CVD. Furthermore, in the gate insulating film 8, at least in a region located on the n-type source contact layer 4, the surface of the n-type source contact layer 4 and a part of the surface of the p-type body layer 3 are formed as shown in FIG. An opening to be exposed is formed. As a method for forming the opening, any conventionally known method can be used. Then, an insulating film 10 covering the upper surface and side surfaces of the gate electrode 9 is formed. As a method for forming the insulating film 10, any conventionally known method such as a CVD method or a photolithography method can be used.

  Then, source electrode 12 connected to the exposed portions of n-type source contact layer 4 and p-type body layer 3 is formed using, for example, a lift-off method. For example, nickel (Ni) can be used as the source electrode 12. In addition, it is preferable to perform the heat processing for alloying here. Specifically, for example, an argon (Ar) gas that is an inert gas is used as the atmosphere gas, and a heat treatment (alloying treatment) is performed with a heating temperature of 950 ° C. and a heating time of 2 minutes. Thereafter, the drain electrode 14 is formed on the back side of the substrate 1. With the above procedure, the semiconductor device 101 in this embodiment is completed.

  The semiconductor device according to the present invention formed by the manufacturing method as described above is a vertical DiMOSFET which is a vertical semiconductor device as described above, and includes a substrate 1, a breakdown voltage holding layer 2, a p-type body layer 3, n. A type source contact layer 4, a gate insulating film 8, a source electrode 12, a gate electrode 9, and a drain electrode 14 formed on the back side of the substrate 1 are provided. Specifically, for example, breakdown voltage holding layer 2 made of silicon carbide is formed on the main surface of substrate 1 made of a SiC single crystal of n-type conductivity. A p-type body layer 3 having a p-type conductivity is formed on the surface of the breakdown voltage holding layer 2 at a distance from each other. Inside the p-type body layer 3, an n-type source contact layer 4 is formed on the surface layer of the p-type body layer 3.

  The p-type body layer 3, the breakdown voltage holding layer 2 exposed between the two p-type body layers 3, the other p-type body layer 3, and the other one from above the n-type source contact layer 4 in one p-type body layer 3 A gate insulating film 8 made of an oxide film is formed so as to extend onto the n-type source contact layer 4 in the p-type body layer 3. A gate electrode 9 is formed on the gate insulating film 8. An insulating film 10 is formed so as to cover the end face and the upper surface of the gate electrode 9. A source electrode 12 is formed so as to be connected to a part of the n-type source contact layer 4 and the p-type body layer 3 and to cover the insulating film 10. A drain electrode 14 is formed on the back surface of the substrate 1 opposite to the surface on which the pressure-resistant holding layer 2 is formed.

  Thus, since the main surface of the pressure | voltage resistant holding | maintenance layer 2 which is a silicon carbide layer becomes a {0-33-8} surface substantially, like the case of the manufacturing method of the semiconductor device shown in FIG. In the activation annealing step (S40) shown in FIG. 2, annealing can be performed without forming a protective film covering the surface of the breakdown voltage holding layer 2. For this reason, it is possible to realize a semiconductor device with a reduced manufacturing cost as compared with the case where the protective film is formed, and a high-quality semiconductor device exhibiting high channel mobility.

(Embodiment 2)
A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.

  Referring to FIGS. 5 and 6, a semiconductor device according to the present invention is a vertical MOSFET that is a vertical device using a plurality of mesa structures and grooves with inclined side surfaces formed between the mesa structures. It is. The semiconductor device shown in FIGS. 5 and 6 includes a substrate 1 made of silicon carbide, a breakdown voltage holding layer 2 that is an epitaxial layer made of silicon carbide and having an n-type conductivity, silicon carbide, and has a conductivity type. A p-type body layer 3 (p-type semiconductor layer 3) which is p-type, an n-type source contact layer 4 which is made of silicon carbide and has an n-type conductivity, and a silicon carbide and has a p-type conductivity. A contact region 5, a gate insulating film 8, a gate electrode 9, an interlayer insulating film 10, a source electrode 12, a source wiring electrode 13, a drain electrode 14, and a back surface protective electrode 15 are provided.

  As shown in FIG. 5, a plurality of (four in FIG. 5) mesa structures are formed on the main surface of substrate 1 by partially removing the silicon carbide layer. Specifically, the top surface and bottom surface of the mesa structure are hexagonal, and the side walls thereof are inclined with respect to the main surface of the substrate 1. Between adjacent mesa structures, a groove 6 having a side surface 20 with inclined side walls of the mesa structure is formed.

  In the semiconductor device shown in FIGS. 5 and 6, substrate 1 is made of silicon carbide having a crystal type of hexagonal crystal. The breakdown voltage holding layer 2 is formed on one main surface of the substrate 1. A p-type body layer 3 is formed on the breakdown voltage holding layer 2. An n-type source contact layer 4 is formed on the p-type body layer 3. A p-type contact region 5 is formed so as to be surrounded by the n-type source contact layer 4. By partially removing n-type source contact layer 4, p-type body layer 3 and breakdown voltage holding layer 2, a mesa structure surrounded by trench 6 is formed. The side wall of the groove 6 (the side wall of the mesa structure) is an end surface that is inclined with respect to the main surface of the substrate 1. The planar shape of the convex part surrounded by the inclined end face (the convex part having a mesa structure in which the source electrode 12 is formed on the upper surface) is hexagonal as shown in FIG.

  A gate insulating film 8 is formed on the side wall and bottom wall of the trench 6. This gate insulating film 8 extends to the upper surface of the n-type source contact layer 4. A gate electrode 9 is formed on the gate insulating film 8 so as to fill the inside of the trench 6 (that is, so as to fill a space between adjacent mesa structures). The upper surface of the gate electrode 9 has substantially the same height as the upper surface of the portion located on the upper surface of the n-type source contact layer 4 in the gate insulating film 8.

  An interlayer insulating film 10 is formed so as to cover a portion of gate insulating film 8 that extends to the upper surface of n-type source contact layer 4 and gate electrode 9. By removing the interlayer insulating film 10 and a part of the gate insulating film 8, an opening 11 is formed so as to expose a part of the n-type source contact layer 4 and the p-type contact region 5. A source electrode 12 is formed so as to fill the inside of the opening 11 and to be in contact with a part of the p-type contact region 5 and the n-type source contact layer 4. Source wiring electrode 13 is formed to be in contact with the upper surface of source electrode 12 and to extend on the upper surface of interlayer insulating film 10. A drain electrode 14 is formed on the back surface of the substrate 1 opposite to the main surface on which the breakdown voltage holding layer 2 is formed. The drain electrode 14 is an ohmic electrode. In this drain electrode 14, a back surface protection electrode 15 is formed on the surface opposite to the surface facing the substrate 1.

  In the semiconductor device shown in FIGS. 5 and 6, the side wall of trench 6 (side wall of the mesa structure) is inclined, and the side wall has a hexagonal crystal type of silicon carbide constituting breakdown voltage holding layer 2 and the like. Is substantially the {0-33-8} plane. Specifically, with respect to the crystal plane constituting the side wall, the off angle with respect to the {0-33-8} plane in the <1-100> direction is −3 ° or more and 3 ° or less, more preferably −1 ° or more. The surface is 1 ° or less. As can be seen from FIG. 6, these so-called semipolar side walls can be used as a channel region which is an active region and an ion implantation region of a semiconductor device. Since these side walls are stable crystal planes, when the side walls are used for the channel region, higher channel mobility is obtained than when other crystal planes (for example, (0001) plane) are used for the channel region. In addition, the leakage current can be sufficiently reduced and a high breakdown voltage can be obtained.

  Next, the operation of the semiconductor device shown in FIGS. 5 and 6 will be briefly described. Referring to FIG. 6, in a state where a voltage equal to or lower than a threshold is applied to gate electrode 9, that is, in an off state, a reverse bias is applied between p type body layer 3 and breakdown voltage holding layer 2 having a conductivity type of n type. It becomes a non-conductive state. On the other hand, when a positive voltage is applied to the gate electrode 9, an inversion layer is formed in the channel region in the vicinity of the region in contact with the gate insulating film 8 in the p-type body layer 3. As a result, the n-type source contact layer 4 and the breakdown voltage holding layer 2 are electrically connected. As a result, a current flows between the source electrode 12 and the drain electrode 14.

  Next, a method for manufacturing the semiconductor device shown in FIGS. 5 and 6 according to the present invention will be described with reference to FIGS.

First, referring to FIG. 7, an epitaxial layer of silicon carbide having n type conductivity is formed on the main surface of substrate 1 made of silicon carbide. The epitaxial layer becomes the breakdown voltage holding layer 2. Epitaxial growth for forming the breakdown voltage holding layer 2 is a CVD using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. It can be implemented by law. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as an n-type impurity. The concentration of the n-type impurity in the breakdown voltage holding layer 2 can be, for example, 5 × 10 ¹³ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less.

  Next, p-type body layer 3 and n-type source contact layer 4 are formed by implanting ions into the upper surface layer of breakdown voltage holding layer 2. In ion implantation for forming p-type body layer 3, an impurity having a p-type conductivity such as aluminum (Al) is implanted. At this time, the depth of the region where the p-type body layer 3 is formed can be adjusted by adjusting the acceleration energy of the implanted ions.

  Next, an n-type source contact layer 4 is formed by ion-implanting impurities of n-type conductivity into the breakdown voltage holding layer 2 in which the p-type body layer 3 is formed. For example, phosphorus or the like can be used as the n-type impurity. In this way, the structure shown in FIG. 8 is obtained.

  Next, as shown in FIG. 9, a mask layer 17 is formed on the upper surface of the n-type source contact layer 4. As mask layer 17, for example, an insulating film such as a silicon oxide film can be used. As a method for forming the mask layer 17, for example, the following steps can be used. That is, a silicon oxide film is formed on the upper surface of the n-type source contact layer 4 using a CVD method or the like. Then, a resist film (not shown) having a predetermined opening pattern is formed on the silicon oxide film by using a photolithography method. Using this resist film as a mask, the silicon oxide film is removed by etching. Thereafter, the resist film is removed. As a result, a mask layer 17 having an opening pattern is formed in a region where the groove 16 shown in FIG. 9 is to be formed.

Then, using this mask layer 17 as a mask, parts of n-type source contact layer 4, p-type body layer 3 and breakdown voltage holding layer 2 are removed by etching. As an etching method, for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. By such etching, grooves 16 whose side walls are substantially perpendicular to the main surface of the substrate 1 can be formed in regions where the grooves 6 in FIG. 6 are to be formed. In this way, the structure shown in FIG. 9 is obtained.

  Next, a thermal etching process for exposing a predetermined crystal plane in the breakdown voltage holding layer 2, the p-type body layer 3 and the n-type source contact layer 4 is performed. Specifically, the side wall of the groove 16 shown in FIG. 9 is etched (thermal etching) using a mixed gas of oxygen gas and chlorine gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. to 1000 ° C. Thereby, as shown in FIG. 10, the groove | channel 6 which has the side surface 20 inclined with respect to the main surface of the board | substrate 1 can be formed.

Here, with respect to the conditions of the thermal etching step, 0.5 ≦ x ≦ 2 in a reaction formula expressed as SiC + mO ₂ + nCl ₂ → SiCl _x + COy (where m, n, x, and y are positive numbers). The main reaction proceeds when the x and y conditions of 0.0 and 1.0 ≦ y ≦ 2.0 are satisfied, and the reaction (thermal etching) proceeds most when the conditions of x = 4 and y = 2. Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. When the heat treatment temperature is set to 700 ° C. or more and 1000 ° C. or less as described above, the etching rate of SiC is, for example, about 70 μm / hr. Further, in this case, if silicon oxide (SiO ₂ ) is used as the mask layer 17, the selectivity ratio of SiC to SiO ₂ can be extremely increased, so that the mask layer 17 made of SiO ₂ is substantially not etched during SiC etching. Not etched.

  The crystal plane appearing on the side surface 20 is substantially a {0-33-8} plane. That is, in the etching under the conditions described above, the {0-33-8} plane that is the crystal plane with the slowest etching rate is self-formed as the side face 20 of the groove 6. As a result, a structure as shown in FIG. 10 is obtained. The crystal plane constituting the side surface 20 may be a {01-1-4} plane. Further, when the crystal type of silicon carbide constituting the breakdown voltage holding layer 2 or the like is a cubic crystal, the crystal plane constituting the side surface 20 may be a {111} plane.

  Next, the mask layer 17 is removed by an arbitrary method such as etching. Thereafter, a resist film (not shown) having a predetermined pattern is formed by photolithography so as to extend from the inside of the trench 6 to the upper surface of the n-type source contact layer 4. As the resist film, a resist film having an opening pattern formed at the bottom of the groove 6 and a part of the upper surface of the n-type source contact layer 4 is used. Then, by using this resist film as a mask, an impurity having a conductivity type of p-type is ion-implanted to form an electric field relaxation region 7 at the bottom of the trench 6, and a conductive region in a partial region of the n-type source contact layer 4. A contact region 5 having a p-type is formed. Thereafter, the resist film is removed. As a result, a structure as shown in FIGS. 11 and 12 is obtained. As can be seen from FIG. 12, the planar shape of the groove 6 is a mesh shape in which the planar shape of the unit cell (the annular groove 6 surrounding one mesa structure) is a hexagonal shape. In addition, the p-type contact region 5 is disposed substantially at the center of the upper surface of the mesa structure as shown in FIG. The planar shape of the p-type contact region 5 is the same as the outer peripheral shape of the upper surface of the mesa structure, and is a hexagonal shape.

  Then, an activation annealing step for activating the impurities implanted by the above-described ion implantation is performed. In this activation annealing step, annealing is performed without forming a cap layer on the surface of the epitaxial layer made of silicon carbide (for example, on the side wall of the mesa structure). Here, the inventors do not deteriorate the surface properties of the above-described {0-33-8} plane even if the activation annealing treatment is performed without forming a protective film such as a cap layer on the surface. It was found that sufficient surface smoothness can be maintained. For this reason, the activation annealing step is directly performed by omitting the step of forming the protective film (cap layer) before the activation annealing treatment, which has been conventionally considered necessary. Note that the activation annealing step may be performed after the cap layer described above is formed. In addition, for example, the activation annealing treatment may be performed by providing a cap layer only on the upper surfaces of the n-type source contact layer 4 and the p-type contact region 5.

  Next, as shown in FIG. 13, gate insulating film 8 is formed so as to extend from the inside of trench 6 to the upper surfaces of n-type source contact layer 4 and p-type contact region 5. As gate insulating film 8, for example, an oxide film (silicon oxide film) obtained by thermally oxidizing an epitaxial layer made of silicon carbide can be used. In this way, the structure shown in FIG. 13 is obtained.

  Next, as shown in FIG. 14, a gate electrode 9 is formed on the gate insulating film 8 so as to fill the inside of the trench 6. As a method for forming the gate electrode 9, for example, the following method can be used. First, on the gate insulating film 8, a conductor film to be a gate electrode extending to the inside of the trench 6 and the region on the p-type contact region 5 is formed by sputtering or the like. As a material of the conductor film, any material such as metal can be used as long as it is a conductive material. Thereafter, the portion of the conductor film formed in a region other than the inside of the trench 6 is removed by using any method such as etch back or CMP. As a result, a conductor film filling the inside of the groove 6 remains, and the gate electrode 9 is constituted by the conductor film. In this way, the structure shown in FIG. 14 is obtained.

  Next, interlayer insulating film 10 (see FIG. 15) is formed so as to cover the upper surface of gate electrode 9 and the upper surface of gate insulating film 8 exposed on p-type contact region 5. As the interlayer insulating film, any material can be used as long as it is an insulating material. Then, a resist film having a pattern is formed on the interlayer insulating film 10 by using a photolithography method. In the resist film (not shown), an opening pattern is formed in a region located on the p-type contact region 5.

  Then, using this resist film as a mask, the interlayer insulating film 10 and the gate insulating film 8 are partially removed by etching. As a result, an opening 11 (see FIG. 15) is formed in the interlayer insulating film 10 and the gate insulating film 8. At the bottom of the opening 11, the p-type contact region 5 and the n-type source contact layer 4 are partially exposed. Thereafter, a conductor film to be the source electrode 12 (see FIG. 15) is formed so as to fill the inside of the opening 11 and cover the upper surface of the resist film described above. Thereafter, by removing the resist film using a chemical solution or the like, the portion of the conductor film formed on the resist film is simultaneously removed (list off). As a result, the source electrode 12 can be formed by the conductor film filled in the opening 11. The source electrode 12 is an ohmic electrode in ohmic contact with the p-type contact region 5 and the n-type source contact layer 4.

  Further, the drain electrode 14 (see FIG. 15) is formed on the back surface side of the substrate 1 (the surface side opposite to the main surface on which the breakdown voltage holding layer 2 is formed). As the drain electrode 14, any material can be used as long as it can make ohmic contact with the substrate 1. In this way, the structure shown in FIG. 15 is obtained.

  Thereafter, the source wiring electrode 13 (see FIG. 6) that contacts the upper surface of the source electrode 12 and extends on the upper surface of the interlayer insulating film 10, and the back surface protection electrode 15 ( 6) is formed by using an arbitrary method such as a sputtering method. As a result, the semiconductor device shown in FIGS. 5 and 6 can be obtained.

  Next, with reference to FIGS. 16 and 17, a modification of the method for manufacturing the semiconductor device according to the present invention shown in FIGS. 5 and 6 will be described.

  In a modification of the method for manufacturing a semiconductor device according to the present invention, first, the steps shown in FIGS. Thereafter, the mask layer 17 shown in FIG. 9 is removed. Next, a Si coating 21 (see FIG. 16) made of silicon is formed so as to extend from the inside of the trench 16 to the upper surface of the n-type source contact layer 4. By performing the heat treatment in this state, silicon carbide is reconfigured in the region in contact with the Si coating 21 on the inner peripheral surface of the groove 16 and the upper surface of the n-type source contact layer 4. In this way, as shown in FIG. 16, silicon carbide reconstructed layer 22 is formed such that the side wall of the groove has a predetermined crystal plane ({0-33-8} plane). As a result, a structure as shown in FIG. 16 is obtained.

Thereafter, the remaining Si film 21 is removed. As a method for removing the Si coating 21, for example, etching using a mixed gas such as HNO ₃ and HF can be used. Thereafter, the surface layer of the reconstruction layer 22 described above is removed by etching. ICP-RIE can be used as the etching for removing the reconstruction layer 22. As a result, as shown in FIG. 17, a groove 6 having an inclined side surface can be formed.

  Thereafter, the semiconductor device shown in FIGS. 5 and 6 can be obtained by carrying out the steps shown in FIGS. 11 to 15 described above.

(Embodiment 3)
With reference to FIG. 18, a semiconductor device according to a third embodiment of the present invention will be described.

  Referring to FIG. 18, the semiconductor device according to the present invention is an IGBT which is a vertical device using a groove whose side surface is inclined. The semiconductor device shown in FIG. 18 includes a p-type substrate 31 made of silicon carbide, p-type epitaxial layer 36 as a buffer layer made of silicon carbide, p-type conductivity, and silicon carbide. The n-type epitaxial layer 32 as a breakdown voltage holding layer whose conductivity type is n-type, and silicon carbide, and the p-type semiconductor layer 33 corresponding to the well region whose conductivity type is p-type, and silicon carbide, and conductive N-type source contact layer 34 corresponding to the emitter region of n-type, contact region 35 made of silicon carbide and p-type of conductivity, gate insulating film 8, gate electrode 9, and interlayer insulating film 10, a source electrode 12 corresponding to the emitter electrode, a source wiring electrode 13, a drain electrode 14 corresponding to the collector electrode, and a back surface protective electrode 15.

  The p-type epitaxial layer 36 that is a buffer layer is formed on one main surface of the substrate 31. An n-type epitaxial layer 32 is formed on the p-type epitaxial layer 36. A p-type semiconductor layer 33 is formed on the n-type epitaxial layer 32. An n-type source contact layer 34 is formed on the p-type semiconductor layer 33. A p-type contact region 35 is formed so as to be surrounded by the n-type source contact layer 34. The trench 6 is formed by partially removing the n-type source contact layer 34, the p-type semiconductor layer 33, and the n-type epitaxial layer 32. The side wall of the groove 6 is an end face inclined with respect to the main surface of the substrate 31. The planar shape of the convex portion surrounded by the inclined end surface (the mesa structure as the convex shape portion in which the source electrode 12 is formed on the upper surface) is a hexagon as in the semiconductor device shown in FIG. Yes.

  A gate insulating film 8 is formed on the side wall and bottom wall of the trench 6. This gate insulating film 8 extends to the upper surface of the n-type source contact layer 34. A gate electrode 9 is formed on the gate insulating film 8 so as to fill the trench 6. The upper surface of the gate electrode 9 has substantially the same height as the upper surface of the portion located on the upper surface of the n-type source contact layer 34 in the gate insulating film 8.

  Interlayer insulating film 10 is formed so as to cover a portion of gate insulating film 8 that extends to the upper surface of n-type source contact layer 34 and gate electrode 9. By removing the interlayer insulating film 10 and a part of the gate insulating film 8, the opening 11 is formed so as to expose a part of the n-type source contact layer 34 and the p-type contact region 35. Source electrode 12 is formed so as to fill the inside of opening 11 and to be in contact with part of p-type contact region 35 and n-type source contact layer 34. Source wiring electrode 13 is formed to be in contact with the upper surface of source electrode 12 and to extend on the upper surface of interlayer insulating film 10.

  On the back surface of the substrate 1 opposite to the main surface on which the breakdown voltage holding layer 2 is formed, the drain electrode 14 and the back surface protection electrode 15 are formed as in the semiconductor device shown in FIGS. ing.

  In the semiconductor device shown in FIG. 18 as well, the side walls of trench 6 are inclined, and the side walls are formed of silicon carbide crystals constituting n-type epitaxial layer 32 and the like, as in the semiconductor devices shown in FIGS. When the mold is hexagonal, it is substantially the {0-33-8} plane. In this case, the same effect as that of the semiconductor device shown in FIG. 5 can be obtained. In the semiconductor devices according to the second and third embodiments, the side wall may be substantially a {01-1-4} plane. In addition, when the crystal type of silicon carbide constituting the n-type epitaxial layer 32 or the like is a cubic crystal, the inclined sidewall of the groove 6 may be substantially a {111} plane.

  Next, the operation of the semiconductor device shown in FIG. 18 will be briefly described. Referring to FIG. 18, when a negative voltage is applied to gate electrode 9 and the negative voltage exceeds a threshold value, it opposes groove 6 of p-type semiconductor layer 33 in contact with gate insulating film 8 on the side of gate electrode 9. An inversion layer is formed in the end region (channel region), and the n-type source contact layer 34 as the emitter region and the n-type epitaxial layer 32 as the breakdown voltage holding layer are electrically connected. As a result, holes are injected from the n-type source contact layer 34 that is the emitter region into the n-type epitaxial layer 32 that is the breakdown voltage holding layer, and correspondingly, the substrate 31 passes through the p-type epitaxial layer 36 that is the buffer layer. Thus, electrons are supplied to the n-type epitaxial layer 32. As a result, the IGBT is turned on, conductivity modulation occurs in the n-type epitaxial layer 32, and a current flows in a state where the resistance between the source electrode 12 as the emitter electrode and the drain electrode 14 as the collector electrode is lowered. On the other hand, when the negative voltage applied to the gate electrode 9 is equal to or lower than the threshold value, an inversion layer is not formed in the channel region, so that a reverse bias state is present between the n-type epitaxial layer 32 and the p-type semiconductor layer 33. Maintained. As a result, the IGBT is turned off and no current flows.

  With reference to FIGS. 19 to 26, a method of manufacturing the semiconductor device according to the third embodiment of the present invention will be described.

First, referring to FIG. 19, p type epitaxial layer 36 of conductivity type p type and silicon carbide is formed on the main surface of substrate 31 made of silicon carbide. Then, an n-type epitaxial layer 32 of silicon carbide whose conductivity type is n-type is formed on p-type epitaxial layer 36. The n-type epitaxial layer 32 becomes a breakdown voltage holding layer. In the epitaxial growth for forming the p-type epitaxial layer 36 and the n-type epitaxial layer 32, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) is used as a source gas, and a hydrogen gas ( It can be carried out by a CVD method using H ₂ ). At this time, it is preferable to introduce, for example, aluminum (Al) or the like as an impurity having a p-type conductivity, and to introduce, for example, nitrogen (N) or phosphorus (P) as an n-type impurity.

  Next, ion implantation is performed on the upper surface layer of the n-type epitaxial layer 32 to form the p-type semiconductor layer 33 and the n-type source contact layer 34. In the ion implantation for forming the p-type semiconductor layer 33, for example, a p-type impurity such as aluminum (Al) is ion-implanted. At this time, the depth of the region where the p-type semiconductor layer 33 is formed can be adjusted by adjusting the acceleration energy of the implanted ions.

  Next, an n-type source contact layer 34 is formed by ion implantation of an n-type impurity of conductivity type into the n-type epitaxial layer 32 in which the p-type semiconductor layer 33 is formed. For example, phosphorus or the like can be used as the n-type impurity. In this way, the structure shown in FIG. 20 is obtained.

  Next, as shown in FIG. 19, a mask layer 17 is formed on the upper surface of the n-type source contact layer 34. As mask layer 17, for example, an insulating film such as a silicon oxide film can be used. As a method for forming the mask layer 17, a method similar to the method for manufacturing the mask layer 17 described in FIG. 9 can be used. As a result, a mask layer 17 having an opening pattern is formed in a region where the groove 16 shown in FIG. 21 is to be formed.

  Then, part of n-type source contact layer 34, p-type semiconductor layer 33, and n-type epitaxial layer 32 is removed by etching using mask layer 17 as a mask. As the etching method and the like, the same method as that shown in FIG. 9 can be used. In this way, the structure shown in FIG. 21 is obtained.

  Next, a thermal etching process for exposing a predetermined crystal plane in the n-type epitaxial layer 32, the p-type semiconductor layer 33, and the n-type source contact layer 34 is performed. The conditions for this thermal etching step can be the same as the conditions for the thermal etching step described with reference to FIG. As a result, the groove 6 having the side surface 20 inclined with respect to the main surface of the substrate 31 can be formed as shown in FIG. The plane orientation of the crystal plane appearing on the side surface 20 is {0-33-8}. In this way, a structure as shown in FIG. 22 is obtained.

  Next, the mask layer 17 is removed by an arbitrary method such as etching. Thereafter, similarly to the process shown in FIG. 11, a resist film (not shown) having a predetermined pattern is applied to the photo resist so as to extend from the inside of the trench 6 to the upper surface of the n-type source contact layer 34. It is formed using a lithography method. As the resist film, a resist film having an opening pattern formed at the bottom of the groove 6 and a part of the upper surface of the n-type source contact layer 34 is used. Then, using this resist film as a mask, an impurity of p-type conductivity is ion-implanted to form an electric field relaxation region 7 at the bottom of the trench 6 and conductive in a partial region of the n-type source contact layer 34. A contact region 35 of p type is formed. Thereafter, the resist film is removed. As a result, a structure as shown in FIG. 23 is obtained.

  Then, an activation annealing step for activating the impurities implanted by the above-described ion implantation is performed. In this activation annealing step, a protective film is particularly formed on the surface of the epitaxial layer made of silicon carbide (specifically, on the side surface 20 of the groove 6) as in the case of the first and second embodiments of the present invention already described. Annealing is performed without forming a (cap layer). Further, for example, the activation annealing process may be performed by providing a cap layer only on the upper surfaces of the n-type source contact layer 34 and the p-type contact region 35.

  Next, as shown in FIG. 24, gate insulating film 8 is formed so as to extend from the inside of trench 6 to the upper surfaces of n-type source contact layer 4 and p-type contact region 5. The material and forming method of the gate insulating film 8 are the same as the material and forming method of the gate insulating film 8 in FIG. In this way, the structure shown in FIG. 24 is obtained.

  Next, as shown in FIG. 25, a gate electrode 9 is formed on the gate insulating film 8 so as to fill the inside of the trench 6. As a formation method of the gate electrode 9, a formation method similar to the formation method of the gate electrode 9 shown in FIG. 14 can be used. In this way, the structure shown in FIG. 25 is obtained.

  Next, interlayer insulating film 10 (see FIG. 26) is formed so as to cover the upper surface of gate electrode 9 and the upper surface of gate insulating film 8 exposed on p-type contact region 35. Any material can be used for the interlayer insulating film 10 as long as it is an insulating material. Similarly to the process shown in FIG. 15, an opening 11 (see FIG. 26) is formed in the interlayer insulating film 10 and the gate insulating film 8. The method for forming the opening 11 is the same as the method for forming the opening in FIG. At the bottom of the opening 11, the p-type contact region 35 and the n-type source contact layer 34 are partially exposed.

  Thereafter, the source electrode 12 is formed from the conductive film filled in the opening 11 by using a method similar to the method described in FIG. The source electrode 12 is an ohmic electrode in ohmic contact with the p-type contact region 35 and the n-type source contact layer 34.

  Further, the drain electrode 14 (see FIG. 26) is formed on the back surface side of the substrate 31 (surface side opposite to the main surface on which the n-type epitaxial layer 32 is formed). As the drain electrode 14, any material can be used as long as it can make ohmic contact with the substrate 1. In this way, the structure shown in FIG. 26 is obtained.

  Thereafter, the upper surface of the source electrode 12 is contacted, and the source wiring electrode 13 (see FIG. 15) extending on the upper surface of the interlayer insulating film 10 and the back surface protection electrode 15 (formed on the surface of the drain electrode 14) 15) are formed by using an arbitrary method such as a sputtering method. As a result, the semiconductor device shown in FIG. 18 can be obtained.

(Reference example)
A reference example of the semiconductor device according to the present invention will be described with reference to FIG.

Referring to FIG. 27, a semiconductor device which is a reference example of the present invention is a PiN diode, and includes a substrate 1 made of silicon carbide, an n-type conductivity, and a concentration of conductive impurities in substrate 1. an epitaxial layer 42, n ^{- -} have a low conductivity impurity concentration, n having a ridge structure on the surface is formed in the ridge structure 44 formed on the surface of the epitaxial layer 42, n ^- is connected to the epitaxial layer 42 The p ⁺ semiconductor layer 43 and a guard ring 45 formed around the ridge structure 44 are provided. Substrate 1 is made of silicon carbide and has n type conductivity. N ⁻ epitaxial layer 42 is formed on the main surface of substrate 1. On the surface of n ⁻ epitaxial layer 42, a ridge structure 44 in which side surface 20 is inclined with respect to the main surface of substrate 1 is formed. In the layer including the upper surface of the ridge structure 44, a p ⁺ semiconductor layer 43 having a p-type conductivity is formed. A guard ring 45 having a p-type conductivity region is formed so as to surround the ridge structure 44. The guard ring 45 is formed in an annular shape so as to surround the ridge structure 44. The side surface 20 of the ridge structure 44 is constituted by a specific crystal plane (for example, {0-33-8} plane). That is, the ridge structure 44 is composed of six planes equivalent to the specific crystal plane ({0-33-8} plane) described above. For this reason, the planar shape of the upper surface and the bottom of the ridge structure 44 is a hexagonal shape.

  Also in the semiconductor device having such a structure, the side surface 20 of the ridge structure 44 is a stable crystal plane similarly to the side surface 20 of the groove 6 shown in FIG. Therefore, the leakage current from the side surface 20 can be sufficiently reduced.

Next, a method for manufacturing the semiconductor device shown in FIG. 27 will be described. As a method for manufacturing the semiconductor device shown in FIG. 27, first, a substrate 1 made of silicon carbide is prepared. As the substrate 1, for example, a substrate made of silicon carbide having a crystal type of hexagonal crystal is used. An n ⁻ epitaxial layer 42 is formed on the main surface of substrate 1 using an epitaxial growth method. A p-type semiconductor layer to be the p ⁺ semiconductor layer 43 is formed by ion-implanting a p-type impurity into the surface layer of the n ⁻ epitaxial layer 42.

Thereafter, an island-shaped mask pattern made of a silicon oxide film is formed in a region to be the ridge structure 44 (see FIG. 27). The planar shape of the mask pattern may be a hexagonal shape, for example, but may be any other shape (for example, a circle or a square). Then, with this mask pattern formed, p ⁺ semiconductor layer 43 and n ⁻ epitaxial layer 42 are partially removed by etching. As a result, a convex portion to be the ridge structure 44 is formed under the mask pattern.

Then, by performing the thermal etching process in the same manner as the process shown in FIG. 9 in the second embodiment of the present invention described above, the side surface of the convex portion is removed by etching, and the inclined side surface 20 shown in FIG. obtain. Thereafter, the mask pattern is removed. Further, a resist film having a predetermined pattern is formed so as to cover the whole. In the resist film, an opening pattern is formed in a region to be the guard ring 45. Using this resist film as a mask, a p-type impurity is implanted into n ⁻ epitaxial layer 42 to form guard ring 45. Thereafter, the resist film is removed. Then, activation annealing is performed after the ion implantation for forming the guard ring 45. In the activation annealing, heat treatment may be performed without forming a cap layer covering at least the side surface 20. Good. As a result, the semiconductor device shown in FIG. 27 can be obtained.

Next, a modification of the semiconductor device shown in FIG. 27 will be described with reference to FIG.
The semiconductor device shown in FIG. 28 is a semiconductor device according to the present invention, and basically has the same structure as that of the semiconductor device shown in FIG. 27, but is replaced with a JTE instead of the guard ring 45 (see FIG. 27). (Junction Termination Extension) Region 46 is different. The JTE region 46 is a region having a p-type conductivity. Such a JTE region 46 can also be formed by performing ion implantation and activation annealing in the same manner as the guard ring 45 shown in FIG. Similarly to the method for manufacturing the semiconductor device shown in FIG. 27, in the method for manufacturing the semiconductor device shown in FIG. 28, at least the side surface in the activation annealing process after ion implantation for forming the JTE region 46 is performed. The activation annealing process is performed without forming a cap layer that covers 20. Even in this case, since the side surface 20 is constituted by a stable crystal plane (for example, {0-33-8} plane), the problem that the surface of the side surface 20 is roughened by the active annealing does not occur. Further, the guard ring 45 and / or the JET structure shown in FIGS. 27 and 28 can be applied to the first to third embodiments of the semiconductor device according to the present invention described above.

  Although there is a part which overlaps with embodiment mentioned above, the characteristic structure of this invention is enumerated below.

In the method of manufacturing a semiconductor device according to the present invention, a silicon carbide layer (withstand voltage holding layer 2, n-type epitaxial layer 32, and n ⁻ epitaxial layer 42) having a surface substantially including a {0-33-8} plane is provided. A step of preparing a substrate formed on the main surface (step (S10) and step (S20) in FIG. 2), a step of injecting conductive impurities into the silicon carbide layer (step (S30) in FIG. 2), And a step of performing a heat treatment for activating the implanted conductive impurities (step (S40) in FIG. 2). In the heat treatment step (S40), the surface of the silicon carbide layer is exposed to the atmospheric gas for heat treatment.

  In this way, it is not necessary to form a protective film (cap layer) during activation annealing after ion implantation for the silicon carbide layer, so that the manufacturing process of the semiconductor device can be simplified as compared with the case of forming the protective film. Therefore, the manufacturing cost of the semiconductor device can be reduced.

  In the semiconductor device manufacturing method, the step of preparing the substrate is a step of forming an end surface (side surface 20) inclined with respect to the main surface of the substrate in the silicon carbide layer (FIGS. 9, 10, 16, and 17). Steps shown) may be included. The side surface 20 may be a surface substantially including a {0-33-8} plane. Here, it is relatively difficult to epitaxially grow the silicon carbide layer with the {0-33-8} plane as the main surface. On the other hand, with respect to the silicon carbide layer formed on substrate 1, the silicon carbide layer is epitaxially grown so that the plane orientation of the main surface has an off angle of a minute angle (for example, about 8 °) with respect to the (0001) plane. It is well established technically to some extent. And if the end surface which becomes said {0-33-8} surface is formed by processing such a silicon carbide layer, said {0-33-8} surface will be surface (side 20) comparatively easily. ) Can be obtained.

A semiconductor device according to the present invention includes a substrate 1 having a main surface and a silicon carbide layer formed on the main surface of the substrate 1 and including an end surface (side surface 20) inclined with respect to the main surface (FIG. 6). The breakdown voltage holding layer 2, the semiconductor layer 3, the n-type source contact layer 4, and the p-type contact region 5, or the n-type epitaxial layer 32, the p-type semiconductor layer 33, the n-type source contact layer 34, and the p-type in FIG. Contact region 35 and n ⁻ epitaxial layer 42). The side surface 20 substantially includes a {0-33-8} plane. The side surface 20 includes a conductive impurity implantation region (ion implantation region). The side surface 20 may include a channel region. A plurality of the side surfaces 20 may be formed. Each of the plurality of side surfaces 20 may be configured by a surface substantially equivalent to the {0-33-8} plane.

  In this way, since the activation annealing can be performed without forming a protective film in the activation annealing after ion implantation is performed on the side surface 20, a semiconductor device with reduced manufacturing costs can be obtained. Can do.

  Further, since the side surface 20 of the silicon carbide layer is substantially the above-described {0-33-8} plane, the side surface 20 which is a so-called semipolar plane is used as an ion implantation region, so that the ion The implantation region can be used as a channel region (active region) of the semiconductor device, for example. Here, the side surface 20 is a stable crystal surface, and high channel mobility can be obtained. Therefore, when the side surface 20 is used for a channel region configured by ion implantation, a higher quality that exhibits higher channel mobility than when other crystal planes (for example, (0001) plane) are used for the channel region. A semiconductor device can be realized. Further, since the side surface 20 substantially includes the {0-33-8} plane, a step (step difference) is formed on the side surface 20 as in the case where the crystal orientation of the end surface is deviated from the {0-33-8} plane. ) Exist in large numbers, and the occurrence of problems such as a decrease in channel mobility can be suppressed.

  In the semiconductor device, the silicon carbide layer may include a plurality of mesa structures in which the side surface 20 forms a side surface on the main surface located on the opposite side to the surface facing the substrate 1. A surface portion (bottom portion of groove 6) of the silicon carbide layer located between the plurality of mesa structures and continuous with side surface 20 may be substantially a {000-1} plane. Here, the surface portion is substantially a {000-1} plane when the crystal plane constituting the surface portion is the {000-1} plane and the crystal constituting the surface portion. It means that the surface is a surface having an off angle of -3 ° or more and 3 ° or less with respect to the {000-1} surface in the <1-100> direction. The off-angle is preferably −1 ° or more and 11 ° or less, and the crystal plane constituting the surface portion is more preferably a {000-1} plane.

  In this case, since the surface portion between the mesa structures is also a stable {000-1} plane (so-called just surface), the cap layer that protects the surface portion during the heat treatment such as the activation annealing described above. Even without forming, the surface portion and the upper surface of the mesa structure are hardly roughened by the heat treatment. Therefore, the step of forming a cap layer on the surface portion can be omitted for heat treatment such as activation annealing.

  In the semiconductor device, the planar shape of the upper surface continuous with the side surface 20 in the plurality of mesa structures may be hexagonal as shown in FIG. 5 and FIG. 12, and the plurality of mesa structures include at least three mesa structures. You may go out. The plurality of mesa structures may be arranged such that an equilateral triangle is formed by a line segment connecting the centers when viewed in plan. In this case, since the mesa structure can be arranged most densely, more mesa structures can be formed on one substrate 1 and 31. For this reason, as many semiconductor devices as possible using the mesa structure can be formed from one substrate 1, 31.

  In the semiconductor device, the upper surface of the mesa structure shown in FIGS. 5 and 12 or the like may be substantially a {000-1} plane. In this case, since the upper surface of the mesa structure is also a stable {000-1} plane (so-called just plane), the cap layer that protects the upper surface of the mesa structure during the heat treatment such as the activation annealing described above. Even without forming, the upper surface of the mesa structure is hardly roughened by the heat treatment. Therefore, the step of forming a cap layer on the upper surface of the mesa structure for heat treatment such as activation annealing can be omitted.

  In the semiconductor device or the method for manufacturing a semiconductor device, the surface roughness of the side surface 20 that is the surface of the silicon carbide layer after the heat treatment step is a root mean square roughness (Rq: old RMS) defined in JIS B0601. It may be 10 nm or less. In this case, it is possible to suppress the occurrence of defects due to the surface roughness of the side surface 20.

  As shown in FIGS. 6 and 18, the semiconductor device may include a source electrode 12 formed on the upper surface of the mesa structure and a gate electrode 9 formed between the plurality of mesa structures. . In this case, since the source electrode 12 and the gate electrode 9 are disposed at positions that are relatively easy to form, it is possible to suppress the manufacturing process of the semiconductor device from becoming complicated.

  The semiconductor device may further include an electric field relaxation region 7 formed between a plurality of mesa structures. In this case, the electric field relaxation region 7 exists when the drain electrode 14 is formed on the back side of the substrates 1 and 31 (the back side opposite to the main surface where silicon carbide is formed on the substrates 1 and 31). Thus, the breakdown voltage between the electrode (for example, the gate electrode 9) and the drain electrode 14 between the mesa structures can be increased.

  A method for manufacturing a semiconductor device according to the present invention includes a step of preparing substrates 1 and 31 having a silicon carbide layer formed on the main surface shown in FIGS. 8 and 20, and FIGS. 7 and 8 or FIG. As shown in FIG. 22, in the silicon carbide layer, a step of forming an end surface (side surface 20) inclined with respect to the main surfaces of the substrates 1, 31 and a step of forming an insulating film (gate insulating film 8) on the side surface 20. And a step of forming a gate electrode 9 on the gate insulating film 8. In the step of forming the end surface, the end surface (side surface 20) is formed so as to substantially include the {0-33-8} surface. In this way, the semiconductor device according to the present invention can be easily manufactured.

  In the semiconductor device manufacturing method, in the step of forming the end surface, a plurality of end surfaces (side surfaces 20) form side surfaces on the main surface of the silicon carbide layer located on the opposite side of the surface facing the substrates 1 and 31. A mesa structure may be formed. In this case, since the side surface 20 of the mesa structure substantially includes the {0-33-8} plane, a MOSFET, an IGBT, or the like using the side surface 20 as a channel region can be easily formed. The semiconductor device manufacturing method may further include a step of forming the source electrode 12 on the upper surface of the mesa structure as shown in FIGS.

  In the semiconductor device manufacturing method, in the step of forming the end face, a mesa structure in which the planar shape of the upper surface is a hexagon may be formed as shown in FIG. In this case, the side surface 20 of the mesa structure can be substantially constituted only by the {0-33-8} plane. For this reason, the integration degree of the semiconductor device can be improved by using all of the outer peripheral side surface 20 of the mesa structure as a channel region.

  In the semiconductor device manufacturing method, the step of forming the end face includes the step of forming the mask layer 17 as shown in FIGS. 9 and 21, and the mesa structure as shown in FIGS. 9 and 10 or FIGS. Forming the step. In the step of forming mask layer 17, a plurality of mask layers 17 having a hexagonal planar shape may be formed on the main surface of the silicon carbide layer. In the step of forming a mesa structure, the mask layer 17 may be used as a mask to form a mesa structure having a hexagonal planar shape on the upper surface. In this case, the position of the mesa structure to be formed (that is, the position of the side surface 20) can be controlled by the pattern position of the mask layer 17. For this reason, the freedom degree of the layout of the semiconductor device formed can be raised.

  In the manufacturing method of the semiconductor device, the step of forming the end face includes the step of forming the mask layer 17 and the recess (the groove 16 in FIGS. 9 and 21 as shown in FIGS. 9 and 10 or FIGS. 21 and 22). ) And a step of forming the mesa structure shown in FIGS. 10 and 22 may be included. In the step of forming mask layer 17, a plurality of mask layers 17 having a hexagonal planar shape may be formed on the main surface of the silicon carbide layer at intervals from each other. In the step of forming the recess (groove 16), by using the mask layer 17 as a mask, the silicon carbide layer exposed between the plurality of mask layers 17 is partially removed to form the main surface of the silicon carbide layer. A recess (groove 16) may be formed. In the step of forming the mesa structure, the mesa structure in which the planar shape of the upper surface is a hexagon may be formed by partially removing the side wall of the groove 16. In this case, the time for partially removing the side wall of groove 16 (for example, thermal etching) to form the mesa structure can be made shorter than when groove 16 is not previously formed in the silicon carbide layer using mask layer 17 as a mask.

  In the method for manufacturing a semiconductor device, in the step of forming the end face, the side face 20 of the mesa structure may be formed in a self-forming manner. Specifically, by performing etching under predetermined conditions on the silicon carbide layer (for example, thermal etching with a mixed gas of oxygen and chlorine as a reaction gas and a heating temperature of 700 ° C. or more and 1200 ° C. or less), The {0-33-8} plane which is the slowest etching speed in the etching may be self-formed. Alternatively, as shown in FIG. 16, after a surface to be the side surface 20 is formed by normal etching, a silicon film (Si film 21) is formed on the surface, and silicon carbide is present in a state where the Si film 21 exists. By heating the layer, the SiC reconstruction layer 22 may be formed on the surface, and as a result, the {0-33-8} surface may be formed. In this case, the {0-33-8} plane can be stably formed on the side surface 20.

  In the semiconductor device manufacturing method, in the step of forming the end face, the side face 20 of the mesa structure and the surface portion of the silicon carbide layer (the bottom wall of the groove 6) located between the plurality of mesa structures and continuing to the side face 20 May be formed in a self-forming manner. Specifically, using a method such as thermal etching or formation of the SiC reconstruction layer 22, the {0-33-8} plane is exposed as the side surface 20 of the mesa structure, and the bottom wall of the groove 6 is exposed. A predetermined crystal plane (for example, (0001) plane or (000-1) plane) may be exposed. In this case, a predetermined crystal plane ({0-33-8} plane) can be stably formed on the side wall 20 and also on the bottom wall of the groove 6.

From a different point of view, the semiconductor device includes, as shown in FIGS. 3, 5, 6, 18, 18, 27, 28, etc., substrates 1, 31 having a main surface, and a silicon carbide layer ( The breakdown voltage holding layer 2, the semiconductor layer 3, the n-type source contact layer 4, and the p-type contact region 5 in FIG. 6, or the n-type epitaxial layer 32, the p-type semiconductor layer 33, the n-type source contact layer 34 in FIG. p-type contact region 35, or n ⁻ epitaxial layer 42 and p ⁺ semiconductor layer 43) of FIGS. 27 and 28. The silicon carbide layer is formed on the main surfaces of substrates 1 and 31. The silicon carbide layer includes a side surface 20 that is an end surface inclined with respect to the main surface. Side surface 20 substantially includes one of a {0-33-8} plane and a {01-1-4} plane when the silicon carbide layer has a hexagonal crystal type, and the silicon carbide layer has a crystal type In the case where is a cubic crystal, it substantially includes the {111} plane.

  In this case, the side surface 20 formed in the silicon carbide layer is substantially any of the {0-33-8} plane, the {01-1-4} plane, and the {111} plane. These side surfaces 20 that are so-called semipolar surfaces can be used as active regions of the semiconductor device (for example, channel regions and conductive regions formed by implantation of conductive impurities). And since these side surfaces 20 are stable crystal planes, when the side surfaces 20 are used as active regions such as channel regions, than when other crystal surfaces (for example, (0001) planes) are used as channel regions, The leakage current can be sufficiently reduced and a high breakdown voltage can be obtained.

  In the semiconductor device, the side surface 20 may include an active region as shown in FIGS. In the semiconductor device, specifically, the active region includes a channel region. In this case, the characteristics such as the reduction of the leakage current and the high breakdown voltage described above can be obtained with certainty.

In the semiconductor device, the silicon carbide layer includes a mesa structure in which the side surface 20 constitutes a side surface as shown in FIGS. 27 and 28 on the main surface located on the opposite side of the surface facing the substrates 1 and 31. You may go out. A PN junction (a junction between the n ⁻ epitaxial layer 42 and the p ⁺ semiconductor layer 43 in FIGS. 27 and 28) may be formed in the mesa structure. In this case, since the side surface 20 which is the side wall of the mesa structure is the above-described crystal plane, the leakage current from the side surface 20 can be reduced.

  In the semiconductor device, as shown in FIG. 28, at least a part of the side surface 20 may constitute a termination structure (JTE region 46). In this case, the leakage current in the termination structure formed on the side surface 20 can be reduced and the breakdown voltage of the termination structure can be increased.

  Further, the method of manufacturing a semiconductor device according to the present invention includes a step of preparing substrates 1 and 31 on which a silicon carbide layer is formed as shown in FIGS. 8 and 20, and FIGS. 10 and 11 or FIGS. As shown in FIG. 22, the step of forming an end surface (side surface 20) inclined with respect to the main surface of the silicon carbide layer, and the end surface (side surface 20) as shown in FIG. 11 to FIG. 17 or FIG. And a step of forming a structure included in the semiconductor device. In the step of forming the end face (side face 20), the silicon carbide layer is heated while contacting the reaction gas containing oxygen and chlorine with the silicon carbide layer, and the main surface of the silicon carbide layer is partially removed by etching. Thus, an end surface (side surface 20) inclined with respect to the main surface of the silicon carbide layer (for example, the upper surfaces of n-type source contact layers 4 and 34 in FIGS. 10 and 22) is formed. The end face (side face 20) substantially includes either the {0-33-8} face or the {01-14} face when the silicon carbide layer has a hexagonal crystal type. When the mold is a cubic crystal, it substantially includes {111} planes. In this case, the semiconductor device according to the present invention can be easily manufactured.

  Further, the substrate processing method according to the present invention includes a step of preparing substrates 1 and 31 on which a silicon carbide layer is formed as shown in FIGS. 8 and 20, and FIGS. 9 and 10 or FIGS. 21 and 22. And a step of forming an end face (side face 20) inclined with respect to the main surface of the silicon carbide layer. In the step of forming the end face (side face 20), the silicon carbide layer is heated while contacting the reaction gas containing oxygen and chlorine with the silicon carbide layer, and the main surface of the silicon carbide layer is partially removed by etching. By doing so, the side surface 20 inclined with respect to the main surface of the silicon carbide layer is formed. Side surface 20 substantially includes one of a {0-33-8} plane and a {01-14} plane when the crystal type of the silicon carbide layer is hexagonal, and the crystal type of the silicon carbide layer is cubic. In the case of a crystal, it substantially includes the {111} plane. In this case, it is possible to easily obtain a substrate on which the silicon carbide layer having the side surface 20 including the crystal face described above is formed.

  Prior to the step of forming the end face (side surface 20), the semiconductor device manufacturing method or the substrate processing method includes a mask having a pattern on the main surface of the silicon carbide layer, as shown in FIGS. A step of forming the layer 17 may be further provided. In the step of forming the end surface (side surface 20), etching may be performed using the mask layer 17 as a mask. In this case, the position of the side surface 20 to be formed can be controlled by the pattern position of the mask layer 17. For this reason, the freedom degree of the layout of the semiconductor device formed can be raised.

  Further, a part of the silicon carbide layer is previously removed by the etching using the mask layer 17 as a mask, and then, as shown in FIGS. 10 and 22, while contacting with a reactive gas containing oxygen and chlorine. It is preferable that the main surface of the silicon carbide layer is partially removed by etching (thermal etching) by heating the silicon carbide layer. In this case, the time required for the thermal etching for forming the side surface 20 can be shortened compared with the case where the etching using the mask layer 17 as a mask is not performed in advance.

  In the reaction gas used in the step of forming the end face (side surface 20) in the semiconductor device manufacturing method or the substrate processing method, the ratio of the oxygen flow rate to the chlorine flow rate is 0.25 to 2.0. May be. In this case, the end face including the {0-33-8} plane, the {01-1-4} plane, or the {111} plane can be reliably formed.

  In the semiconductor device manufacturing method or the substrate processing method, the temperature for heating the silicon carbide layer in the step of forming the end surface (side surface 20) may be 700 ° C. or higher and 1200 ° C. or lower. Moreover, the minimum of the said temperature to heat can be 800 degreeC, More preferably, it can be 900 degreeC. Further, the upper limit of the heating temperature is more preferably 1100 ° C, and even more preferably 1000 ° C. In this case, the etching rate in the thermal etching process for forming the end face including the {0-33-8} plane, the {01-1-4} plane, or the {111} plane can be set to a sufficiently practical value. Therefore, the processing time of the process can be sufficiently shortened.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is particularly advantageously applied to a semiconductor device using a silicon carbide layer.

1,31 substrate, 2 breakdown voltage holding layer, 3 p-type body layer (p-type semiconductor layer), 4,34 n-type source contact layer, 5,35 contact region, 6,16 groove, 7 electric field relaxation region, 8 gate insulation Film, 9 gate electrode, 10 interlayer insulating film, 11 opening, 12 source electrode, 13 source wiring electrode, 14, 112 drain electrode, 15 back surface protection electrode, 17 mask layer, 20 side surface, 21 Si coating, 22 SiC reconstruction Layer, 32 n type epitaxial layer, 33 p type semiconductor layer, 36 p type epitaxial layer, 42 n ⁻ epitaxial layer, 43 p ⁺ semiconductor layer, 44 ridge structure, 45 guard ring, 46 JTE region, 101 semiconductor device.

Claims (7)

Providing a substrate on which a silicon carbide layer having a surface substantially including a {0-33-8} plane is formed on a main surface;
Injecting conductive impurities into the silicon carbide layer;
Performing a heat treatment for activating the implanted conductive impurities,
The method of manufacturing a semiconductor device, wherein in the step of performing the heat treatment, the surface of the silicon carbide layer is exposed to an atmosphere gas for performing the heat treatment. The step of preparing the substrate includes the step of forming an end surface inclined with respect to the main surface of the substrate in the silicon carbide layer,
The method of manufacturing a semiconductor device according to claim 1, wherein the end surface is a surface substantially including the {0-33-8} plane. A substrate having a main surface;
A silicon carbide layer formed on the main surface of the substrate and including an end face inclined with respect to the main surface;
The end face substantially comprises a {0-33-8} plane;
The end face includes a semiconductor impurity implantation region. The silicon carbide layer includes a plurality of mesa structures in which the end surface constitutes a side surface in a main surface located on the opposite side to the surface facing the substrate,
4. The semiconductor device according to claim 3, wherein the surface portion of the silicon carbide layer located between the plurality of mesa structures and continuing to the side surface is substantially a {000-1} plane. In the plurality of mesa structures, the planar shape of the upper surface connected to the side surface is a hexagon,
The plurality of mesa structures includes at least three mesa structures;
The semiconductor device according to claim 4, wherein the plurality of mesa structures are arranged such that equilateral triangles are formed by line segments connecting the centers when viewed in plan.   The semiconductor device according to claim 5, wherein the upper surface of the mesa structure is substantially a {000-1} plane.   7. The semiconductor device according to claim 3, wherein the surface roughness of the end face is 10 nm or less in terms of root mean square roughness.

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