JPH10107263A - Insulated gate silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device having excellent characteristics which suppresses influences on carrier mobility of a minute step of a crystal surface caused by a substrate provided with an off-angle for epitaxial growth. SOLUTION: By use of (0001) face as a main face, on a surface layer of a p-epitaxial layer 2 grown on a p<+> -substrate 1 of silicon carbide having an off-angle in a direction of <11-20>, an n-source region 3, and an n-drain region 4 are formed so that main parts of a boundary of an n-source region 3 and a boundary of an n-drain region 4 are made substantially parallel in the direction of an off-angle. A gate electrode layer 6 is provided on the p-epitaxial layer 2 between both regions via a gate insulation film 5, and MOSFET having a source electrode 7, a drain electrode 8 and a gate electrode 9 is formed. Probability that carriers of a current flowing in a channel 10 induced just under the gate electrode layer 6 cross the minute step of a surface layer of the p- epitaxial layer 2 is reduced, and mobility is improved, so that a silicon carbide semiconductor device low in on-resistance is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon carbide semiconductor device using silicon carbide.

[0002]

2. Description of the Related Art The performance of semiconductor devices using silicon has been improved by various structural measures in order to achieve higher frequencies and higher power. However, the semiconductor device is approaching its limit, and a semiconductor device using a new material is being sought in order to achieve higher performance. Power devices that control large power are often required to operate under severe environments such as high temperatures and radiation, but are difficult to achieve with existing semiconductor materials such as silicon and gallium arsenide.

[0003] In response to the above requirements, silicon carbide can easily control p and n valence electrons by adding impurities, and has a wide band gap (2.93 eV or 3.26 eV depending on the crystal system). Therefore, it is expected as a material for next-generation power devices that can operate at high capacity, high frequency, and high temperature. Specifically, since it has a breakdown electric field one order higher than silicon, it has
Because it has twice the electron saturation drift velocity, it can be applied to high frequency devices, and because it has about three times the thermal conductivity of silicon, it can be applied to high power devices and devices for high temperature environments.

[0004] Despite these excellent features, the crystal growth is difficult, and its development has not been advanced. However, progress in crystal growth technology in recent years has been remarkable, and wafers having a diameter of 30 mm and having a (0001) plane of 6H-SiC or 4H-SiC as a main surface are now commercially available. These are alpha-phase SiC in a form in which a zinc blende type and a wurtzite type are stacked.
Also, in the epitaxial growth technology, 6H-Si
C and 4H-SiC crystals were made into substrates and slightly inclined by oblique polishing (called off-angle).
By growing on a substrate, the substrate temperature is conventionally 18
High quality epitaxial layers, which could not be obtained unless the temperature was about 00 ° C., can now be obtained at a low temperature of about 1500 ° C. With the progress of these crystals, trial production of devices such as a high breakdown voltage junction diode, a Schottky diode, or a MOS field effect transistor (hereinafter, referred to as a MOSFET) is rapidly progressing.

[0005]

As described above, in the epitaxial growth of SiC, it is known that a high-quality epitaxial layer can be grown only on a substrate having an off-angle. In the epitaxial growth of SiC, the off-angle of the (0001) plane crystal is generally set at an angle of about 5 degrees in the <11-20> direction.

The obliquely polished surface is shifted from the crystal plane by an off angle, and the epitaxial growth proceeds while maintaining the crystal plane while adding atoms to minute steps between the crystal planes. Therefore, a step-like minute step in the direction perpendicular to the oblique polishing direction remains on the surface of the epitaxial layer. When the surface of the epitaxial layer is oxidized, the minute step remains at the interface between the oxide film and the epitaxial layer.

Therefore, the surface of the epitaxial layer has a good crystal quality and looks like a mirror surface, but steps are formed on the surface in steps of atomic order. This step can be observed by, for example, a scanning tunneling microscope. If the off-angle direction is a <11-20> direction, the step is formed parallel to a <1-100> direction perpendicular to that direction. I understand.

[0008] When a current flows just below the surface or interface where such steps exist, it causes a decrease in mobility. In fact, in silicon MOSFETs, it is known that microscopic irregularities at the interface between the dielectric and the semiconductor affect the mobility of the channel. In SiC,
Until now, devices that control the current by applying an electric field to the gates such as MOSFETs and forming a channel have been fabricated, but these devices have been fabricated without considering the direction of the current flowing through the channel. ing. For this reason, the mobility of the MOS interface n-channel is 1
When using an epitaxial of × 10 ¹⁶ cm ^-3 , 70
The highest value was cm ² / Vs, which was considerably low by analogy with the mobility of the SiC bulk.

In view of the above problems, an object of the present invention is to suppress the influence of microsteps on the crystal surface on carrier mobility caused by a substrate having an off-angle for epitaxial growth, and to provide a silicon carbide semiconductor having excellent characteristics. It is to provide a device.

[0010]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a gate electrode layer having an epitaxial layer formed on a silicon carbide substrate having an off-angle, and a gate electrode layer provided on the epitaxial layer via a gate insulating film. In the insulated gate silicon carbide semiconductor device having a channel formation region immediately below the gate electrode layer, the direction of the current flowing through the channel and the direction of the off-angle are substantially perpendicular to each other.

For example, a lateral MIS in which a semiconductor device has a second conductivity type source region and a second conductivity type drain region selectively formed on a surface layer of a first conductivity type epitaxial layer.
FET, where the main portion of the boundary of the second conductivity type source region and the boundary of the second conductivity type drain region on the epitaxial layer surface immediately below the gate electrode layer are substantially parallel to the off-angle direction, A lateral type device having a second conductivity type collector region formed in a surface layer of a first conductivity type epitaxial layer, a second conductivity type base region, and a first conductivity type emitter region formed in the second conductivity type base region. An IGBT in which the boundary of the second conductivity type base region and the boundary of the first conductivity type emitter region are substantially parallel to the off-angle direction on the surface of the epitaxial layer immediately below the gate electrode layer; Second conductivity type base region formed in the surface layer of one conductivity type epitaxial layer and first conductivity type formed in the second conductivity type base region A vertical conductivity type MISFET having a source region and a second conductivity type drain region formed on the back surface side of the substrate, wherein a boundary of the second conductivity type base region and the first conductivity type are formed on the epitaxial layer surface immediately below the gate electrode layer. When the boundary of the mold source region is substantially parallel to the off-angle direction, or when the semiconductor device is a second conductivity type base region formed on the surface layer of the first conductivity type epitaxial layer and the second conductivity type base region A vertical I type having a first conductivity type emitter region formed in the region and a second conductivity type collector region formed on the back side of the substrate
This is the case where the boundary of the second conductivity type base region and the boundary of the first conductivity type emitter region are substantially parallel to the off-angle direction on the surface of the epitaxial layer immediately below the gate electrode layer.

As described in the preceding paragraph, when the surface of the epitaxial layer or the surface of the epitaxial layer is oxidized, a step-like minute step in the direction perpendicular to the oblique polishing direction is formed at the interface between the oxide film and the epitaxial layer. Remains. When a current flows in a direction crossing such a step, the mobility of carriers is reduced. If the path through which the current flows is made parallel to the step as in the present invention, the probability of crossing the step is reduced, and a decrease in mobility can be prevented.

If the off-angle direction is [11-20], the direction of the boundary of the impurity region immediately below the gate electrode layer is [1-100], and the off-angle direction is [1-10].
0], the direction of the boundary of the impurity region immediately below the gate electrode layer is preferably set to [11-20]. In that way, the probability of the current crossing a small step is reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on embodiments by taking a lateral MOSFET which is a kind of MISFET as an example. The following is a description of a substrate polished obliquely in the <11-20> direction. [Embodiment 1] FIG. 1A is a sectional view of a lateral MOSFET according to a first embodiment of the present invention.

The p ^{+ of} 6H—SiC whose (0001) plane is polished obliquely in the <11-20> direction at an off angle of 3.5 degrees
On a substrate 1, ap epitaxial layer 2 doped with aluminum (Al) at 3 × 10 ¹⁶ cm ⁻³ is formed by epitaxial growth. The n source region 3 and the n drain region 4 are selectively ion-implanted with nitrogen into the surface layer of the p epitaxial layer 2 and then heat-treated.
Are formed. n source region 3 and n drain region 4
A gate electrode layer 6 of polycrystalline silicon is provided on a surface of p epitaxial layer 2 sandwiched between the gate electrode layer 6 and a silicon oxide gate insulating film 5. Further, a source electrode 7, a drain electrode 8, and a gate electrode 9 of, for example, Ni are provided in contact with the n source region 3, the n drain region 4, and the gate electrode layer 6, respectively.

The operation of the MOSFET is performed as follows. By applying a positive voltage equal to or higher than a certain value (threshold voltage) to the gate electrode 9, a channel 10 which is an inversion layer is formed on the surface layer of the p epitaxial layer 2 immediately below the gate electrode layer 6, and the channel 10 , A current flows between the source electrode 7 and the drain electrode 8.
When the voltage application to the gate electrode 9 is stopped, the channel 10
Disappears and the current stops flowing.

FIG. 1B is a plan view showing the arrangement of each diffusion layer on the surface of the silicon carbide. The vertical direction of the figure is <
The <11-20> direction and the left-right direction are <1-100> directions. As can be seen in the figure, the surface layer of the (0001) crystal having an off-angle in the <11-20> direction has n
The source region 3 and the n-drain region 4 are formed to face each other in the <1-100> direction, that is, the direction perpendicular to the off-angle direction. The arrangement of the gate electrode layer 6 is indicated by a dotted line. With this arrangement, when a voltage is applied to the gate electrode 9, the current flows through the channel 10 <
1-100> direction.

FIG. 1C is an enlarged view of a section taken along the line AA 'in FIG. 1B, and is measured by an atomic force microscope. Flat surfaces are atomically smooth (0001)
Plane. As described above, it is found that there are many microsteps having a height of 2 to 5 nm at intervals of 10 to 50 nm in the <11-20> direction, but there are almost no steps in the <1-100> direction perpendicular thereto. Was. That is, since there are no steps along the direction in which the current flows, the carrier mobility is not affected.

When an n-channel lateral MOSFET is actually formed on a p × ³ epitaxial layer 2 of 3 × 10 ¹⁶ cm ⁻³ ,
In the structure of FIG. 1, a mobility of 80 cm ² / Vs was obtained. [Comparative Example] FIG. 2A shows a lateral MOSF as a comparative example.
It is sectional drawing of ET.

Also in this example, a p epitaxial layer 2 doped with 3 × 10 ¹⁶ cm ^{−3 of} Al formed by epitaxial growth is formed on ap ⁺ substrate 1 polished obliquely in the <11-20> direction. A lateral MOSFET is formed on the surface layer of the epitaxial layer 2 as in FIG. FIG. 2B is a plan view showing the arrangement of each diffusion layer on the surface of the silicon carbide. The vertical direction of the figure is <1
The <-100> direction and the left-right direction are <11-20> directions. As can be seen in the figure, the surface layer of the (0001) crystal having an off-angle in the <11-20> direction has n
The source region 3 and the n-drain region 4 are formed so as to face each other in the <11-20> direction, that is, the direction parallel to the off-angle direction. The arrangement of the gate electrode layer 6 is indicated by a dotted line. With this arrangement, when a voltage is applied to the gate electrode 9, the current flows through the channel 10 <
11-20> direction.

FIG. 2C is an enlarged view of a cross section taken along line BB ′ of FIG. 2B. In this case, there are countless steps along the direction in which the current flows.
In this case, the mobility between the source and the drain is low because the current flows while vertically crossing the micro steps at the interface of the gate oxide film. Horizontal MOS of this comparative example
In an FET, the channel mobility is 20 cm ² / V
s.

By the arrangement of the n source region 3 and the n drain region 4 in the first embodiment, the probability that the current flowing between the source electrode 7 and the drain electrode 8 crosses the micro steps immediately below the gate oxide film 5 is greatly reduced. It is considered that the mobility is higher than that of the comparative example. The comparative example corresponds to the case where the probability of the carrier crossing a small step is the maximum. When the on-resistance of the MOSFET of the 600 V class is estimated based on the difference in the mobility, the MOSFET of the comparative example shows 1 × 10 ⁻² Ωc
m ² , whereas the MOSFET of the first embodiment is 2 ×
The loss is greatly reduced to 10 ⁻³ Ωcm ² . Further, the characteristics of the manufactured semiconductor device are made uniform. [Embodiment 2] In the case of a power device, a vertical structure is often used because a large amount of current flows. FIG. 3 (a)
FIG. 3 is a sectional view of a vertical MOSFET according to a second embodiment of the present invention.

In this example, an n ⁺ substrate 11 is used, on which an n epitaxial layer 12 is deposited. Then, p base region 14 is formed in the surface layer of n epitaxial layer 12, and source electrode 7 is connected to p base region 1.
4 on the n-source region 3 selectively formed on the surface layer.
The drain electrodes 8 are provided on the back surface of the n-substrate 11, respectively, and a current flows in a direction perpendicular to the main surface of the substrate. 5 is a gate insulating film, 6 is a gate electrode layer, and 9 is a gate electrode.

FIG. 3B is a plan view showing the arrangement of diffusion regions on the surface of silicon carbide. The vertical direction of the figure is <11
The <-20> direction and the left-right direction are <1-100> directions.
As shown in the figure, the surface layer of the (0001) crystal having an off-angle in the <11-20> direction has a surface exposed portion of the n source region 3 and the n epitaxial layer 12 of <1-1.
00> direction, that is, at right angles to the off-angle direction.

With such an arrangement, when a voltage is applied to the gate electrode 9, the current in the channel 10 is <1-1.
The channel 10 flows in the <00> direction, but the channel 10 is also formed on the very surface layer of the p-epitaxial layer 2, so that the influence of the surface is inevitable. With the arrangement as in the second embodiment, the current flowing between the source electrode 7 and the drain electrode 8 is:
The probability of crossing a minute step immediately below the gate oxide film 5 is greatly reduced, and the mobility is increased. Third Embodiment FIG. 4A is a cross-sectional view of a horizontal IGBT according to a third embodiment of the present invention.

An n epitaxial layer 12 doped with 3 × 10 ¹⁶ cm ⁻³ of N is formed on an n ⁺ substrate 11 polished obliquely in the <11-20> direction at an off angle of 3.5 degrees by an epitaxial growth method. I have. By selectively ion-implanting Al and N into the surface layer of the n-epitaxial layer 12 and thereafter performing heat treatment, the p-collector region 1 is formed.
3. A p base region 14 and an n emitter region 15 are formed in the p base region 14. On the surface of p base region 14 sandwiched between n emitter region 15 and n epitaxial layer 12, gate electrode layer 6 of polycrystalline silicon is provided via gate insulating film 5 of silicon oxide.
Further, an emitter electrode 16, a collector electrode 17, and a gate electrode 9, for example, of Ni are provided in contact with the n emitter region 15, the p collector region 13, and the gate electrode layer 6, respectively.

The operation of the IGBT is performed as follows. By applying a positive voltage equal to or higher than a certain value (threshold voltage) to the gate electrode 9, an inversion layer (channel) is generated in the surface layer of the p base region 14 immediately below the gate electrode layer 6, and through the channel, Electrons are injected from emitter electrode 17 into n epitaxial layer 12. This electron is
The base current of the pnp transistor composed of the p collector region 13, the n epitaxial layer 12, and the p base region 14 is turned on, and the transistor is turned on, so that the emitter electrode 1
7. A current flows between the collector electrodes 16. Gate electrode 9
Is stopped, the supply of electrons from the n emitter region 15 stops, and the IGBT is turned off.

FIG. 4B is a plan view showing the arrangement of diffusion regions on the surface of silicon carbide. The vertical direction of the figure is <11
The <-20> direction and the left-right direction are <1-100> directions.
Also in this case, the n emitter region 15 and the exposed surface of the n epitaxial layer 12 are formed to face each other in the <1-100> direction, that is, the direction perpendicular to the off-angle direction. Therefore, electrons flow through the channel 10 <1-1.
There are almost no minute steps in the 00> direction, and the carrier mobility is not affected.

Similarly, the same effect can be obtained in a vertical IGBT formed on an epitaxial wafer having an n epitaxial layer stacked on ap ⁺ substrate.

[0030]

As described above, according to the present invention, there is provided an insulated gate type carbonization having a gate electrode layer provided on a epitaxial layer grown on a silicon carbide substrate having an off angle via a gate insulating film. In the silicon semiconductor device, by arranging the impurity regions such that the direction of the current flowing through the channel formed immediately below the gate electrode layer and the direction of the off-angle are substantially perpendicular to each other,
By reducing the probability that carriers cross minute steps and devising them to flow in parallel with the steps, it is possible to improve mobility and to provide a device with less loss compared to the prior art.

For example, as described in the embodiment, the MO
It is clear that the on-resistance is reduced to 1/5 as compared with the worst arrangement example in the case of the SFET, and the effect of reducing the loss of the silicon carbide semiconductor device is great. Further, it greatly contributes to uniformity of characteristics in the manufactured semiconductor device.

[Brief description of the drawings]

FIG. 1A shows a lateral MOSFET according to a first embodiment of the present invention.
T is a cross-sectional view, (b) is a plan view showing the arrangement of diffusion regions on the surface of silicon carbide, and (c) is an enlarged view of a cross-section along the line AA '.

2A is a cross-sectional view of a lateral MOSFET of a comparative example, FIG. 2B is a plan view showing an arrangement of diffusion regions on the surface of silicon carbide, and FIG. 2C is an enlarged cross-section taken along line BB ′. Figure

FIG. 3A is a vertical MOSFET according to a second embodiment of the present invention;
T is a cross-sectional view, and (b) is a plan view showing the arrangement of diffusion regions on the silicon carbide surface.

FIG. 4A is a cross-sectional view of a horizontal IGBT according to a third embodiment of the present invention, and FIG. 4B is a plan view showing the arrangement of diffusion regions on the surface of silicon carbide.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 p ⁺ substrate 2 p epitaxial layer 3 n source region 4 n drain region 5 gate insulating film 6 gate electrode layer 7 source electrode 8 drain electrode 9 gate electrode 10 channel 11 n ⁺ substrate 12 n epitaxial layer 13 p collector region 14 p base region 15 n emitter region 16 collector electrode 17 emitter electrode

Claims (7)

[Claims] An epitaxial layer is formed on a silicon carbide substrate having an off-angle, a gate electrode layer is provided on the epitaxial layer with a gate insulating film interposed therebetween, and a channel forming region is formed immediately below the gate electrode layer. An insulated gate silicon carbide semiconductor device, comprising: a direction of a current flowing through a channel and an off-angle direction are substantially perpendicular to each other. 2. A semiconductor device according to claim 1, wherein said semiconductor device is a lateral MISFET having a second conductivity type source region and a second conductivity type drain region selectively formed in a surface layer of said first conductivity type epitaxial layer. 2. The insulated gate type device according to claim 1, wherein a main portion of a boundary between the second conductivity type source region and a second conductivity type drain region on the surface of the epitaxial layer is substantially parallel to an off-angle direction. Silicon carbide semiconductor device. 3. A semiconductor device comprising: a second conductivity type collector region, a second conductivity type base region formed in a surface layer of a first conductivity type epitaxial layer, and a first conductivity type formed in the second conductivity type base region. Lateral IGBT having a semiconductor emitter region
The main part of the boundary of the second conductivity type base region and the boundary of the first conductivity type emitter region on the surface of the epitaxial layer immediately below the gate electrode layer is substantially parallel to the off-angle direction. The insulated gate silicon carbide semiconductor device according to claim 1. 4. A semiconductor device comprising: a second conductivity type base region formed in a surface layer of a first conductivity type epitaxial layer; a first conductivity type source region formed in the second conductivity type base region; Vertical MISFET having a second conductivity type drain region formed on the back side of the semiconductor device, and a main conductivity type boundary between the second conductivity type base region and the first conductivity type source region on the surface of the epitaxial layer immediately below the gate electrode layer. 2. The insulated gate silicon carbide semiconductor device according to claim 1, wherein the portion is substantially parallel to an off-angle direction. 5. A semiconductor device comprising: a second conductivity type base region formed in a surface layer of a first conductivity type epitaxial layer; a first conductivity type emitter region formed in the second conductivity type base region; Vertical IGBT having a second conductivity type collector region formed on the back surface side of the semiconductor device, and a main boundary of the second conductivity type base region and the first conductivity type emitter region on the surface of the epitaxial layer immediately below the gate electrode layer. 2. The insulated gate silicon carbide semiconductor device according to claim 1, wherein the portion is substantially parallel to an off-angle direction. 6. The direction of the off-angle is [11-20], and the direction of the main part of the boundary of the impurity region on the surface of the epitaxial layer immediately below the gate electrode layer is substantially [1-100].
The insulated gate silicon carbide semiconductor device according to any one of claims 1 to 5, wherein 7. The off-angle direction is [1-100], and the direction of the main part of the boundary of the impurity region on the surface of the epitaxial layer immediately below the gate electrode layer is substantially [11-20].
The insulated gate silicon carbide semiconductor device according to any one of claims 1 to 5, wherein