JPH09260650A - Silicon carbide trench fet and manufacture thereof - Google Patents

Silicon carbide trench fet and manufacture thereof

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Publication number
JPH09260650A
JPH09260650A JP8065745A JP6574596A JPH09260650A JP H09260650 A JPH09260650 A JP H09260650A JP 8065745 A JP8065745 A JP 8065745A JP 6574596 A JP6574596 A JP 6574596A JP H09260650 A JPH09260650 A JP H09260650A
Authority
JP
Japan
Prior art keywords
trench
silicon carbide
silicon
layer
conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8065745A
Other languages
Japanese (ja)
Inventor
Katsunori Ueno
勝典 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP8065745A priority Critical patent/JPH09260650A/en
Publication of JPH09260650A publication Critical patent/JPH09260650A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66053Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the on resistance of a silicon carbide (4H-SiC, 6H-SiC) trench FET(field effect transistor). SOLUTION: A SiC crystal with the face (such as the faces (1, -1, 0, 0), vertical to the face (0001) as its main face is used, the side surfaces of a trench 15 are formed so as to become roughly the face (0001), and a channel 20 is contrived so as to be able to be formed on the side of the face (000), specially the silicon face (0001) which is terminated by silicon atoms. An n-type emitter region 14 is formed only in the surface layer of a p-type base layer 13 on the side of the silicon face (0001) or the trench inner surface to oppose to the silicon face (0001) is shifted from the face (0001), the horizontal section of a gate electrode 17 is formed so as to turn into a triangle, and it is also possible to reduce the unit area of a cell. The film thickness of an oxide film on the silicon face (0001) and the film thickness of an oxide film on the carbon face (0001) have only to be formed in the same thickness by a thermal oxidation, an oxide film selective removal and a reoxidation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、高耐圧、大電流
を制御する電界効果トランジスタ(以下FETと略
す)、特に炭化ケイ素を用い、トレンチを有する炭化ケ
イ素トレンチFETに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter abbreviated as FET) for controlling a high breakdown voltage and a large current, and particularly to a silicon carbide trench FET having a trench using silicon carbide.

【0002】[0002]

【従来の技術】最近、電力用半導体素子として炭化ケイ
素(以下SiCと略す)を用いた縦型FETの試作が行
われている。SiCは最大電界強度がシリコンより一桁
大きいため、薄い結晶で高耐圧の半導体素子ができ、オ
ン電圧を低くできて、大電流密度の使用に適するからで
ある。
2. Description of the Related Art Recently, trial manufacture of a vertical FET using silicon carbide (hereinafter abbreviated as SiC) as a power semiconductor element has been carried out. Since the maximum electric field strength of SiC is an order of magnitude higher than that of silicon, a semiconductor element with a thin crystal and a high breakdown voltage can be formed, the on-voltage can be lowered, and it is suitable for use with a large current density.

【0003】縦型FETは、SiCの電力用デバイスへ
の適用を考える上で重要なデバイスである。その理由は
電圧駆動型デバイスであるため、素子の並列駆動が容易
であり、また駆動回路の簡素化が可能なこと、およびユ
ニポーラ素子であるため、高速スイッチングが可能なこ
となどによる。また、SiCにおいては、シリコンと異
なり深い不純物拡散が困難であるのに対して、エピタキ
シャル成長は比較的容易であるので、図7に示すような
トレンチ5をもつトレンチFETが一般的である。な
お、以下においてn、pを冠した層、領域等はそれぞれ
電子、正孔を多数キャリアとする層、領域を意味するも
のとする。
The vertical FET is an important device when considering application of SiC to a power device. The reason is that it is a voltage-driven device, so that it is easy to drive the elements in parallel, and the drive circuit can be simplified, and because it is a unipolar element, high-speed switching is possible. Further, unlike SiC, it is difficult to diffuse deep impurities in SiC, but epitaxial growth is relatively easy. Therefore, a trench FET having a trench 5 as shown in FIG. 7 is generally used. In the following, layers, regions, and the like bearing n and p are layers and regions in which electrons and holes serve as majority carriers, respectively.

【0004】図7は、従来試作されたSiCのトレンチ
FETの要部断面図である。図において、n+ ドレイン
層1のサブストレート上にサブストレートより不純物濃
度の低いnドリフト層2とp型のpベース層3とをエピ
タキシャル成長したSiC基板が用いられている。Si
Cでは、厚い層を熱拡散で形成することが困難である
が、エピタキシャル成長は比較的容易に行われる。pベ
ース層3の表面層に選択的に高濃度のnソース領域4が
形成され、そのnソース領域4の一部に表面からドリフ
ト層2に達する溝(以後トレンチと呼ぶ)5が形成され
ている。トレンチ5の内側にはゲート絶縁膜6を介して
ゲート電極7が設けられ、また、nソース領域4の表面
とpベース層3の表面露出部に共通に接触してソース電
極8が、n + ドレイン層1の裏面にドレイン電極9がそ
れぞれ設けられている。
FIG. 7 shows a conventionally manufactured SiC trench.
It is a principal part sectional drawing of FET. In the figure, n+drain
The impurity concentration on the substrate of layer 1 is higher than that of the substrate.
The n drift layer 2 and the p-type p base layer 3 having a low degree are epitaxially formed.
A SiC substrate that has been grown by a taxi is used. Si
In C, it is difficult to form a thick layer by thermal diffusion
However, epitaxial growth is relatively easy. p
The high concentration n source region 4 is selectively formed on the surface layer of the source layer 3.
Diffused from the surface to a part of the n source region 4 formed.
A trench (hereinafter referred to as a trench) 5 reaching the trench layer 2 is formed.
ing. Inside the trench 5 via the gate insulating film 6
A gate electrode 7 is provided and the surface of the n source region 4 is provided.
And the exposed surface of the p base layer 3 are commonly contacted, and
Pole 8 is n +A drain electrode 9 is formed on the back surface of the drain layer 1.
Each is provided.

【0005】このMOSFETの動作は、ドレイン電極
9とソース電極8との間に電圧を印加した状態で、ゲー
ト電極7にある値以上の正の電圧を加えると、ゲート電
極7の横のpベース層3の表面層にチャネル(反転層)
10が形成され、そのチャネル10を通じて、ソース電
極8からドレイン電極9へと電子電流が流れる。このよ
うにして、高耐圧を維持し、かつ大電流を制御するもの
である。SiCにおいては、ゲート絶縁膜6としてSi
Cを熱酸化してできる酸化ケイ素膜が使用できる。ただ
し、ゲート絶縁膜6は他の絶縁膜でもよい。なお、以下
酸化ケイ素膜を酸化膜と呼ぶ。
The operation of this MOSFET is such that when a positive voltage higher than a certain value is applied to the gate electrode 7 in a state where a voltage is applied between the drain electrode 9 and the source electrode 8, the p-base next to the gate electrode 7 is applied. Channel (inversion layer) in the surface layer of layer 3
10 is formed, and an electron current flows from the source electrode 8 to the drain electrode 9 through the channel 10. In this way, a high breakdown voltage is maintained and a large current is controlled. In SiC, Si is used as the gate insulating film 6.
A silicon oxide film formed by thermally oxidizing C can be used. However, the gate insulating film 6 may be another insulating film. Note that the silicon oxide film is hereinafter referred to as an oxide film.

【0006】これまでに報告されているSiCの縦型M
OSFETでは、用いられた単結晶は4H−SiCまた
は6H−SiCと呼ばれるものであった。これらは閃亜
鉛鉱型とウルツ鉱型とを積層した形のアルファ相SiC
で、単結晶ウェハの製造が可能であることによる。そし
て先にも述べたように、用いる結晶のnドリフト層2は
通常エピタキシャル成長法により形成されている。これ
は不純物濃度および厚さを正確に制御するためである。
更に、これらの単結晶の表面の結晶方位は、(000
1)面、或いはc面と呼ばれる方位であった。この方位
が使用される理由は、これまでのエピタキシャル成長技
術が、(0001)面について開発されてきたことによ
る。従って、炭化ケイ素トレンチFETのチャネルが形
成されるのは、ほぼ90度傾いた面、或いは大きく(0
001)面からはずれた面であったことが図から容易に
理解できる。
The vertical M of SiC that has been reported so far.
In OSFETs, the single crystals used were those called 4H-SiC or 6H-SiC. These are alpha-phase SiC in the form of stacking zinc blende type and wurtzite type
Therefore, it is possible to manufacture a single crystal wafer. As described above, the crystalline n drift layer 2 used is usually formed by an epitaxial growth method. This is to accurately control the impurity concentration and thickness.
Furthermore, the crystal orientation of the surface of these single crystals is (000
The orientation was called 1) plane or c-plane. The reason that this orientation is used is that the epitaxial growth techniques so far have been developed for the (0001) plane. Therefore, the channel of the silicon carbide trench FET is formed on a surface inclined by about 90 degrees or a large (0
It can be easily understood from the figure that the surface was deviated from the (001) surface.

【0007】[0007]

【発明が解決しようとする課題】以上の説明からわかる
ように、これまでの縦型FETをはじめとするSiC半
導体素子の試作は、電力用半導体素子の特性を重視した
ものではなく、利用できる結晶のみを考慮したものであ
った。図8は、SiCの縦型FETの耐圧とオン抵抗と
の関係を表した図であって、横軸にFETの耐圧、縦軸
にそのオン抵抗をとり、FETのチャネル(反転層)の
移動度をパラメータとしてプロットしたものである。こ
の図8から、SiCの縦型FETのオン抵抗は、FET
のチャネルの移動度によって大きく左右されることがわ
かる。
As can be seen from the above description, the trial manufacture of SiC semiconductor devices such as vertical FETs so far does not place importance on the characteristics of power semiconductor devices and can be used for crystals. It was only a consideration. FIG. 8 is a diagram showing the relationship between the breakdown voltage and the on-resistance of a vertical SiC FET, where the horizontal axis represents the breakdown voltage of the FET and the vertical axis represents the on-resistance, and the movement of the channel (inversion layer) of the FET is shown. It is plotted using degrees as a parameter. From this FIG. 8, the on-resistance of the SiC vertical FET is
It can be seen that the channel mobility greatly depends on the channel mobility.

【0008】これは縦型FETのオン抵抗に、チャネル
の抵抗が直列に入っているためである。特に、1000
V以下の領域では、ほとんどFETのチャネルによって
抵抗が占められている。この耐圧範囲は、パワーデバイ
スとしての利用が最も多い範囲であることから、特にこ
の領域でメリットがでることが期待される。すなわち、
SiC本来のメリットを引き出すためには、FETのチ
ャネルの移動度をどこまで大きくできるかが最も大きな
因子であることを示している。
This is because the resistance of the channel is in series with the ON resistance of the vertical FET. Especially 1000
In the region below V, the resistance is almost occupied by the channel of the FET. Since this withstand voltage range is the most used range as a power device, it is expected that there will be an advantage especially in this range. That is,
It has been shown that in order to bring out the original merits of SiC, the maximum factor is how much the channel mobility of the FET can be increased.

【0009】ところが、これまでの報告では、SiCの
縦型FETの移動度は、10cm2/Vs程度しか報告
されていない。一方では、(0001)面に平行にチャ
ネルが形成される横型のFETでは、すでに70cm2
/Vsが報告されている。この原因については、明らか
になっていないが、表面の結晶面の特性が特に重要な役
割をしていることは間違いない。
However, in the reports so far, the mobility of the SiC vertical FET is reported to be only about 10 cm 2 / Vs. On the other hand, in a lateral FET in which a channel is formed parallel to the (0001) plane, it is already 70 cm 2
/ Vs is reported. Although the cause of this has not been clarified, there is no doubt that the characteristics of the surface crystal plane play a particularly important role.

【0010】以上の問題に鑑みて本発明の目的は、チャ
ネルのできる結晶面を移動度の大きな結晶面とすること
によって、オン抵抗の小さな炭化ケイ素トレンチFET
を提供することにある。
In view of the above problems, an object of the present invention is to make a crystal plane in which a channel is formed into a crystal plane having a high mobility, so that a silicon carbide trench FET having a small on-resistance can be obtained.
Is to provide.

【0011】[0011]

【課題を解決するための手段】上記課題の解決のため本
発明は、アルファ相炭化ケイ素単結晶の第一導電型ドレ
イン層上に順に形成されたドレイン層より不純物濃度の
低い炭化ケイ素の第一導電型ドリフト層と炭化ケイ素の
第二導電型ベース層と、その第二導電型ベース層の表面
層の一部に形成された第一導電型ソース領域と、その第
一導電型ソース領域の表面から第一導電型ドリフト層に
達するトレンチとを有し、そのトレンチ内にゲート絶縁
膜を介して設けられたゲート電極と、第一導電型ソース
領域の表面に接して設けられたソース電極と、第一導電
型ドレイン層の裏面に設けられたドレイン電極とを備え
る炭化ケイ素トレンチFETにおいて、ゲート電極に電
圧を印加したときにゲート絶縁膜に沿った第二導電型ベ
ース層に(0001)面方向の反転層のチャネルが形成
されるものとする。
In order to solve the above problems, the present invention provides a first silicon carbide having a lower impurity concentration than a drain layer sequentially formed on a first conductivity type drain layer of an alpha phase silicon carbide single crystal. A second conductivity type base layer of a conductivity type drift layer and silicon carbide, a first conductivity type source region formed in a part of a surface layer of the second conductivity type base layer, and a surface of the first conductivity type source region From, having a trench reaching the first conductivity type drift layer, the gate electrode provided through the gate insulating film in the trench, the source electrode provided in contact with the surface of the first conductivity type source region, In a silicon carbide trench FET including a drain electrode provided on the back surface of a first conductivity type drain layer, when a voltage is applied to the gate electrode, a second conductivity type base layer along the gate insulating film is formed (000 ) Channels face the direction of the inversion layer is assumed to be formed.

【0012】特に、トレンチの側面がほぼ(0001)
面であるものがよい。図9、図10は、それぞれ(00
01)面に垂直および平行な反転層における移動度の電
子濃度依存性の図である。横軸は電子濃度、縦軸は移動
度で、いずれも対数表示になっている。低温での計算値
であるため、図8の値より大きな値になっているが、傾
向は利用できる。4H−SiC、6H−SiCの両結晶
ともに、(0001)面に平行な反転層の移動度が、
(0001)面に垂直な反転層の移動度より、約20〜
30%大きいことがわかる。
Particularly, the side surface of the trench is almost (0001).
What is a face is good. 9 and 10 show (00
It is a figure of the electron concentration dependence of the mobility in the inversion layer perpendicular | vertical and parallel to the (01) plane. The horizontal axis represents electron concentration and the vertical axis represents mobility, both of which are shown in logarithmic scale. Since it is a calculated value at a low temperature, the value is larger than the value in FIG. 8, but the tendency can be used. In both 4H-SiC and 6H-SiC crystals, the mobility of the inversion layer parallel to the (0001) plane is
From the mobility of the inversion layer perpendicular to the (0001) plane, about 20 to
You can see that it is 30% larger.

【0013】従って、トレンチの側面がほぼ(000
1)面であるようにすれば、キャリアの移動度の大きい
(0001)面をチャネルとして利用できる。そして、
炭化ケイ素サブストレートの主面がほぼ(0001)面
に垂直な結晶面、例えば、(1、0、−1、0)面や
(1、1、−2、0)面、あるいはそれらと等価な結晶
面であるものとする。
Therefore, the side surface of the trench is approximately (000
If the plane is the (1) plane, the (0001) plane having high carrier mobility can be used as a channel. And
A crystal plane in which a main surface of a silicon carbide substrate is substantially perpendicular to a (0001) plane, for example, a (1,0, -1,0) plane or a (1,1, -2,0) plane, or an equivalent thereof It shall be a crystal plane.

【0014】そのような低次の面の結晶は、切り出しや
すく、またそのような結晶を用いて、表面にほぼ垂直な
トレンチを形成すれば、(0001)面に平行なチャネ
ルができる。また、トレンチの(0001)シリコン面
側にのみ第一導電型ソース領域を有するものとする。
A crystal of such a low-order plane is easy to cut out, and if a trench almost vertical to the surface is formed using such a crystal, a channel parallel to the (0001) plane is formed. Further, it is assumed that the source region of the first conductivity type is provided only on the (0001) silicon surface side of the trench.

【0015】(0001)面をチャネル領域とした場
合、(0001)面にはシリコンで終端した(000
1)シリコン面と、これと180度の裏の炭素で終端し
た(000、−1)炭素面とが現れる。(0001)シ
リコン面は、(000、−1)炭素面よりもはるかに酸
化速度が小さい。逆にいうと、熱酸化した場合(00
0、−1)炭素面には、(0001)シリコン面よりず
っと厚い酸化膜が出来てしまう。従って、(0001)
シリコン面側に(適当な厚さの酸化膜を形成して)チャ
ネルを形成したとき、反対側の(000、−1)炭素面
側では酸化膜の厚さが厚すぎて、ほとんどFETのチャ
ネルは形成されないため、その領域は無効領域となる。
When the (0001) plane is used as a channel region, the (0001) plane is terminated with silicon (000).
1) A silicon surface and a (000, -1) carbon surface terminated by this and a 180 degree back carbon appear. The (0001) silicon face has a much lower oxidation rate than the (000, -1) carbon face. Conversely, when thermally oxidized (00
An oxide film much thicker than the (0001) silicon surface is formed on the (0, -1) carbon surface. Therefore, (0001)
When a channel is formed on the silicon surface side (by forming an oxide film of an appropriate thickness), the oxide film is too thick on the opposite (000, -1) carbon surface side, and almost all of the FET channel is formed. Is not formed, the area becomes an invalid area.

【0016】そこで、トレンチの(0001)シリコン
面側にのみ第一導電型ソース領域を形成し、(000、
−1)炭素面側には第一導電型ソース領域を形成せず、
ソース電極と第二導電型ベース領域とのオーミック接触
を形成する領域として使用すれば、単位セル当たりの面
積を小さくすることが可能である。また、トレンチの
(0001)シリコン面に対向する面が(000、−
1)面からずれており、ゲート電極の水平断面が突出部
を有するものとしてもよい。
Therefore, the first conductivity type source region is formed only on the (0001) silicon surface side of the trench, and (000,
-1) The first conductivity type source region is not formed on the carbon surface side,
When used as a region for forming ohmic contact between the source electrode and the second conductivity type base region, the area per unit cell can be reduced. The surface of the trench facing the (0001) silicon surface is (000, −
1) It may be offset from the plane, and the horizontal cross section of the gate electrode may have a protrusion.

【0017】そのように、ゲート電極を三角形または台
形状とすれば、ゲート電極の幅を確保しながら、(00
01)シリコン面をできるだけ広くしてかつ単位セル当
たりの面積を小さくすることができる。特に、トレンチ
の(0001)シリコン面に対向する面が(000、−
1)炭素面から30〜60度ずれているものとする。
As described above, when the gate electrode is formed in a triangular shape or a trapezoidal shape, (00
01) The silicon surface can be made as wide as possible and the area per unit cell can be reduced. In particular, the surface of the trench facing the (0001) silicon surface is (000, −
1) It is assumed that it is deviated from the carbon surface by 30 to 60 degrees.

【0018】Tokura等の報告によれば、(Jpn.
J. Appl. Phys.,Vol.34,Part 1, No.10, (1995) pp.556
7)(000、−1)炭素面から30度以上ずれると、
熱酸化膜の厚さは、(000、−1)炭素面のそれの1
/4以下になることが知られている。従って、(000
1)シリコン面に対向する面を(000、−1)炭素面
から30度以上ずらした面にすれば、その面でのゲート
酸化膜の厚さは、(0001)シリコン面側のゲート酸
化膜の厚さとほぼ同じになる。
According to the report of Tokura et al. (Jpn.
J. Appl. Phys., Vol.34, Part 1, No.10, (1995) pp.556
7) If it deviates more than 30 degrees from the (000, -1) carbon surface,
The thickness of the thermal oxide film is 1 of that of the (000, -1) carbon surface.
It is known to be / 4 or less. Therefore, (000
1) If the surface facing the silicon surface is shifted from the (000, -1) carbon surface by 30 degrees or more, the thickness of the gate oxide film on that surface is (0001) silicon surface side gate oxide film. The thickness will be almost the same.

【0019】更に、トレンチの一方の側面が(000
1)シリコン面であり、対向する側面が(000、−
1)炭素面であり、両側面のゲート絶縁膜がほぼ同じ膜
厚であるものとしてもよい。そのようにすれば、トレン
チの両側にチャネルができる。トレンチの一方の側面が
(0001)シリコン面であり、対向する側面が(00
0、−1)炭素面であり、両側面のゲート絶縁膜がほぼ
同じ膜厚であるSiCトレンチFETの製造方法として
は、トレンチ内面に熱酸化膜を形成した後、(000、
−1)炭素面の熱酸化膜を選択的に除去し、再び熱酸化
して(0001)シリコン面と対向する(000、−
1)炭素面のゲート絶縁膜をほぼ同じ膜厚にするものと
する。
Further, one side surface of the trench is (000
1) It is a silicon surface, and the opposite side surface is (000,-
1) It may be a carbon surface, and the gate insulating films on both side surfaces may have substantially the same film thickness. This will create channels on both sides of the trench. One side surface of the trench is a (0001) silicon surface, and the opposite side surface is (00 0).
As a method of manufacturing a SiC trench FET having a carbon surface of 0, −1) and gate insulating films on both side surfaces having substantially the same film thickness, a thermal oxide film is formed on the inner surface of the trench and then (000,
-1) The thermal oxide film on the carbon surface is selectively removed and again thermally oxidized to face the (0001) silicon surface (000,-
1) The gate insulating film on the carbon surface should have almost the same thickness.

【0020】また、トレンチ内面にCVD法によりゲー
ト絶縁膜を堆積してもよい。これらの方法で、両側面の
ゲート絶縁膜がほぼ同じ膜厚となり両側にチャネルを有
するSiCトレンチFETとすることができる。
A gate insulating film may be deposited on the inner surface of the trench by the CVD method. By these methods, the gate insulating films on both side surfaces have almost the same film thickness, so that a SiC trench FET having channels on both sides can be obtained.

【0021】[0021]

【発明の実施の形態】以下図面を参照しながら本発明の
実施の形態について説明する。 [実施例1]図1は、本発明第一の実施例のSiCトレ
ンチFETの要部断面図である。図に示したのは単位セ
ルと呼ばれる電流のスイッチングを行う単位の部分であ
る。実際の素子は図の単位セルを多数集積した上、更に
主に周辺に耐圧を担う部分があるが、本発明の本質に係
わる部分ではないので省略する。ここで、この結晶は4
H−SiCで、図のA−A線の方向が<0001>方向
であり、図の結晶の上面は、(0001)面に垂直な
面、例えば(1、0、−1、0)面である。
Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1 is a cross-sectional view of an essential part of a SiC trench FET according to a first embodiment of the present invention. What is shown in the figure is a portion of a unit called a unit cell for switching a current. In the actual device, a large number of unit cells shown in the figure are integrated, and a peripheral portion mainly bears a withstand voltage, but this is omitted because it is not a portion related to the essence of the present invention. Here, this crystal is 4
In H-SiC, the direction of the AA line in the figure is the <0001> direction, and the upper surface of the crystal in the figure is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane. is there.

【0022】図8の従来のトレンチMOSFETとは、
結晶方位が異なるだけで、構造は同じである。すなわ
ち、n+ ドレイン層11のサブストレート上にそれぞれ
不純物濃度の低いnドリフト層12とp型のpベース層
13とをエピタキシャル成長したSiC基板が用いられ
ている。ここで、n+ ドレイン層11の不純物濃度は5
×1018cm-3、nドリフト層12、pベース層13の
不純物濃度と厚さはそれぞれ5×1015cm-3、10μ
m、6×1016cm-3、1.5μmである。そのpベー
ス層13の表面層に、燐のイオン注入および熱処理によ
り、選択的にnソース領域14が形成されている。その
nソース領域14の一部に、四フッ化炭素ガスを用いた
反応製造方法イオンエッチングにより、表面からnドリ
フト層12に達する溝(以後トレンチと呼ぶ)15が形
成されている。トレンチ15はストライプ状で紙面に垂
直方向に延びており、その側面は、ほぼ(0001)面
になっている。トレンチ15の内側には熱酸化により、
厚さ100nmのゲート酸化膜16が形成され、その内
部に減圧CVD法により、多結晶シリコンのゲート電極
17が埋め込まれている。またNiのスパッタリングに
より、nソース領域14の表面とpベース層13の表面
露出部に共通に接触してソース電極18が、n + ドレイ
ン層11の裏面にドレイン電極19がそれぞれ設けられ
ている。
The conventional trench MOSFET shown in FIG.
The structure is the same, only the crystallographic orientation is different. Sand
Chi, n+On the substrate of the drain layer 11 respectively
N drift layer 12 having a low impurity concentration and p-type p base layer
13 is a SiC substrate epitaxially grown on
ing. Where n+The impurity concentration of the drain layer 11 is 5
× 1018cm-3, N drift layer 12, and p base layer 13
Impurity concentration and thickness are 5 × 10 eachFifteencm-310μ
m, 6 × 1016cm-3, 1.5 μm. That p base
The surface layer of the sputter layer 13 is subjected to phosphorus ion implantation and heat treatment.
Therefore, the n source region 14 is selectively formed. That
Carbon tetrafluoride gas was used for a part of the n source region 14.
Reaction manufacturing method By ion etching, n
A groove (hereinafter referred to as a trench) 15 reaching the soft layer 12 is formed.
Has been established. The trench 15 has a stripe shape and hangs down on the paper.
It extends in the vertical direction and its side surface is almost (0001) plane.
It has become. By thermal oxidation inside the trench 15,
A gate oxide film 16 having a thickness of 100 nm is formed.
Gate electrode of polycrystalline silicon by low pressure CVD method
17 is embedded. For Ni sputtering
From the surface of the n source region 14 and the surface of the p base layer 13
The source electrode 18 contacts the exposed portion in common, +Dray
Drain electrodes 19 are provided on the back surface of the drain layer 11, respectively.
ing.

【0023】このSiCトレンチFETの動作原理は、
図7の従来のSiCトレンチFETと本質的に同じであ
る。しかし、このような構造として、移動度の大きい
(0001)面をMOSFETのチャネル20に利用す
ることによって、SiCトレンチFETのオン抵抗を小
さくすることができる。図9と図10との比較から、
(0001)面に沿ってチャネル20を形成した本実施
例のSiCトレンチFETは、(0001)面に垂直方
向にチャネルを形成する従来のものより約30%小さい
オン抵抗になる。
The operating principle of this SiC trench FET is as follows.
It is essentially the same as the conventional SiC trench FET of FIG. However, by using the (0001) plane having high mobility as the channel 20 of the MOSFET as such a structure, the on-resistance of the SiC trench FET can be reduced. From the comparison between FIG. 9 and FIG.
The SiC trench FET of this embodiment in which the channel 20 is formed along the (0001) plane has an ON resistance which is about 30% smaller than that of the conventional one in which the channel is formed in the direction perpendicular to the (0001) plane.

【0024】[実施例2]図2は、本発明第二の実施例
のSiC縦型トレンチMOSFETの断面図である。こ
こで、この結晶は、4H−SiCで図のB−B線の方向
が<0001>方向であり、図の結晶の上面は、(00
01)面に垂直な面、例えば(1、0、−1、0)面で
ある。この実施例のトレンチMOSFETでは、トレン
チ25の右側の上面に近い表面層にnソース領域24は
あるが、左側にはnソース領域がない点が実施例1と違
っている。
[Embodiment 2] FIG. 2 is a sectional view of a SiC vertical trench MOSFET according to a second embodiment of the present invention. Here, this crystal is 4H-SiC and the direction of the line BB in the figure is the <0001> direction, and the upper surface of the crystal in the figure is (00
It is a plane perpendicular to the (01) plane, for example, a (1, 0, -1, 0) plane. The trench MOSFET of this embodiment is different from the first embodiment in that the n source region 24 is provided in the surface layer near the upper surface on the right side of the trench 25, but the n source region is not provided on the left side.

【0025】トレンチの側面を(0001)面とした場
合、(0001)面にはシリコンで終端した(000
1)シリコン面と、対向する側の炭素で終端した(00
0、−1)炭素面とが現れる。先に述べたように(00
01)シリコン面は、(0001)炭素面よりもはるか
に酸化速度が小さい。図2のトレンチMOSFETで
は、トレンチ25の右側が(0001)シリコン面であ
り、左側が(000、−1)炭素面となっている。それ
に対応してシリコン面ではゲート酸化膜26の厚さが薄
く、炭素面ではゲート酸化膜26’の厚さが厚くなって
いる。
When the side surface of the trench is the (0001) plane, the (0001) plane is terminated with silicon (000).
1) Terminated with carbon on the silicon surface and the opposite side (00
0, -1) carbon surface appears. As mentioned earlier, (00
The 01) silicon surface has a much lower oxidation rate than the (0001) carbon surface. In the trench MOSFET of FIG. 2, the right side of the trench 25 is the (0001) silicon surface and the left side is the (000, −1) carbon surface. Correspondingly, the gate oxide film 26 is thin on the silicon surface, and the gate oxide film 26 'is thick on the carbon surface.

【0026】このように、炭素面側のゲート酸化膜2
6’が厚くなるため、一定のゲート電圧をゲート電極2
7に印加したとき、トレンチ25の右側の(0001)
シリコン面側ではチャネル30ができるものの、炭素面
側では(仮にnソース領域があったとしても)チャネル
がほとんど出来ないということが起きる。そこでこのよ
うな構造では、シリコン面側のゲート酸化膜26に合わ
せてデバイス設計することが重要である。(もし、炭素
面側のゲート酸化膜26’の厚さを適正な値にすると、
シリコン面側でのゲート酸化膜26の厚さが極端に薄く
なって、ゲート酸化膜の絶縁耐圧が著しく損なわれ
る。)そのため、トレンチ25の左側すなわち炭素面側
はnソース領域を形成したとしても、その領域は無効領
域となる。
Thus, the gate oxide film 2 on the carbon surface side
Since 6'is thicker, a constant gate voltage is applied to the gate electrode 2
(0001) on the right side of the trench 25 when applied to
Although the channel 30 can be formed on the silicon surface side, it hardly occurs on the carbon surface side (even if there is an n source region). Therefore, in such a structure, it is important to design the device in accordance with the gate oxide film 26 on the silicon surface side. (If the thickness of the gate oxide film 26 'on the carbon surface side is set to an appropriate value,
The thickness of the gate oxide film 26 on the silicon surface side becomes extremely thin, and the dielectric strength of the gate oxide film is significantly impaired. Therefore, even if an n source region is formed on the left side of the trench 25, that is, on the carbon face side, that region becomes an ineffective region.

【0027】そこで図2に示すように、炭素面側にはn
ソース領域を形成せず、pベース層23とソース電極2
8とのオーミック接触を形成する領域として使用すれ
ば、単位セルの構造を単純化でき、単位セルの寸法を小
さくすることができる。すなわち、単位面積当たりのチ
ャネル密度を大きくすることができ、結果としてトレン
チFETのオン抵抗を小さくすることができる。
Therefore, as shown in FIG. 2, n is present on the carbon face side.
The p base layer 23 and the source electrode 2 are formed without forming the source region.
When used as a region for forming an ohmic contact with 8, the structure of the unit cell can be simplified and the size of the unit cell can be reduced. That is, the channel density per unit area can be increased, and as a result, the ON resistance of the trench FET can be reduced.

【0028】[実施例3]図3は、本発明第三の実施例
のSiCトレンチFETのSiC結晶表面の平面図であ
る。ここで、この結晶は、図のC−C線の方向が<00
01>方向であり、図の結晶の上面は、(0001)面
に垂直な面、例えば(1、0、−1、0)面である。
[Embodiment 3] FIG. 3 is a plan view of the SiC crystal surface of the SiC trench FET of the third embodiment of the present invention. Here, in this crystal, the direction of the line CC in the figure is <00.
01> direction, and the upper surface of the crystal in the figure is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane.

【0029】この実施例3では、(0001)シリコン
面に対向する面を(000、−1)面からずらし、斜め
にしたので、ゲート電極37の水平断面が三角形になっ
ている。ゲート電極37の外側の三角形はゲート酸化膜
36である。三角形のもっとも長い右辺に沿ってnソー
ス領域34が形成されている。点線は、カソード電極の
nソース領域34およびpベース層33への接触部分を
示している。なお、ゲート電極37は、図の平面では孤
立しているが、図の平面以外の部分で互いに接続する手
段が取られている。
In the third embodiment, since the surface facing the (0001) silicon surface is offset from the (000, -1) surface and is inclined, the horizontal cross section of the gate electrode 37 is triangular. The triangle outside the gate electrode 37 is the gate oxide film 36. An n source region 34 is formed along the longest right side of the triangle. The dotted line indicates the contact portion of the cathode electrode with the n source region 34 and the p base layer 33. Although the gate electrodes 37 are isolated in the plane of the drawing, a means for connecting to each other is provided in a portion other than the plane of the drawing.

【0030】実施例1と実施例2では、ゲート電極1
7、27がストライプ状であって、その片側が(00
0、−1)炭素面のため無効領域となった。それに対
し、図3の実施例3の構造では、ゲート電極37の最大
幅を同じにした上でゲート電極37の形状を工夫し、無
効領域を減らして(0001)シリコン面側の面積をほ
ぼ2倍に増大させることができる。その分だけオン抵抗
を低減できることになる。
In Example 1 and Example 2, the gate electrode 1
7 and 27 are stripes, and one side is (00
0, -1) It became an ineffective area because of the carbon surface. On the other hand, in the structure of the third embodiment of FIG. 3, the maximum width of the gate electrode 37 is made the same, and the shape of the gate electrode 37 is devised to reduce the ineffective region so that the area on the (0001) silicon surface side is almost 2 Can be doubled. The ON resistance can be reduced accordingly.

【0031】[実施例4]図4は、本発明第四の実施例
のSiC縦型トレンチMOSFETのSiC表面の平面
図である。ここで、この結晶は、図のD−D線の方向が
<0001>方向であり、結晶の上面は、(0001)
面に垂直な面、例えば(1、0、−1、0)面である。
[Embodiment 4] FIG. 4 is a plan view of the SiC surface of a SiC vertical trench MOSFET according to a fourth embodiment of the present invention. Here, in this crystal, the direction of the DD line in the figure is the <0001> direction, and the upper surface of the crystal is (0001)
It is a plane perpendicular to the plane, for example, a (1, 0, -1, 0) plane.

【0032】この実施例4では、(0001)シリコン
面に対向する面の一部を(0001)面からずらし、斜
めにし、<0001>方向に突出部を有する点は図3の
実施例3と同じであるが、ゲート電極47が互いに接続
している。ゲート電極47の長い右辺に沿ってnソース
領域44が形成されている。点線は、ソース電極のnソ
ース領域44およびpベース層43の表面への接触部分
を示している。
In the fourth embodiment, a part of the surface facing the (0001) silicon surface is deviated from the (0001) surface, is inclined, and has a protrusion in the <0001> direction as in the third embodiment shown in FIG. The same, but the gate electrodes 47 are connected to each other. An n source region 44 is formed along the long right side of the gate electrode 47. The dotted line shows the contact portion of the source electrode with the surfaces of the n source region 44 and the p base layer 43.

【0033】図3の構造では、各セルのゲート電極37
が孤立しているために、これらをつなぐための構造が必
要であったが、この例では、各セルのゲート電極47は
互いに端で接続されており、特別な接続構造が不要であ
る。この実施例のトレンチFETでも、FETの密度を
大きくとることで総チャネル幅が大きくなり、FETの
抵抗を小さくすることができる。
In the structure of FIG. 3, the gate electrode 37 of each cell is
However, in this example, the gate electrodes 47 of the cells are connected to each other at their ends, and no special connection structure is required. Also in the trench FET of this embodiment, by increasing the density of the FET, the total channel width is increased and the resistance of the FET can be reduced.

【0034】[実施例5]図5は、本発明第五の実施例
のSiCトレンチFETのSiC表面の平面図である。
ここで、この結晶は、図のE−E線の方向が<0001
>方向であり、図の結晶の上面は、(0001)面に垂
直な面、例えば(1、0、−1、0)面である。
[Embodiment 5] FIG. 5 is a plan view of the SiC surface of a SiC trench FET according to a fifth embodiment of the present invention.
Here, in this crystal, the direction of line EE in the figure is <0001
> Direction, and the upper surface of the crystal in the figure is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane.

【0035】この実施例5では、(0001)シリコン
面に対向する面の一部を(000、−1)面からずら
し、斜めにしてゲート電極57の水平断面が三角形にな
っている点は実施例3と同じである。ただし、(000
1)シリコン面と対向する面との間の角度は35度にな
っている。ゲート電極57を取り囲む三角形はゲート酸
化膜56である。そして、nソース領域54が長い右辺
に沿ってだけでなく、ゲート電極57を取り囲むように
形成されている。点線は、ソース電極のnソース領域5
4およびpベース層53の表面への接触部分を示してい
る。
In Example 5, the point that the gate electrode 57 has a triangular horizontal cross section is obtained by shifting a part of the surface facing the (0001) silicon surface from the (000, -1) surface and making it oblique. Same as Example 3. However, (000
1) The angle between the silicon surface and the opposing surface is 35 degrees. The triangle surrounding the gate electrode 57 is the gate oxide film 56. Then, the n source region 54 is formed not only along the long right side but so as to surround the gate electrode 57. The dotted line indicates the n source region 5 of the source electrode.
4 and the contact portion to the surface of the p base layer 53 are shown.

【0036】先に述べたように、Tokura等の報告
によれば、(000、−1)炭素面から30度以上ずれ
ると、熱酸化膜の厚さは、(000、−1)炭素面のそ
れの1/4以下になることが知られている。従って、本
実施例5のようにシリコン面に対向する面を(000、
−1)炭素面から35度ずらした面にすれば、その面で
のゲート酸化膜56’の厚さは、(0001)シリコン
面のゲート酸化膜56の厚さとほぼ同じになる。そのた
め、そのゲート電極57を囲むようにnソース領域54
を形成すれば、全周がFETとなり、無効領域とはなら
ない。確かに(000、−1)面からずらされている部
分のチャネルの移動度は(0001)面のチャネルほど
大きくはないが、全体のチャネル幅は大幅に増大し、そ
れだけトレンチFETのオン抵抗は低くなる。
As described above, according to the report of Tokura et al., When the temperature is deviated from the (000, -1) carbon surface by 30 degrees or more, the thickness of the thermal oxide film becomes (000, -1) carbon surface. It is known to be less than 1/4 of that. Therefore, the surface facing the silicon surface is (000,
-1) If the surface is deviated from the carbon surface by 35 degrees, the thickness of the gate oxide film 56 'on that surface is almost the same as the thickness of the gate oxide film 56 on the (0001) silicon surface. Therefore, the n source region 54 is formed so as to surround the gate electrode 57.
If it is formed, the entire circumference becomes a FET and it does not become an invalid area. Certainly, the mobility of the channel in the portion deviated from the (000, -1) plane is not as large as that of the channel in the (0001) plane, but the overall channel width is greatly increased, and the on-resistance of the trench FET is correspondingly increased. Get lower.

【0037】(0001)面からのずれる角度が60度
以上になると、(0001)シリコン面のチャネルよ
り、ずれた面のチャネルの方が倍以上の面積になり、
(0001)面の大きい移動度があまり効果をもたらさ
ないことになる。 [実施例6]図6は、本発明第六の実施例のSiC縦型
トレンチMOSFETの部分断面図である。ここで、こ
の結晶は、図のF−F線の方向が<0001>方向であ
り、結晶の上面は、(0001)面に垂直な面、例えば
(1、0、−1、0)面である。
When the angle of deviation from the (0001) plane is 60 degrees or more, the area of the channel on the deviated plane becomes more than double the area of the channel on the (0001) silicon plane.
The large mobility of the (0001) plane has little effect. [Embodiment 6] FIG. 6 is a partial sectional view of a SiC vertical trench MOSFET according to a sixth embodiment of the present invention. Here, in this crystal, the direction of line FF in the figure is the <0001> direction, and the upper surface of the crystal is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane. is there.

【0038】この実施例6では、ゲート電極67がスト
ライプ状で、トレンチ65の側面の一方は(0001)
シリコン面、他方は(000、−1)炭素面になってい
る。しかし、図1の実施例1とは違って、(0001)
シリコン面側のゲート絶縁膜66、(000、−1)炭
素面側のゲート絶縁膜66’の厚さは両側で同じになっ
ている。そして、ゲート電極67の両側のpベース層6
3の表面層にnソース領域64が形成されている。従っ
て(000、−1)炭素面側も無効領域にはならず、F
ETとして働く。しかもこの実施例6では、ゲート電極
67の両側のチャネル70、70’が移動度の大きい
(0001)面方向になっているので、トレンチFET
のオン抵抗は、図1の実施例1の約1/2になる。
In the sixth embodiment, the gate electrode 67 has a stripe shape, and one side surface of the trench 65 is (0001).
The silicon surface and the other are (000, -1) carbon surfaces. However, unlike the first embodiment in FIG. 1, (0001)
The thickness of the gate insulating film 66 on the silicon surface side and the thickness of the gate insulating film 66 'on the (000, -1) carbon surface side are the same on both sides. Then, the p base layers 6 on both sides of the gate electrode 67 are formed.
An n source region 64 is formed in the surface layer of No. 3. Therefore, the (000, -1) carbon face side does not become an ineffective region, and F
Work as an ET. Moreover, in the sixth embodiment, since the channels 70 and 70 'on both sides of the gate electrode 67 are oriented in the (0001) plane direction where the mobility is high, the trench FET is formed.
The ON resistance of is about 1/2 that of the first embodiment shown in FIG.

【0039】ゲート電極67の両側のゲート絶縁膜6
6、66’の厚さを同じにするには、次のような製造方
法とすればよい。四フッ化炭素と酸素との混合ガスを用
いた反応性イオンエッチングにより、トレンチ65を形
成した後、熱酸化により、トレンチ65内に酸化膜を形
成する。この酸化膜は熱酸化膜なので、(0001)シ
リコン面には薄く、(0001)炭素面には厚くできる
が、この時はシリコン面上の酸化膜厚がゲート絶縁膜6
6として適当な厚さに制御する。次に、反応性イオンエ
ッチングのイオン入射角依存性を利用して、炭素面上の
酸化膜を選択的に除去する。その後再び熱酸化により、
(0001)炭素面上にゲート絶縁膜66’として適当
な厚さの酸化膜を成長させる。この時間は先の酸化の際
の時間に比べて非常に短いので、(0001)シリコン
面上の酸化膜は殆ど厚くならない。
The gate insulating film 6 on both sides of the gate electrode 67
In order to make the thicknesses of 6, 66 'the same, the following manufacturing method may be used. After forming the trench 65 by reactive ion etching using a mixed gas of carbon tetrafluoride and oxygen, an oxide film is formed in the trench 65 by thermal oxidation. Since this oxide film is a thermal oxide film, it can be thin on the (0001) silicon surface and thick on the (0001) carbon surface. At this time, the oxide film thickness on the silicon surface is equal to that of the gate insulating film 6.
6, the thickness is controlled to a suitable value. Next, the oxide film on the carbon surface is selectively removed by utilizing the ion incident angle dependence of the reactive ion etching. Then again by thermal oxidation,
An oxide film having an appropriate thickness is grown as a gate insulating film 66 'on the (0001) carbon surface. Since this time is much shorter than the time of the previous oxidation, the oxide film on the (0001) silicon surface hardly becomes thick.

【0040】また別の方法としては、ゲート絶縁膜66
としてプラズマCVD法により酸化膜を堆積してもよ
い。そうすれば、(0001)シリコン面、(000、
−1)炭素面に同じ厚さのゲート絶縁膜66、66’が
堆積される。プラズマCVD法によるゲート絶縁膜6
6、66’としては、窒化ケイ素膜を堆積してもよい。
As another method, the gate insulating film 66 is used.
Alternatively, an oxide film may be deposited by the plasma CVD method. Then, the (0001) silicon surface, (000,
-1) Gate insulating films 66 and 66 'having the same thickness are deposited on the carbon surface. Gate insulating film 6 formed by plasma CVD method
As 6, 66 ', a silicon nitride film may be deposited.

【0041】以上の実施例において、SiC結晶を4H
−SiCとしたが、6H−SiCにも適用できる。ま
た、(0001)面に垂直な結晶の主面として(1、
0、−1、0)面のものを取り上げたが、(1、1、−
2、0)面を始めとして沢山の結晶面が考えられる。更
に、ソース電極8とドレイン電極9とが、SiC結晶の
異なる表面に設けられたいわゆる縦型のFETの例を示
したが、必ずしも縦型FETに限らず、両電極が同一表
面上に有る横型のトレンチFETにも適用できる。
In the above embodiment, the SiC crystal was changed to 4H.
Although -SiC is used, 6H-SiC is also applicable. Further, as a main surface of the crystal perpendicular to the (0001) plane, (1,
I picked up the (0, -1, 0) plane, but (1, 1,-)
Many crystal planes are conceivable, including the (2,0) plane. Further, an example of a so-called vertical type FET in which the source electrode 8 and the drain electrode 9 are provided on different surfaces of the SiC crystal is shown, but not limited to the vertical type FET, a horizontal type FET in which both electrodes are on the same surface is shown. It can also be applied to the trench FET of.

【0042】[0042]

【発明の効果】以上説明したように本発明のSiCトレ
ンチFETは、(0001)面に垂直な結晶面を主面と
する結晶を用い、垂直なトレンチを形成するなどして、
キャリアの移動度の大きい(0001)面にチャネルが
形成されるようにすることによって、トレンチFETの
オン抵抗を大幅に低減することができる。例えば、(0
001)面に垂直な面にチャネルが形成されていた従来
のトレンチFETに比べ、約30%の低減ができる。
As described above, the SiC trench FET of the present invention uses a crystal whose main surface is a crystal plane perpendicular to the (0001) plane to form a vertical trench.
By forming a channel on the (0001) plane where carrier mobility is high, the on-resistance of the trench FET can be significantly reduced. For example, (0
It can be reduced by about 30% as compared with the conventional trench FET in which the channel is formed on the surface perpendicular to the (001) surface.

【0043】(0001)面には(0001)シリコン
面と(000、−1)炭素面とがあり、熱酸化時の酸化
速度が異なる。このため、(0001)シリコン面側に
適当なゲート酸化膜を熱酸化により形成したときは、
(000、−1)炭素面側のゲート酸化膜は厚くなり過
ぎ、FETとして有効に動作しない。従って、(000
1)シリコン面側のみに第一導電型ソース領域を形成し
たり、ゲート電極の断面を三角形などにしたりして、単
位セル形状の縮小を図り、チャネル幅を増大させ、オン
抵抗を低減することもできる。
The (0001) plane has a (0001) silicon plane and a (000, -1) carbon plane, and the oxidation rates at the time of thermal oxidation are different. Therefore, when an appropriate gate oxide film is formed on the (0001) silicon surface by thermal oxidation,
The gate oxide film on the (000, -1) carbon surface side becomes too thick and does not operate effectively as an FET. Therefore, (000
1) To form a source region of the first conductivity type only on the silicon surface side or to make the cross section of the gate electrode triangular or the like to reduce the unit cell shape, increase the channel width, and reduce the on-resistance. You can also

【0044】更に(000、−1)炭素面側のゲート酸
化膜の厚さをシリコン面側と同じにして、チャネル幅を
増大させ、オン抵抗を低減することもできる。特にスト
ライプ状のゲート電極で、両側のゲート酸化膜の厚さを
同じにすれば、移動度の大きい(0001)面にチャネ
ルが形成されるので、オン抵抗の低減効果も大である。
Further, the thickness of the gate oxide film on the (000, -1) carbon surface side can be made the same as that on the silicon surface side to increase the channel width and reduce the on-resistance. In particular, in the case of a striped gate electrode, if the gate oxide films on both sides have the same thickness, a channel is formed on the (0001) plane having high mobility, and therefore the effect of reducing the on-resistance is great.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1の炭化ケイ素トレンチFETの要部断
面図
FIG. 1 is a sectional view of an essential part of a silicon carbide trench FET of Example 1.

【図2】実施例2の炭化ケイ素トレンチFETの要部断
面図
FIG. 2 is a cross-sectional view of essential parts of a silicon carbide trench FET of Example 2

【図3】実施例3の炭化ケイ素トレンチFETの炭化ケ
イ素表面の平面図
FIG. 3 is a plan view of a silicon carbide surface of a silicon carbide trench FET of Example 3.

【図4】実施例4の炭化ケイ素トレンチFETの炭化ケ
イ素表面の平面図
FIG. 4 is a plan view of a silicon carbide surface of a silicon carbide trench FET of Example 4.

【図5】実施例5の炭化ケイ素トレンチFETの炭化ケ
イ素表面の平面図
FIG. 5 is a plan view of the silicon carbide surface of the silicon carbide trench FET of Example 5.

【図6】実施例5の炭化ケイ素トレンチFETの要部断
面図
FIG. 6 is a cross-sectional view of essential parts of a silicon carbide trench FET of Example 5.

【図7】従来の炭化ケイ素トレンチFETの要部断面図FIG. 7 is a cross-sectional view of a main part of a conventional silicon carbide trench FET.

【図8】炭化ケイ素トレンチFETのオン抵抗のチャネ
ル移動度依存性を示す図
FIG. 8 is a diagram showing channel mobility dependence of on-resistance of a silicon carbide trench FET.

【図9】炭化ケイ素トレンチFETのチャネル移動度と
キャリア濃度との関係を示す図
FIG. 9 is a diagram showing a relationship between channel mobility and carrier concentration of a silicon carbide trench FET.

【図10】炭化ケイ素トレンチFETのチャネル移動度
とキャリア濃度との関係を示す図
FIG. 10 is a diagram showing a relationship between channel mobility and carrier concentration of a silicon carbide trench FET.

【符号の説明】[Explanation of symbols]

1、11 n+ ドレイン層 2、12 nドリフト層 3、13、23、33、43、53、63 pべース
層 4、14、24、34、44、54、64 nソース
領域 5、15、25、65 トレンチ 6、16、26、26’、36、46、56、56’、
66、66’ ゲト絶縁膜またはゲート酸化膜 7、17、27、37、47、57、67 ゲート電
極 8、18、28、68 ソース電極 9、19、 ドレイン電極 10、20、30、70、70’ チャネル
1, 11 n + drain layer 2, 12 n drift layer 3, 13, 23, 33, 43, 53, 63 p base layer 4, 14, 24, 34, 44, 54, 64 n source region 5, 15 , 25,65 trenches 6, 16, 26, 26 ', 36, 46, 56, 56',
66, 66 ′ Gate insulating film or gate oxide film 7, 17, 27, 37, 47, 57, 67 Gate electrode 8, 18, 28, 68 Source electrode 9, 19, Drain electrode 10, 20, 30, 70, 70 'Channel

Claims (11)

【特許請求の範囲】[Claims] 【請求項1】アルファ相炭化ケイ素単結晶の第一導電型
ドレイン層上に順に形成されたそのドレイン層より不純
物濃度の低い炭化ケイ素の第一導電型ドリフト層と炭化
ケイ素の第二導電型ベース層と、その第二導電型ベース
層の表面層の一部に形成された第一導電型ソース領域
と、その第一導電型ソース領域の表面から第一導電型ド
リフト層に達するトレンチとを有し、そのトレンチ内に
ゲート絶縁膜を介して設けられたゲート電極と、第一導
電型ソース領域の表面に接して設けられたソース電極
と、第一導電型ドレイン層の裏面に設けられたドレイン
電極とを備えるものにおいて、 ゲート電極に電圧を印加したときにゲート絶縁膜に沿っ
た第二導電型ベース層に(0001)面方向のチャネル
が形成されることを特徴とする炭化ケイ素トレンチFE
T。
1. A first-conductivity-type drift layer of silicon carbide and a second-conductivity-type base of silicon carbide, which are successively formed on a first-conductivity-type drain layer of an alpha-phase silicon carbide single crystal and have a lower impurity concentration than the drain layer. A layer, a first conductivity type source region formed in a part of the surface layer of the second conductivity type base layer, and a trench reaching the first conductivity type drift layer from the surface of the first conductivity type source region. The gate electrode provided in the trench via the gate insulating film, the source electrode provided in contact with the surface of the first conductivity type source region, and the drain provided on the back surface of the first conductivity type drain layer. A silicon carbide tray having a (0001) plane direction in the second conductivity type base layer along the gate insulating film when a voltage is applied to the gate electrode. FE
T.
【請求項2】トレンチの少なくとも一方の側面がほぼ
(0001)面であることを特徴とする請求項1記載の
炭化ケイ素トレンチFET。
2. A silicon carbide trench FET according to claim 1, wherein at least one side surface of the trench is substantially a (0001) plane.
【請求項3】第二導電型ベース層の主面がほぼ(000
1)面に垂直な結晶面であることを特徴とする請求項2
記載の炭化ケイ素トレンチFET。
3. The main surface of the second conductivity type base layer is approximately (000
3. A crystal plane perpendicular to the 1) plane.
The silicon carbide trench FET described.
【請求項4】第二導電型ベース層の主面がほぼ(1、
0、−1、0)面、あるいはそれと等価な結晶面である
ことを特徴とする請求項3記載の炭化ケイ素トレンチF
ET。
4. The main surface of the second-conductivity-type base layer is substantially (1,
4. The silicon carbide trench F according to claim 3, wherein the silicon carbide trench F has a (0, -1, 0) plane or a crystal plane equivalent thereto.
ET.
【請求項5】第二導電型ベース層の主面がほぼ(1、
1、−2、0)面、あるいはそれと等価な結晶面である
ことを特徴とする請求項3記載の炭化ケイ素トレンチF
ET。
5. The main surface of the second-conductivity-type base layer is substantially (1,
4. The silicon carbide trench F according to claim 3, wherein the silicon carbide trench F has a (1, -2, 0) plane or a crystal plane equivalent thereto.
ET.
【請求項6】トレンチの(0001)シリコン面側にの
み第一導電型ソース領域を形成することを特徴とする請
求項3ないし5のいずれかに記載の炭化ケイ素トレンチ
FET。
6. The silicon carbide trench FET according to claim 3, wherein the first conductivity type source region is formed only on the (0001) silicon surface side of the trench.
【請求項7】トレンチの(0001)シリコン面に対向
する面が(000、−1)面からずれており、ゲート電
極の水平断面が突出部を有することを特徴とする請求項
2ないし6のいずれかに記載の炭化ケイ素トレンチFE
T。
7. The method according to claim 2, wherein the surface of the trench facing the (0001) silicon surface is offset from the (000, -1) surface, and the horizontal cross section of the gate electrode has a protrusion. Silicon carbide trench FE according to any one of
T.
【請求項8】トレンチの(0001)シリコン面に対向
する面が(000、−1)面から30〜90度ずれてい
ることを特徴とする請求項7記載の炭化ケイ素トレンチ
FET。
8. A silicon carbide trench FET according to claim 7, wherein the surface of the trench facing the (0001) silicon surface is offset from the (000, -1) surface by 30 to 90 degrees.
【請求項9】トレンチの一方の側面が(0001)シリ
コン面であり、対向する側面が(000、−1)炭素面
であり、両側面のゲート絶縁膜がほぼ同じ膜厚であるこ
とを特徴とする請求項2ないし5のいずれかに記載の炭
化ケイ素トレンチFET。
9. A trench is characterized in that one side surface is a (0001) silicon surface, the opposite side surface is a (000, -1) carbon surface, and the gate insulating films on both side surfaces have substantially the same thickness. The silicon carbide trench FET according to any one of claims 2 to 5.
【請求項10】第一導電型の炭化ケイ素サブストレート
上に順に形成された基板より不純物濃度の低い炭化ケイ
素の第一導電型ドリフト層と炭化ケイ素の第二導電型ベ
ース層と、その第二導電型ベース層の表面層の一部に形
成された第一導電型ソース領域と、その第一導電型ソー
ス領域の表面から第一導電型ドリフト層に達し、側面が
ほぼ(0001)、(000、−1)面であるトレンチ
とを有し、そのトレンチ内にゲート絶縁膜を介して設け
られたゲート電極と、第一導電型ソース領域の表面に接
して設けられたソース電極と、炭化ケイ素サブストレー
トの表面に設けられたドレイン電極とを備える炭化ケイ
素トレンチFETの製造方法において、 トレンチ内部に熱酸化により酸化ケイ素膜を形成した
後、(000、−1)炭素面の酸化ケイ素膜を選択的に
除去し、再び熱酸化して(0001)シリコン面と対向
する(000、−1)炭素面のゲート絶縁膜をほぼ同じ
膜厚にすることを特徴とする炭化ケイ素トレンチFET
の製造方法。
10. A first-conductivity-type drift layer of silicon carbide and a second-conductivity-type base layer of silicon carbide, each of which has an impurity concentration lower than that of a substrate, which is sequentially formed on a first-conductivity-type silicon carbide substrate, and a second layer thereof. The first conductivity type source region formed in a part of the surface layer of the conductivity type base layer and the first conductivity type drift layer from the surface of the first conductivity type source region, and the side surfaces thereof are approximately (0001), (000 , -1) plane, and a gate electrode provided in the trench via a gate insulating film, a source electrode provided in contact with the surface of the first conductivity type source region, and silicon carbide. In a method of manufacturing a silicon carbide trench FET including a drain electrode provided on a surface of a substrate, a silicon oxide film is formed inside the trench by thermal oxidation, and then a (000, -1) carbon surface is oxidized. A silicon carbide trench FET characterized in that the silicon film is selectively removed and then thermally oxidized again so that the gate insulating film on the (000, -1) carbon surface facing the (0001) silicon surface has almost the same thickness.
Manufacturing method.
【請求項11】第一導電型の炭化ケイ素サブストレート
上に順に形成された基板より不純物濃度の低い炭化ケイ
素の第一導電型ドリフト層と炭化ケイ素の第二導電型ベ
ース層と、その第二導電型ベース層の表面層の一部に形
成された第一導電型ソース領域と、その第一導電型ソー
ス領域の表面から第一導電型ドリフト層に達し、側面が
ほぼ(0001)、(000、−1)面であるトレンチ
とを有し、そのトレンチ内にゲート絶縁膜を介して設け
られたゲート電極と、第一導電型ソース領域の表面に接
して設けられたソース電極と、炭化ケイ素サブストレー
トの表面に設けられたドレイン電極とを備える炭化ケイ
素トレンチFETの製造方法において、 トレンチ内部にCVD法により、トレンチの両側面に同
じ膜圧のゲート絶縁膜を堆積することを特徴とする炭化
ケイ素トレンチFETの製造方法。
11. A first-conductivity-type drift layer of silicon carbide and a second-conductivity-type base layer of silicon carbide, each of which has an impurity concentration lower than that of a substrate, which is sequentially formed on a first-conductivity-type silicon carbide substrate, and a second layer thereof. The first conductivity type source region formed in a part of the surface layer of the conductivity type base layer and the first conductivity type drift layer from the surface of the first conductivity type source region, and the side surfaces thereof are approximately (0001), (000 , -1) plane, and a gate electrode provided in the trench via a gate insulating film, a source electrode provided in contact with the surface of the first conductivity type source region, and silicon carbide. In a method of manufacturing a silicon carbide trench FET including a drain electrode provided on a surface of a substrate, a gate insulating film having the same film pressure is deposited on both side surfaces of the trench by a CVD method inside the trench. A method of manufacturing a silicon carbide trench FET, comprising:
JP8065745A 1996-03-22 1996-03-22 Silicon carbide trench fet and manufacture thereof Pending JPH09260650A (en)

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