JPH09260650A - Silicon carbide trench fet and manufacture thereof - Google Patents
Silicon carbide trench fet and manufacture thereofInfo
- Publication number
- JPH09260650A JPH09260650A JP8065745A JP6574596A JPH09260650A JP H09260650 A JPH09260650 A JP H09260650A JP 8065745 A JP8065745 A JP 8065745A JP 6574596 A JP6574596 A JP 6574596A JP H09260650 A JPH09260650 A JP H09260650A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- silicon carbide
- silicon
- layer
- conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 96
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 66
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 52
- 239000010703 silicon Substances 0.000 claims abstract description 52
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 42
- 239000013078 crystal Substances 0.000 claims abstract description 39
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 239000002344 surface layer Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 abstract description 2
- 238000010405 reoxidation reaction Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 229910052984 zinc sulfide Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- WGPCGCOKHWGKJJ-UHFFFAOYSA-N sulfanylidenezinc Chemical compound [Zn]=S WGPCGCOKHWGKJJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、高耐圧、大電流
を制御する電界効果トランジスタ（以下ＦＥＴと略
す）、特に炭化ケイ素を用い、トレンチを有する炭化ケ
イ素トレンチＦＥＴに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter abbreviated as FET) for controlling a high breakdown voltage and a large current, and particularly to a silicon carbide trench FET having a trench using silicon carbide.
【０００２】[0002]
【従来の技術】最近、電力用半導体素子として炭化ケイ
素（以下ＳｉＣと略す）を用いた縦型ＦＥＴの試作が行
われている。ＳｉＣは最大電界強度がシリコンより一桁
大きいため、薄い結晶で高耐圧の半導体素子ができ、オ
ン電圧を低くできて、大電流密度の使用に適するからで
ある。2. Description of the Related Art Recently, trial manufacture of a vertical FET using silicon carbide (hereinafter abbreviated as SiC) as a power semiconductor element has been carried out. Since the maximum electric field strength of SiC is an order of magnitude higher than that of silicon, a semiconductor element with a thin crystal and a high breakdown voltage can be formed, the on-voltage can be lowered, and it is suitable for use with a large current density.
【０００３】縦型ＦＥＴは、ＳｉＣの電力用デバイスへ
の適用を考える上で重要なデバイスである。その理由は
電圧駆動型デバイスであるため、素子の並列駆動が容易
であり、また駆動回路の簡素化が可能なこと、およびユ
ニポーラ素子であるため、高速スイッチングが可能なこ
となどによる。また、ＳｉＣにおいては、シリコンと異
なり深い不純物拡散が困難であるのに対して、エピタキ
シャル成長は比較的容易であるので、図７に示すような
トレンチ５をもつトレンチＦＥＴが一般的である。な
お、以下においてｎ、ｐを冠した層、領域等はそれぞれ
電子、正孔を多数キャリアとする層、領域を意味するも
のとする。The vertical FET is an important device when considering application of SiC to a power device. The reason is that it is a voltage-driven device, so that it is easy to drive the elements in parallel, and the drive circuit can be simplified, and because it is a unipolar element, high-speed switching is possible. Further, unlike SiC, it is difficult to diffuse deep impurities in SiC, but epitaxial growth is relatively easy. Therefore, a trench FET having a trench 5 as shown in FIG. 7 is generally used. In the following, layers, regions, and the like bearing n and p are layers and regions in which electrons and holes serve as majority carriers, respectively.
【０００４】図７は、従来試作されたＳｉＣのトレンチ
ＦＥＴの要部断面図である。図において、ｎ+ ドレイン
層１のサブストレート上にサブストレートより不純物濃
度の低いｎドリフト層２とｐ型のｐベース層３とをエピ
タキシャル成長したＳｉＣ基板が用いられている。Ｓｉ
Ｃでは、厚い層を熱拡散で形成することが困難である
が、エピタキシャル成長は比較的容易に行われる。ｐベ
ース層３の表面層に選択的に高濃度のｎソース領域４が
形成され、そのｎソース領域４の一部に表面からドリフ
ト層２に達する溝（以後トレンチと呼ぶ）５が形成され
ている。トレンチ５の内側にはゲート絶縁膜６を介して
ゲート電極７が設けられ、また、ｎソース領域４の表面
とｐベース層３の表面露出部に共通に接触してソース電
極８が、ｎ + ドレイン層１の裏面にドレイン電極９がそ
れぞれ設けられている。FIG. 7 shows a conventionally manufactured SiC trench.
It is a principal part sectional drawing of FET. In the figure, n+drain
The impurity concentration on the substrate of layer 1 is higher than that of the substrate.
The n drift layer 2 and the p-type p base layer 3 having a low degree are epitaxially formed.
A SiC substrate that has been grown by a taxi is used. Si
In C, it is difficult to form a thick layer by thermal diffusion
However, epitaxial growth is relatively easy. p
The high concentration n source region 4 is selectively formed on the surface layer of the source layer 3.
Diffused from the surface to a part of the n source region 4 formed.
A trench (hereinafter referred to as a trench) 5 reaching the trench layer 2 is formed.
ing. Inside the trench 5 via the gate insulating film 6
A gate electrode 7 is provided and the surface of the n source region 4 is provided.
And the exposed surface of the p base layer 3 are commonly contacted, and
Pole 8 is n +A drain electrode 9 is formed on the back surface of the drain layer 1.
Each is provided.
【０００５】このＭＯＳＦＥＴの動作は、ドレイン電極
９とソース電極８との間に電圧を印加した状態で、ゲー
ト電極７にある値以上の正の電圧を加えると、ゲート電
極７の横のｐベース層３の表面層にチャネル（反転層）
１０が形成され、そのチャネル１０を通じて、ソース電
極８からドレイン電極９へと電子電流が流れる。このよ
うにして、高耐圧を維持し、かつ大電流を制御するもの
である。ＳｉＣにおいては、ゲート絶縁膜６としてＳｉ
Ｃを熱酸化してできる酸化ケイ素膜が使用できる。ただ
し、ゲート絶縁膜６は他の絶縁膜でもよい。なお、以下
酸化ケイ素膜を酸化膜と呼ぶ。The operation of this MOSFET is such that when a positive voltage higher than a certain value is applied to the gate electrode 7 in a state where a voltage is applied between the drain electrode 9 and the source electrode 8, the p-base next to the gate electrode 7 is applied. Channel (inversion layer) in the surface layer of layer 3
10 is formed, and an electron current flows from the source electrode 8 to the drain electrode 9 through the channel 10. In this way, a high breakdown voltage is maintained and a large current is controlled. In SiC, Si is used as the gate insulating film 6.
A silicon oxide film formed by thermally oxidizing C can be used. However, the gate insulating film 6 may be another insulating film. Note that the silicon oxide film is hereinafter referred to as an oxide film.
【０００６】これまでに報告されているＳｉＣの縦型Ｍ
ＯＳＦＥＴでは、用いられた単結晶は４Ｈ−ＳｉＣまた
は６Ｈ−ＳｉＣと呼ばれるものであった。これらは閃亜
鉛鉱型とウルツ鉱型とを積層した形のアルファ相ＳｉＣ
で、単結晶ウェハの製造が可能であることによる。そし
て先にも述べたように、用いる結晶のｎドリフト層２は
通常エピタキシャル成長法により形成されている。これ
は不純物濃度および厚さを正確に制御するためである。
更に、これらの単結晶の表面の結晶方位は、（０００
１）面、或いはｃ面と呼ばれる方位であった。この方位
が使用される理由は、これまでのエピタキシャル成長技
術が、（０００１）面について開発されてきたことによ
る。従って、炭化ケイ素トレンチＦＥＴのチャネルが形
成されるのは、ほぼ９０度傾いた面、或いは大きく（０
００１）面からはずれた面であったことが図から容易に
理解できる。The vertical M of SiC that has been reported so far.
In OSFETs, the single crystals used were those called 4H-SiC or 6H-SiC. These are alpha-phase SiC in the form of stacking zinc blende type and wurtzite type
Therefore, it is possible to manufacture a single crystal wafer. As described above, the crystalline n drift layer 2 used is usually formed by an epitaxial growth method. This is to accurately control the impurity concentration and thickness.
Furthermore, the crystal orientation of the surface of these single crystals is (000
The orientation was called 1) plane or c-plane. The reason that this orientation is used is that the epitaxial growth techniques so far have been developed for the (0001) plane. Therefore, the channel of the silicon carbide trench FET is formed on a surface inclined by about 90 degrees or a large (0
It can be easily understood from the figure that the surface was deviated from the (001) surface.
【０００７】[0007]
【発明が解決しようとする課題】以上の説明からわかる
ように、これまでの縦型ＦＥＴをはじめとするＳｉＣ半
導体素子の試作は、電力用半導体素子の特性を重視した
ものではなく、利用できる結晶のみを考慮したものであ
った。図８は、ＳｉＣの縦型ＦＥＴの耐圧とオン抵抗と
の関係を表した図であって、横軸にＦＥＴの耐圧、縦軸
にそのオン抵抗をとり、ＦＥＴのチャネル（反転層）の
移動度をパラメータとしてプロットしたものである。こ
の図８から、ＳｉＣの縦型ＦＥＴのオン抵抗は、ＦＥＴ
のチャネルの移動度によって大きく左右されることがわ
かる。As can be seen from the above description, the trial manufacture of SiC semiconductor devices such as vertical FETs so far does not place importance on the characteristics of power semiconductor devices and can be used for crystals. It was only a consideration. FIG. 8 is a diagram showing the relationship between the breakdown voltage and the on-resistance of a vertical SiC FET, where the horizontal axis represents the breakdown voltage of the FET and the vertical axis represents the on-resistance, and the movement of the channel (inversion layer) of the FET is shown. It is plotted using degrees as a parameter. From this FIG. 8, the on-resistance of the SiC vertical FET is
It can be seen that the channel mobility greatly depends on the channel mobility.
【０００８】これは縦型ＦＥＴのオン抵抗に、チャネル
の抵抗が直列に入っているためである。特に、１０００
Ｖ以下の領域では、ほとんどＦＥＴのチャネルによって
抵抗が占められている。この耐圧範囲は、パワーデバイ
スとしての利用が最も多い範囲であることから、特にこ
の領域でメリットがでることが期待される。すなわち、
ＳｉＣ本来のメリットを引き出すためには、ＦＥＴのチ
ャネルの移動度をどこまで大きくできるかが最も大きな
因子であることを示している。This is because the resistance of the channel is in series with the ON resistance of the vertical FET. Especially 1000
In the region below V, the resistance is almost occupied by the channel of the FET. Since this withstand voltage range is the most used range as a power device, it is expected that there will be an advantage especially in this range. That is,
It has been shown that in order to bring out the original merits of SiC, the maximum factor is how much the channel mobility of the FET can be increased.
【０００９】ところが、これまでの報告では、ＳｉＣの
縦型ＦＥＴの移動度は、１０ｃｍ2／Ｖｓ程度しか報告
されていない。一方では、（０００１）面に平行にチャ
ネルが形成される横型のＦＥＴでは、すでに７０ｃｍ2
／Ｖｓが報告されている。この原因については、明らか
になっていないが、表面の結晶面の特性が特に重要な役
割をしていることは間違いない。However, in the reports so far, the mobility of the SiC vertical FET is reported to be only about 10 cm 2 / Vs. On the other hand, in a lateral FET in which a channel is formed parallel to the (0001) plane, it is already 70 cm 2
/ Vs is reported. Although the cause of this has not been clarified, there is no doubt that the characteristics of the surface crystal plane play a particularly important role.
【００１０】以上の問題に鑑みて本発明の目的は、チャ
ネルのできる結晶面を移動度の大きな結晶面とすること
によって、オン抵抗の小さな炭化ケイ素トレンチＦＥＴ
を提供することにある。In view of the above problems, an object of the present invention is to make a crystal plane in which a channel is formed into a crystal plane having a high mobility, so that a silicon carbide trench FET having a small on-resistance can be obtained.
Is to provide.
【００１１】[0011]
【課題を解決するための手段】上記課題の解決のため本
発明は、アルファ相炭化ケイ素単結晶の第一導電型ドレ
イン層上に順に形成されたドレイン層より不純物濃度の
低い炭化ケイ素の第一導電型ドリフト層と炭化ケイ素の
第二導電型ベース層と、その第二導電型ベース層の表面
層の一部に形成された第一導電型ソース領域と、その第
一導電型ソース領域の表面から第一導電型ドリフト層に
達するトレンチとを有し、そのトレンチ内にゲート絶縁
膜を介して設けられたゲート電極と、第一導電型ソース
領域の表面に接して設けられたソース電極と、第一導電
型ドレイン層の裏面に設けられたドレイン電極とを備え
る炭化ケイ素トレンチＦＥＴにおいて、ゲート電極に電
圧を印加したときにゲート絶縁膜に沿った第二導電型ベ
ース層に（０００１）面方向の反転層のチャネルが形成
されるものとする。In order to solve the above problems, the present invention provides a first silicon carbide having a lower impurity concentration than a drain layer sequentially formed on a first conductivity type drain layer of an alpha phase silicon carbide single crystal. A second conductivity type base layer of a conductivity type drift layer and silicon carbide, a first conductivity type source region formed in a part of a surface layer of the second conductivity type base layer, and a surface of the first conductivity type source region From, having a trench reaching the first conductivity type drift layer, the gate electrode provided through the gate insulating film in the trench, the source electrode provided in contact with the surface of the first conductivity type source region, In a silicon carbide trench FET including a drain electrode provided on the back surface of a first conductivity type drain layer, when a voltage is applied to the gate electrode, a second conductivity type base layer along the gate insulating film is formed (000 ) Channels face the direction of the inversion layer is assumed to be formed.
【００１２】特に、トレンチの側面がほぼ（０００１）
面であるものがよい。図９、図１０は、それぞれ（００
０１）面に垂直および平行な反転層における移動度の電
子濃度依存性の図である。横軸は電子濃度、縦軸は移動
度で、いずれも対数表示になっている。低温での計算値
であるため、図８の値より大きな値になっているが、傾
向は利用できる。４Ｈ−ＳｉＣ、６Ｈ−ＳｉＣの両結晶
ともに、（０００１）面に平行な反転層の移動度が、
（０００１）面に垂直な反転層の移動度より、約２０〜
３０％大きいことがわかる。Particularly, the side surface of the trench is almost (0001).
What is a face is good. 9 and 10 show (00
It is a figure of the electron concentration dependence of the mobility in the inversion layer perpendicular | vertical and parallel to the (01) plane. The horizontal axis represents electron concentration and the vertical axis represents mobility, both of which are shown in logarithmic scale. Since it is a calculated value at a low temperature, the value is larger than the value in FIG. 8, but the tendency can be used. In both 4H-SiC and 6H-SiC crystals, the mobility of the inversion layer parallel to the (0001) plane is
From the mobility of the inversion layer perpendicular to the (0001) plane, about 20 to
You can see that it is 30% larger.
【００１３】従って、トレンチの側面がほぼ（０００
１）面であるようにすれば、キャリアの移動度の大きい
（０００１）面をチャネルとして利用できる。そして、
炭化ケイ素サブストレートの主面がほぼ（０００１）面
に垂直な結晶面、例えば、（１、０、−１、０）面や
（１、１、−２、０）面、あるいはそれらと等価な結晶
面であるものとする。Therefore, the side surface of the trench is approximately (000
If the plane is the (1) plane, the (0001) plane having high carrier mobility can be used as a channel. And
A crystal plane in which a main surface of a silicon carbide substrate is substantially perpendicular to a (0001) plane, for example, a (1,0, -1,0) plane or a (1,1, -2,0) plane, or an equivalent thereof It shall be a crystal plane.
【００１４】そのような低次の面の結晶は、切り出しや
すく、またそのような結晶を用いて、表面にほぼ垂直な
トレンチを形成すれば、（０００１）面に平行なチャネ
ルができる。また、トレンチの（０００１）シリコン面
側にのみ第一導電型ソース領域を有するものとする。A crystal of such a low-order plane is easy to cut out, and if a trench almost vertical to the surface is formed using such a crystal, a channel parallel to the (0001) plane is formed. Further, it is assumed that the source region of the first conductivity type is provided only on the (0001) silicon surface side of the trench.
【００１５】（０００１）面をチャネル領域とした場
合、（０００１）面にはシリコンで終端した（０００
１）シリコン面と、これと１８０度の裏の炭素で終端し
た（０００、−１）炭素面とが現れる。（０００１）シ
リコン面は、（０００、−１）炭素面よりもはるかに酸
化速度が小さい。逆にいうと、熱酸化した場合（００
０、−１）炭素面には、（０００１）シリコン面よりず
っと厚い酸化膜が出来てしまう。従って、（０００１）
シリコン面側に（適当な厚さの酸化膜を形成して）チャ
ネルを形成したとき、反対側の（０００、−１）炭素面
側では酸化膜の厚さが厚すぎて、ほとんどＦＥＴのチャ
ネルは形成されないため、その領域は無効領域となる。When the (0001) plane is used as a channel region, the (0001) plane is terminated with silicon (000).
1) A silicon surface and a (000, -1) carbon surface terminated by this and a 180 degree back carbon appear. The (0001) silicon face has a much lower oxidation rate than the (000, -1) carbon face. Conversely, when thermally oxidized (00
An oxide film much thicker than the (0001) silicon surface is formed on the (0, -1) carbon surface. Therefore, (0001)
When a channel is formed on the silicon surface side (by forming an oxide film of an appropriate thickness), the oxide film is too thick on the opposite (000, -1) carbon surface side, and almost all of the FET channel is formed. Is not formed, the area becomes an invalid area.
【００１６】そこで、トレンチの（０００１）シリコン
面側にのみ第一導電型ソース領域を形成し、（０００、
−１）炭素面側には第一導電型ソース領域を形成せず、
ソース電極と第二導電型ベース領域とのオーミック接触
を形成する領域として使用すれば、単位セル当たりの面
積を小さくすることが可能である。また、トレンチの
（０００１）シリコン面に対向する面が（０００、−
１）面からずれており、ゲート電極の水平断面が突出部
を有するものとしてもよい。Therefore, the first conductivity type source region is formed only on the (0001) silicon surface side of the trench, and (000,
-1) The first conductivity type source region is not formed on the carbon surface side,
When used as a region for forming ohmic contact between the source electrode and the second conductivity type base region, the area per unit cell can be reduced. The surface of the trench facing the (0001) silicon surface is (000, −
1) It may be offset from the plane, and the horizontal cross section of the gate electrode may have a protrusion.
【００１７】そのように、ゲート電極を三角形または台
形状とすれば、ゲート電極の幅を確保しながら、（００
０１）シリコン面をできるだけ広くしてかつ単位セル当
たりの面積を小さくすることができる。特に、トレンチ
の（０００１）シリコン面に対向する面が（０００、−
１）炭素面から３０〜６０度ずれているものとする。As described above, when the gate electrode is formed in a triangular shape or a trapezoidal shape, (00
01) The silicon surface can be made as wide as possible and the area per unit cell can be reduced. In particular, the surface of the trench facing the (0001) silicon surface is (000, −
1) It is assumed that it is deviated from the carbon surface by 30 to 60 degrees.
【００１８】Ｔｏｋｕｒａ等の報告によれば、（Jpn.
J. Appl. Phys.,Vol.34,Part 1, No.10, (1995) pp.556
7）（０００、−１）炭素面から３０度以上ずれると、
熱酸化膜の厚さは、（０００、−１）炭素面のそれの１
／４以下になることが知られている。従って、（０００
１）シリコン面に対向する面を（０００、−１）炭素面
から３０度以上ずらした面にすれば、その面でのゲート
酸化膜の厚さは、（０００１）シリコン面側のゲート酸
化膜の厚さとほぼ同じになる。According to the report of Tokura et al. (Jpn.
J. Appl. Phys., Vol.34, Part 1, No.10, (1995) pp.556
7) If it deviates more than 30 degrees from the (000, -1) carbon surface,
The thickness of the thermal oxide film is 1 of that of the (000, -1) carbon surface.
It is known to be / 4 or less. Therefore, (000
1) If the surface facing the silicon surface is shifted from the (000, -1) carbon surface by 30 degrees or more, the thickness of the gate oxide film on that surface is (0001) silicon surface side gate oxide film. The thickness will be almost the same.
【００１９】更に、トレンチの一方の側面が（０００
１）シリコン面であり、対向する側面が（０００、−
１）炭素面であり、両側面のゲート絶縁膜がほぼ同じ膜
厚であるものとしてもよい。そのようにすれば、トレン
チの両側にチャネルができる。トレンチの一方の側面が
（０００１）シリコン面であり、対向する側面が（００
０、−１）炭素面であり、両側面のゲート絶縁膜がほぼ
同じ膜厚であるＳｉＣトレンチＦＥＴの製造方法として
は、トレンチ内面に熱酸化膜を形成した後、（０００、
−１）炭素面の熱酸化膜を選択的に除去し、再び熱酸化
して（０００１）シリコン面と対向する（０００、−
１）炭素面のゲート絶縁膜をほぼ同じ膜厚にするものと
する。Further, one side surface of the trench is (000
1) It is a silicon surface, and the opposite side surface is (000,-
1) It may be a carbon surface, and the gate insulating films on both side surfaces may have substantially the same film thickness. This will create channels on both sides of the trench. One side surface of the trench is a (0001) silicon surface, and the opposite side surface is (00 0).
As a method of manufacturing a SiC trench FET having a carbon surface of 0, −1) and gate insulating films on both side surfaces having substantially the same film thickness, a thermal oxide film is formed on the inner surface of the trench and then (000,
-1) The thermal oxide film on the carbon surface is selectively removed and again thermally oxidized to face the (0001) silicon surface (000,-
1) The gate insulating film on the carbon surface should have almost the same thickness.
【００２０】また、トレンチ内面にＣＶＤ法によりゲー
ト絶縁膜を堆積してもよい。これらの方法で、両側面の
ゲート絶縁膜がほぼ同じ膜厚となり両側にチャネルを有
するＳｉＣトレンチＦＥＴとすることができる。A gate insulating film may be deposited on the inner surface of the trench by the CVD method. By these methods, the gate insulating films on both side surfaces have almost the same film thickness, so that a SiC trench FET having channels on both sides can be obtained.
【００２１】[0021]
【発明の実施の形態】以下図面を参照しながら本発明の
実施の形態について説明する。 ［実施例１］図１は、本発明第一の実施例のＳｉＣトレ
ンチＦＥＴの要部断面図である。図に示したのは単位セ
ルと呼ばれる電流のスイッチングを行う単位の部分であ
る。実際の素子は図の単位セルを多数集積した上、更に
主に周辺に耐圧を担う部分があるが、本発明の本質に係
わる部分ではないので省略する。ここで、この結晶は４
Ｈ−ＳｉＣで、図のＡ−Ａ線の方向が＜０００１＞方向
であり、図の結晶の上面は、（０００１）面に垂直な
面、例えば（１、０、−１、０）面である。Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1 is a cross-sectional view of an essential part of a SiC trench FET according to a first embodiment of the present invention. What is shown in the figure is a portion of a unit called a unit cell for switching a current. In the actual device, a large number of unit cells shown in the figure are integrated, and a peripheral portion mainly bears a withstand voltage, but this is omitted because it is not a portion related to the essence of the present invention. Here, this crystal is 4
In H-SiC, the direction of the AA line in the figure is the <0001> direction, and the upper surface of the crystal in the figure is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane. is there.
【００２２】図８の従来のトレンチＭＯＳＦＥＴとは、
結晶方位が異なるだけで、構造は同じである。すなわ
ち、ｎ+ ドレイン層１１のサブストレート上にそれぞれ
不純物濃度の低いｎドリフト層１２とｐ型のｐベース層
１３とをエピタキシャル成長したＳｉＣ基板が用いられ
ている。ここで、ｎ+ ドレイン層１１の不純物濃度は５
×１０18ｃｍ-3、ｎドリフト層１２、ｐベース層１３の
不純物濃度と厚さはそれぞれ５×１０15ｃｍ-3、１０μ
ｍ、６×１０16ｃｍ-3、１．５μｍである。そのｐベー
ス層１３の表面層に、燐のイオン注入および熱処理によ
り、選択的にｎソース領域１４が形成されている。その
ｎソース領域１４の一部に、四フッ化炭素ガスを用いた
反応製造方法イオンエッチングにより、表面からｎドリ
フト層１２に達する溝（以後トレンチと呼ぶ）１５が形
成されている。トレンチ１５はストライプ状で紙面に垂
直方向に延びており、その側面は、ほぼ（０００１）面
になっている。トレンチ１５の内側には熱酸化により、
厚さ１００ｎｍのゲート酸化膜１６が形成され、その内
部に減圧ＣＶＤ法により、多結晶シリコンのゲート電極
１７が埋め込まれている。またＮｉのスパッタリングに
より、ｎソース領域１４の表面とｐベース層１３の表面
露出部に共通に接触してソース電極１８が、ｎ + ドレイ
ン層１１の裏面にドレイン電極１９がそれぞれ設けられ
ている。The conventional trench MOSFET shown in FIG.
The structure is the same, only the crystallographic orientation is different. Sand
Chi, n+On the substrate of the drain layer 11 respectively
N drift layer 12 having a low impurity concentration and p-type p base layer
13 is a SiC substrate epitaxially grown on
ing. Where n+The impurity concentration of the drain layer 11 is 5
× 1018cm-3, N drift layer 12, and p base layer 13
Impurity concentration and thickness are 5 × 10 eachFifteencm-310μ
m, 6 × 1016cm-3, 1.5 μm. That p base
The surface layer of the sputter layer 13 is subjected to phosphorus ion implantation and heat treatment.
Therefore, the n source region 14 is selectively formed. That
Carbon tetrafluoride gas was used for a part of the n source region 14.
Reaction manufacturing method By ion etching, n
A groove (hereinafter referred to as a trench) 15 reaching the soft layer 12 is formed.
Has been established. The trench 15 has a stripe shape and hangs down on the paper.
It extends in the vertical direction and its side surface is almost (0001) plane.
It has become. By thermal oxidation inside the trench 15,
A gate oxide film 16 having a thickness of 100 nm is formed.
Gate electrode of polycrystalline silicon by low pressure CVD method
17 is embedded. For Ni sputtering
From the surface of the n source region 14 and the surface of the p base layer 13
The source electrode 18 contacts the exposed portion in common, +Dray
Drain electrodes 19 are provided on the back surface of the drain layer 11, respectively.
ing.
【００２３】このＳｉＣトレンチＦＥＴの動作原理は、
図７の従来のＳｉＣトレンチＦＥＴと本質的に同じであ
る。しかし、このような構造として、移動度の大きい
（０００１）面をＭＯＳＦＥＴのチャネル２０に利用す
ることによって、ＳｉＣトレンチＦＥＴのオン抵抗を小
さくすることができる。図９と図１０との比較から、
（０００１）面に沿ってチャネル２０を形成した本実施
例のＳｉＣトレンチＦＥＴは、（０００１）面に垂直方
向にチャネルを形成する従来のものより約３０％小さい
オン抵抗になる。The operating principle of this SiC trench FET is as follows.
It is essentially the same as the conventional SiC trench FET of FIG. However, by using the (0001) plane having high mobility as the channel 20 of the MOSFET as such a structure, the on-resistance of the SiC trench FET can be reduced. From the comparison between FIG. 9 and FIG.
The SiC trench FET of this embodiment in which the channel 20 is formed along the (0001) plane has an ON resistance which is about 30% smaller than that of the conventional one in which the channel is formed in the direction perpendicular to the (0001) plane.
【００２４】［実施例２］図２は、本発明第二の実施例
のＳｉＣ縦型トレンチＭＯＳＦＥＴの断面図である。こ
こで、この結晶は、４Ｈ−ＳｉＣで図のＢ−Ｂ線の方向
が＜０００１＞方向であり、図の結晶の上面は、（００
０１）面に垂直な面、例えば（１、０、−１、０）面で
ある。この実施例のトレンチＭＯＳＦＥＴでは、トレン
チ２５の右側の上面に近い表面層にｎソース領域２４は
あるが、左側にはｎソース領域がない点が実施例１と違
っている。[Embodiment 2] FIG. 2 is a sectional view of a SiC vertical trench MOSFET according to a second embodiment of the present invention. Here, this crystal is 4H-SiC and the direction of the line BB in the figure is the <0001> direction, and the upper surface of the crystal in the figure is (00
It is a plane perpendicular to the (01) plane, for example, a (1, 0, -1, 0) plane. The trench MOSFET of this embodiment is different from the first embodiment in that the n source region 24 is provided in the surface layer near the upper surface on the right side of the trench 25, but the n source region is not provided on the left side.
【００２５】トレンチの側面を（０００１）面とした場
合、（０００１）面にはシリコンで終端した（０００
１）シリコン面と、対向する側の炭素で終端した（００
０、−１）炭素面とが現れる。先に述べたように（００
０１）シリコン面は、（０００１）炭素面よりもはるか
に酸化速度が小さい。図２のトレンチＭＯＳＦＥＴで
は、トレンチ２５の右側が（０００１）シリコン面であ
り、左側が（０００、−１）炭素面となっている。それ
に対応してシリコン面ではゲート酸化膜２６の厚さが薄
く、炭素面ではゲート酸化膜２６’の厚さが厚くなって
いる。When the side surface of the trench is the (0001) plane, the (0001) plane is terminated with silicon (000).
1) Terminated with carbon on the silicon surface and the opposite side (00
0, -1) carbon surface appears. As mentioned earlier, (00
The 01) silicon surface has a much lower oxidation rate than the (0001) carbon surface. In the trench MOSFET of FIG. 2, the right side of the trench 25 is the (0001) silicon surface and the left side is the (000, −1) carbon surface. Correspondingly, the gate oxide film 26 is thin on the silicon surface, and the gate oxide film 26 'is thick on the carbon surface.
【００２６】このように、炭素面側のゲート酸化膜２
６’が厚くなるため、一定のゲート電圧をゲート電極２
７に印加したとき、トレンチ２５の右側の（０００１）
シリコン面側ではチャネル３０ができるものの、炭素面
側では（仮にｎソース領域があったとしても）チャネル
がほとんど出来ないということが起きる。そこでこのよ
うな構造では、シリコン面側のゲート酸化膜２６に合わ
せてデバイス設計することが重要である。（もし、炭素
面側のゲート酸化膜２６’の厚さを適正な値にすると、
シリコン面側でのゲート酸化膜２６の厚さが極端に薄く
なって、ゲート酸化膜の絶縁耐圧が著しく損なわれ
る。）そのため、トレンチ２５の左側すなわち炭素面側
はｎソース領域を形成したとしても、その領域は無効領
域となる。Thus, the gate oxide film 2 on the carbon surface side
Since 6'is thicker, a constant gate voltage is applied to the gate electrode 2
(0001) on the right side of the trench 25 when applied to
Although the channel 30 can be formed on the silicon surface side, it hardly occurs on the carbon surface side (even if there is an n source region). Therefore, in such a structure, it is important to design the device in accordance with the gate oxide film 26 on the silicon surface side. (If the thickness of the gate oxide film 26 'on the carbon surface side is set to an appropriate value,
The thickness of the gate oxide film 26 on the silicon surface side becomes extremely thin, and the dielectric strength of the gate oxide film is significantly impaired. Therefore, even if an n source region is formed on the left side of the trench 25, that is, on the carbon face side, that region becomes an ineffective region.
【００２７】そこで図２に示すように、炭素面側にはｎ
ソース領域を形成せず、ｐベース層２３とソース電極２
８とのオーミック接触を形成する領域として使用すれ
ば、単位セルの構造を単純化でき、単位セルの寸法を小
さくすることができる。すなわち、単位面積当たりのチ
ャネル密度を大きくすることができ、結果としてトレン
チＦＥＴのオン抵抗を小さくすることができる。Therefore, as shown in FIG. 2, n is present on the carbon face side.
The p base layer 23 and the source electrode 2 are formed without forming the source region.
When used as a region for forming an ohmic contact with 8, the structure of the unit cell can be simplified and the size of the unit cell can be reduced. That is, the channel density per unit area can be increased, and as a result, the ON resistance of the trench FET can be reduced.
【００２８】［実施例３］図３は、本発明第三の実施例
のＳｉＣトレンチＦＥＴのＳｉＣ結晶表面の平面図であ
る。ここで、この結晶は、図のＣ−Ｃ線の方向が＜００
０１＞方向であり、図の結晶の上面は、（０００１）面
に垂直な面、例えば（１、０、−１、０）面である。[Embodiment 3] FIG. 3 is a plan view of the SiC crystal surface of the SiC trench FET of the third embodiment of the present invention. Here, in this crystal, the direction of the line CC in the figure is <00.
01> direction, and the upper surface of the crystal in the figure is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane.
【００２９】この実施例３では、（０００１）シリコン
面に対向する面を（０００、−１）面からずらし、斜め
にしたので、ゲート電極３７の水平断面が三角形になっ
ている。ゲート電極３７の外側の三角形はゲート酸化膜
３６である。三角形のもっとも長い右辺に沿ってｎソー
ス領域３４が形成されている。点線は、カソード電極の
ｎソース領域３４およびｐベース層３３への接触部分を
示している。なお、ゲート電極３７は、図の平面では孤
立しているが、図の平面以外の部分で互いに接続する手
段が取られている。In the third embodiment, since the surface facing the (0001) silicon surface is offset from the (000, -1) surface and is inclined, the horizontal cross section of the gate electrode 37 is triangular. The triangle outside the gate electrode 37 is the gate oxide film 36. An n source region 34 is formed along the longest right side of the triangle. The dotted line indicates the contact portion of the cathode electrode with the n source region 34 and the p base layer 33. Although the gate electrodes 37 are isolated in the plane of the drawing, a means for connecting to each other is provided in a portion other than the plane of the drawing.
【００３０】実施例１と実施例２では、ゲート電極１
７、２７がストライプ状であって、その片側が（００
０、−１）炭素面のため無効領域となった。それに対
し、図３の実施例３の構造では、ゲート電極３７の最大
幅を同じにした上でゲート電極３７の形状を工夫し、無
効領域を減らして（０００１）シリコン面側の面積をほ
ぼ２倍に増大させることができる。その分だけオン抵抗
を低減できることになる。In Example 1 and Example 2, the gate electrode 1
7 and 27 are stripes, and one side is (00
0, -1) It became an ineffective area because of the carbon surface. On the other hand, in the structure of the third embodiment of FIG. 3, the maximum width of the gate electrode 37 is made the same, and the shape of the gate electrode 37 is devised to reduce the ineffective region so that the area on the (0001) silicon surface side is almost 2 Can be doubled. The ON resistance can be reduced accordingly.
【００３１】［実施例４］図４は、本発明第四の実施例
のＳｉＣ縦型トレンチＭＯＳＦＥＴのＳｉＣ表面の平面
図である。ここで、この結晶は、図のＤ−Ｄ線の方向が
＜０００１＞方向であり、結晶の上面は、（０００１）
面に垂直な面、例えば（１、０、−１、０）面である。[Embodiment 4] FIG. 4 is a plan view of the SiC surface of a SiC vertical trench MOSFET according to a fourth embodiment of the present invention. Here, in this crystal, the direction of the DD line in the figure is the <0001> direction, and the upper surface of the crystal is (0001)
It is a plane perpendicular to the plane, for example, a (1, 0, -1, 0) plane.
【００３２】この実施例４では、（０００１）シリコン
面に対向する面の一部を（０００１）面からずらし、斜
めにし、＜０００１＞方向に突出部を有する点は図３の
実施例３と同じであるが、ゲート電極４７が互いに接続
している。ゲート電極４７の長い右辺に沿ってｎソース
領域４４が形成されている。点線は、ソース電極のｎソ
ース領域４４およびｐベース層４３の表面への接触部分
を示している。In the fourth embodiment, a part of the surface facing the (0001) silicon surface is deviated from the (0001) surface, is inclined, and has a protrusion in the <0001> direction as in the third embodiment shown in FIG. The same, but the gate electrodes 47 are connected to each other. An n source region 44 is formed along the long right side of the gate electrode 47. The dotted line shows the contact portion of the source electrode with the surfaces of the n source region 44 and the p base layer 43.
【００３３】図３の構造では、各セルのゲート電極３７
が孤立しているために、これらをつなぐための構造が必
要であったが、この例では、各セルのゲート電極４７は
互いに端で接続されており、特別な接続構造が不要であ
る。この実施例のトレンチＦＥＴでも、ＦＥＴの密度を
大きくとることで総チャネル幅が大きくなり、ＦＥＴの
抵抗を小さくすることができる。In the structure of FIG. 3, the gate electrode 37 of each cell is
However, in this example, the gate electrodes 47 of the cells are connected to each other at their ends, and no special connection structure is required. Also in the trench FET of this embodiment, by increasing the density of the FET, the total channel width is increased and the resistance of the FET can be reduced.
【００３４】［実施例５］図５は、本発明第五の実施例
のＳｉＣトレンチＦＥＴのＳｉＣ表面の平面図である。
ここで、この結晶は、図のＥ−Ｅ線の方向が＜０００１
＞方向であり、図の結晶の上面は、（０００１）面に垂
直な面、例えば（１、０、−１、０）面である。[Embodiment 5] FIG. 5 is a plan view of the SiC surface of a SiC trench FET according to a fifth embodiment of the present invention.
Here, in this crystal, the direction of line EE in the figure is <0001
> Direction, and the upper surface of the crystal in the figure is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane.
【００３５】この実施例５では、（０００１）シリコン
面に対向する面の一部を（０００、−１）面からずら
し、斜めにしてゲート電極５７の水平断面が三角形にな
っている点は実施例３と同じである。ただし、（０００
１）シリコン面と対向する面との間の角度は３５度にな
っている。ゲート電極５７を取り囲む三角形はゲート酸
化膜５６である。そして、ｎソース領域５４が長い右辺
に沿ってだけでなく、ゲート電極５７を取り囲むように
形成されている。点線は、ソース電極のｎソース領域５
４およびｐベース層５３の表面への接触部分を示してい
る。In Example 5, the point that the gate electrode 57 has a triangular horizontal cross section is obtained by shifting a part of the surface facing the (0001) silicon surface from the (000, -1) surface and making it oblique. Same as Example 3. However, (000
1) The angle between the silicon surface and the opposing surface is 35 degrees. The triangle surrounding the gate electrode 57 is the gate oxide film 56. Then, the n source region 54 is formed not only along the long right side but so as to surround the gate electrode 57. The dotted line indicates the n source region 5 of the source electrode.
4 and the contact portion to the surface of the p base layer 53 are shown.
【００３６】先に述べたように、Ｔｏｋｕｒａ等の報告
によれば、（０００、−１）炭素面から３０度以上ずれ
ると、熱酸化膜の厚さは、（０００、−１）炭素面のそ
れの１／４以下になることが知られている。従って、本
実施例５のようにシリコン面に対向する面を（０００、
−１）炭素面から３５度ずらした面にすれば、その面で
のゲート酸化膜５６’の厚さは、（０００１）シリコン
面のゲート酸化膜５６の厚さとほぼ同じになる。そのた
め、そのゲート電極５７を囲むようにｎソース領域５４
を形成すれば、全周がＦＥＴとなり、無効領域とはなら
ない。確かに（０００、−１）面からずらされている部
分のチャネルの移動度は（０００１）面のチャネルほど
大きくはないが、全体のチャネル幅は大幅に増大し、そ
れだけトレンチＦＥＴのオン抵抗は低くなる。As described above, according to the report of Tokura et al., When the temperature is deviated from the (000, -1) carbon surface by 30 degrees or more, the thickness of the thermal oxide film becomes (000, -1) carbon surface. It is known to be less than 1/4 of that. Therefore, the surface facing the silicon surface is (000,
-1) If the surface is deviated from the carbon surface by 35 degrees, the thickness of the gate oxide film 56 'on that surface is almost the same as the thickness of the gate oxide film 56 on the (0001) silicon surface. Therefore, the n source region 54 is formed so as to surround the gate electrode 57.
If it is formed, the entire circumference becomes a FET and it does not become an invalid area. Certainly, the mobility of the channel in the portion deviated from the (000, -1) plane is not as large as that of the channel in the (0001) plane, but the overall channel width is greatly increased, and the on-resistance of the trench FET is correspondingly increased. Get lower.
【００３７】（０００１）面からのずれる角度が６０度
以上になると、（０００１）シリコン面のチャネルよ
り、ずれた面のチャネルの方が倍以上の面積になり、
（０００１）面の大きい移動度があまり効果をもたらさ
ないことになる。 ［実施例６］図６は、本発明第六の実施例のＳｉＣ縦型
トレンチＭＯＳＦＥＴの部分断面図である。ここで、こ
の結晶は、図のＦ−Ｆ線の方向が＜０００１＞方向であ
り、結晶の上面は、（０００１）面に垂直な面、例えば
（１、０、−１、０）面である。When the angle of deviation from the (0001) plane is 60 degrees or more, the area of the channel on the deviated plane becomes more than double the area of the channel on the (0001) silicon plane.
The large mobility of the (0001) plane has little effect. [Embodiment 6] FIG. 6 is a partial sectional view of a SiC vertical trench MOSFET according to a sixth embodiment of the present invention. Here, in this crystal, the direction of line FF in the figure is the <0001> direction, and the upper surface of the crystal is a plane perpendicular to the (0001) plane, for example, the (1, 0, -1, 0) plane. is there.
【００３８】この実施例６では、ゲート電極６７がスト
ライプ状で、トレンチ６５の側面の一方は（０００１）
シリコン面、他方は（０００、−１）炭素面になってい
る。しかし、図１の実施例１とは違って、（０００１）
シリコン面側のゲート絶縁膜６６、（０００、−１）炭
素面側のゲート絶縁膜６６’の厚さは両側で同じになっ
ている。そして、ゲート電極６７の両側のｐベース層６
３の表面層にｎソース領域６４が形成されている。従っ
て（０００、−１）炭素面側も無効領域にはならず、Ｆ
ＥＴとして働く。しかもこの実施例６では、ゲート電極
６７の両側のチャネル７０、７０’が移動度の大きい
（０００１）面方向になっているので、トレンチＦＥＴ
のオン抵抗は、図１の実施例１の約１／２になる。In the sixth embodiment, the gate electrode 67 has a stripe shape, and one side surface of the trench 65 is (0001).
The silicon surface and the other are (000, -1) carbon surfaces. However, unlike the first embodiment in FIG. 1, (0001)
The thickness of the gate insulating film 66 on the silicon surface side and the thickness of the gate insulating film 66 'on the (000, -1) carbon surface side are the same on both sides. Then, the p base layers 6 on both sides of the gate electrode 67 are formed.
An n source region 64 is formed in the surface layer of No. 3. Therefore, the (000, -1) carbon face side does not become an ineffective region, and F
Work as an ET. Moreover, in the sixth embodiment, since the channels 70 and 70 'on both sides of the gate electrode 67 are oriented in the (0001) plane direction where the mobility is high, the trench FET is formed.
The ON resistance of is about 1/2 that of the first embodiment shown in FIG.
【００３９】ゲート電極６７の両側のゲート絶縁膜６
６、６６’の厚さを同じにするには、次のような製造方
法とすればよい。四フッ化炭素と酸素との混合ガスを用
いた反応性イオンエッチングにより、トレンチ６５を形
成した後、熱酸化により、トレンチ６５内に酸化膜を形
成する。この酸化膜は熱酸化膜なので、（０００１）シ
リコン面には薄く、（０００１）炭素面には厚くできる
が、この時はシリコン面上の酸化膜厚がゲート絶縁膜６
６として適当な厚さに制御する。次に、反応性イオンエ
ッチングのイオン入射角依存性を利用して、炭素面上の
酸化膜を選択的に除去する。その後再び熱酸化により、
（０００１）炭素面上にゲート絶縁膜６６’として適当
な厚さの酸化膜を成長させる。この時間は先の酸化の際
の時間に比べて非常に短いので、（０００１）シリコン
面上の酸化膜は殆ど厚くならない。The gate insulating film 6 on both sides of the gate electrode 67
In order to make the thicknesses of 6, 66 'the same, the following manufacturing method may be used. After forming the trench 65 by reactive ion etching using a mixed gas of carbon tetrafluoride and oxygen, an oxide film is formed in the trench 65 by thermal oxidation. Since this oxide film is a thermal oxide film, it can be thin on the (0001) silicon surface and thick on the (0001) carbon surface. At this time, the oxide film thickness on the silicon surface is equal to that of the gate insulating film 6.
6, the thickness is controlled to a suitable value. Next, the oxide film on the carbon surface is selectively removed by utilizing the ion incident angle dependence of the reactive ion etching. Then again by thermal oxidation,
An oxide film having an appropriate thickness is grown as a gate insulating film 66 'on the (0001) carbon surface. Since this time is much shorter than the time of the previous oxidation, the oxide film on the (0001) silicon surface hardly becomes thick.
【００４０】また別の方法としては、ゲート絶縁膜６６
としてプラズマＣＶＤ法により酸化膜を堆積してもよ
い。そうすれば、（０００１）シリコン面、（０００、
−１）炭素面に同じ厚さのゲート絶縁膜６６、６６’が
堆積される。プラズマＣＶＤ法によるゲート絶縁膜６
６、６６’としては、窒化ケイ素膜を堆積してもよい。As another method, the gate insulating film 66 is used.
Alternatively, an oxide film may be deposited by the plasma CVD method. Then, the (0001) silicon surface, (000,
-1) Gate insulating films 66 and 66 'having the same thickness are deposited on the carbon surface. Gate insulating film 6 formed by plasma CVD method
As 6, 66 ', a silicon nitride film may be deposited.
【００４１】以上の実施例において、ＳｉＣ結晶を４Ｈ
−ＳｉＣとしたが、６Ｈ−ＳｉＣにも適用できる。ま
た、（０００１）面に垂直な結晶の主面として（１、
０、−１、０）面のものを取り上げたが、（１、１、−
２、０）面を始めとして沢山の結晶面が考えられる。更
に、ソース電極８とドレイン電極９とが、ＳｉＣ結晶の
異なる表面に設けられたいわゆる縦型のＦＥＴの例を示
したが、必ずしも縦型ＦＥＴに限らず、両電極が同一表
面上に有る横型のトレンチＦＥＴにも適用できる。In the above embodiment, the SiC crystal was changed to 4H.
Although -SiC is used, 6H-SiC is also applicable. Further, as a main surface of the crystal perpendicular to the (0001) plane, (1,
I picked up the (0, -1, 0) plane, but (1, 1,-)
Many crystal planes are conceivable, including the (2,0) plane. Further, an example of a so-called vertical type FET in which the source electrode 8 and the drain electrode 9 are provided on different surfaces of the SiC crystal is shown, but not limited to the vertical type FET, a horizontal type FET in which both electrodes are on the same surface is shown. It can also be applied to the trench FET of.
【００４２】[0042]
【発明の効果】以上説明したように本発明のＳｉＣトレ
ンチＦＥＴは、（０００１）面に垂直な結晶面を主面と
する結晶を用い、垂直なトレンチを形成するなどして、
キャリアの移動度の大きい（０００１）面にチャネルが
形成されるようにすることによって、トレンチＦＥＴの
オン抵抗を大幅に低減することができる。例えば、（０
００１）面に垂直な面にチャネルが形成されていた従来
のトレンチＦＥＴに比べ、約３０％の低減ができる。As described above, the SiC trench FET of the present invention uses a crystal whose main surface is a crystal plane perpendicular to the (0001) plane to form a vertical trench.
By forming a channel on the (0001) plane where carrier mobility is high, the on-resistance of the trench FET can be significantly reduced. For example, (0
It can be reduced by about 30% as compared with the conventional trench FET in which the channel is formed on the surface perpendicular to the (001) surface.
【００４３】（０００１）面には（０００１）シリコン
面と（０００、−１）炭素面とがあり、熱酸化時の酸化
速度が異なる。このため、（０００１）シリコン面側に
適当なゲート酸化膜を熱酸化により形成したときは、
（０００、−１）炭素面側のゲート酸化膜は厚くなり過
ぎ、ＦＥＴとして有効に動作しない。従って、（０００
１）シリコン面側のみに第一導電型ソース領域を形成し
たり、ゲート電極の断面を三角形などにしたりして、単
位セル形状の縮小を図り、チャネル幅を増大させ、オン
抵抗を低減することもできる。The (0001) plane has a (0001) silicon plane and a (000, -1) carbon plane, and the oxidation rates at the time of thermal oxidation are different. Therefore, when an appropriate gate oxide film is formed on the (0001) silicon surface by thermal oxidation,
The gate oxide film on the (000, -1) carbon surface side becomes too thick and does not operate effectively as an FET. Therefore, (000
1) To form a source region of the first conductivity type only on the silicon surface side or to make the cross section of the gate electrode triangular or the like to reduce the unit cell shape, increase the channel width, and reduce the on-resistance. You can also
【００４４】更に（０００、−１）炭素面側のゲート酸
化膜の厚さをシリコン面側と同じにして、チャネル幅を
増大させ、オン抵抗を低減することもできる。特にスト
ライプ状のゲート電極で、両側のゲート酸化膜の厚さを
同じにすれば、移動度の大きい（０００１）面にチャネ
ルが形成されるので、オン抵抗の低減効果も大である。Further, the thickness of the gate oxide film on the (000, -1) carbon surface side can be made the same as that on the silicon surface side to increase the channel width and reduce the on-resistance. In particular, in the case of a striped gate electrode, if the gate oxide films on both sides have the same thickness, a channel is formed on the (0001) plane having high mobility, and therefore the effect of reducing the on-resistance is great.
【図１】実施例１の炭化ケイ素トレンチＦＥＴの要部断
面図FIG. 1 is a sectional view of an essential part of a silicon carbide trench FET of Example 1.
【図２】実施例２の炭化ケイ素トレンチＦＥＴの要部断
面図FIG. 2 is a cross-sectional view of essential parts of a silicon carbide trench FET of Example 2
【図３】実施例３の炭化ケイ素トレンチＦＥＴの炭化ケ
イ素表面の平面図FIG. 3 is a plan view of a silicon carbide surface of a silicon carbide trench FET of Example 3.
【図４】実施例４の炭化ケイ素トレンチＦＥＴの炭化ケ
イ素表面の平面図FIG. 4 is a plan view of a silicon carbide surface of a silicon carbide trench FET of Example 4.
【図５】実施例５の炭化ケイ素トレンチＦＥＴの炭化ケ
イ素表面の平面図FIG. 5 is a plan view of the silicon carbide surface of the silicon carbide trench FET of Example 5.
【図６】実施例５の炭化ケイ素トレンチＦＥＴの要部断
面図FIG. 6 is a cross-sectional view of essential parts of a silicon carbide trench FET of Example 5.
【図７】従来の炭化ケイ素トレンチＦＥＴの要部断面図FIG. 7 is a cross-sectional view of a main part of a conventional silicon carbide trench FET.
【図８】炭化ケイ素トレンチＦＥＴのオン抵抗のチャネ
ル移動度依存性を示す図FIG. 8 is a diagram showing channel mobility dependence of on-resistance of a silicon carbide trench FET.
【図９】炭化ケイ素トレンチＦＥＴのチャネル移動度と
キャリア濃度との関係を示す図FIG. 9 is a diagram showing a relationship between channel mobility and carrier concentration of a silicon carbide trench FET.
【図１０】炭化ケイ素トレンチＦＥＴのチャネル移動度
とキャリア濃度との関係を示す図FIG. 10 is a diagram showing a relationship between channel mobility and carrier concentration of a silicon carbide trench FET.
１、１１ ｎ+ ドレイン層 ２、１２ ｎドリフト層 ３、１３、２３、３３、４３、５３、６３ ｐべース
層 ４、１４、２４、３４、４４、５４、６４ ｎソース
領域 ５、１５、２５、６５ トレンチ ６、１６、２６、２６’、３６、４６、５６、５６’、
６６、６６’ ゲト絶縁膜またはゲート酸化膜 ７、１７、２７、３７、４７、５７、６７ ゲート電
極 ８、１８、２８、６８ ソース電極 ９、１９、 ドレイン電極 １０、２０、３０、７０、７０’ チャネル1, 11 n + drain layer 2, 12 n drift layer 3, 13, 23, 33, 43, 53, 63 p base layer 4, 14, 24, 34, 44, 54, 64 n source region 5, 15 , 25,65 trenches 6, 16, 26, 26 ', 36, 46, 56, 56',
66, 66 ′ Gate insulating film or gate oxide film 7, 17, 27, 37, 47, 57, 67 Gate electrode 8, 18, 28, 68 Source electrode 9, 19, Drain electrode 10, 20, 30, 70, 70 'Channel
Claims (11)
ドレイン層上に順に形成されたそのドレイン層より不純
物濃度の低い炭化ケイ素の第一導電型ドリフト層と炭化
ケイ素の第二導電型ベース層と、その第二導電型ベース
層の表面層の一部に形成された第一導電型ソース領域
と、その第一導電型ソース領域の表面から第一導電型ド
リフト層に達するトレンチとを有し、そのトレンチ内に
ゲート絶縁膜を介して設けられたゲート電極と、第一導
電型ソース領域の表面に接して設けられたソース電極
と、第一導電型ドレイン層の裏面に設けられたドレイン
電極とを備えるものにおいて、 ゲート電極に電圧を印加したときにゲート絶縁膜に沿っ
た第二導電型ベース層に（０００１）面方向のチャネル
が形成されることを特徴とする炭化ケイ素トレンチＦＥ
Ｔ。1. A first-conductivity-type drift layer of silicon carbide and a second-conductivity-type base of silicon carbide, which are successively formed on a first-conductivity-type drain layer of an alpha-phase silicon carbide single crystal and have a lower impurity concentration than the drain layer. A layer, a first conductivity type source region formed in a part of the surface layer of the second conductivity type base layer, and a trench reaching the first conductivity type drift layer from the surface of the first conductivity type source region. The gate electrode provided in the trench via the gate insulating film, the source electrode provided in contact with the surface of the first conductivity type source region, and the drain provided on the back surface of the first conductivity type drain layer. A silicon carbide tray having a (0001) plane direction in the second conductivity type base layer along the gate insulating film when a voltage is applied to the gate electrode. FE
T.
（０００１）面であることを特徴とする請求項１記載の
炭化ケイ素トレンチＦＥＴ。2. A silicon carbide trench FET according to claim 1, wherein at least one side surface of the trench is substantially a (0001) plane.
１）面に垂直な結晶面であることを特徴とする請求項２
記載の炭化ケイ素トレンチＦＥＴ。3. The main surface of the second conductivity type base layer is approximately (000
3. A crystal plane perpendicular to the 1) plane.
The silicon carbide trench FET described.
０、−１、０）面、あるいはそれと等価な結晶面である
ことを特徴とする請求項３記載の炭化ケイ素トレンチＦ
ＥＴ。4. The main surface of the second-conductivity-type base layer is substantially (1,
4. The silicon carbide trench F according to claim 3, wherein the silicon carbide trench F has a (0, -1, 0) plane or a crystal plane equivalent thereto.
ET.
１、−２、０）面、あるいはそれと等価な結晶面である
ことを特徴とする請求項３記載の炭化ケイ素トレンチＦ
ＥＴ。5. The main surface of the second-conductivity-type base layer is substantially (1,
4. The silicon carbide trench F according to claim 3, wherein the silicon carbide trench F has a (1, -2, 0) plane or a crystal plane equivalent thereto.
ET.
み第一導電型ソース領域を形成することを特徴とする請
求項３ないし５のいずれかに記載の炭化ケイ素トレンチ
ＦＥＴ。6. The silicon carbide trench FET according to claim 3, wherein the first conductivity type source region is formed only on the (0001) silicon surface side of the trench.
する面が（０００、−１）面からずれており、ゲート電
極の水平断面が突出部を有することを特徴とする請求項
２ないし６のいずれかに記載の炭化ケイ素トレンチＦＥ
Ｔ。7. The method according to claim 2, wherein the surface of the trench facing the (0001) silicon surface is offset from the (000, -1) surface, and the horizontal cross section of the gate electrode has a protrusion. Silicon carbide trench FE according to any one of
T.
する面が（０００、−１）面から３０〜９０度ずれてい
ることを特徴とする請求項７記載の炭化ケイ素トレンチ
ＦＥＴ。8. A silicon carbide trench FET according to claim 7, wherein the surface of the trench facing the (0001) silicon surface is offset from the (000, -1) surface by 30 to 90 degrees.
コン面であり、対向する側面が（０００、−１）炭素面
であり、両側面のゲート絶縁膜がほぼ同じ膜厚であるこ
とを特徴とする請求項２ないし５のいずれかに記載の炭
化ケイ素トレンチＦＥＴ。9. A trench is characterized in that one side surface is a (0001) silicon surface, the opposite side surface is a (000, -1) carbon surface, and the gate insulating films on both side surfaces have substantially the same thickness. The silicon carbide trench FET according to any one of claims 2 to 5.
上に順に形成された基板より不純物濃度の低い炭化ケイ
素の第一導電型ドリフト層と炭化ケイ素の第二導電型ベ
ース層と、その第二導電型ベース層の表面層の一部に形
成された第一導電型ソース領域と、その第一導電型ソー
ス領域の表面から第一導電型ドリフト層に達し、側面が
ほぼ（０００１）、（０００、−１）面であるトレンチ
とを有し、そのトレンチ内にゲート絶縁膜を介して設け
られたゲート電極と、第一導電型ソース領域の表面に接
して設けられたソース電極と、炭化ケイ素サブストレー
トの表面に設けられたドレイン電極とを備える炭化ケイ
素トレンチＦＥＴの製造方法において、 トレンチ内部に熱酸化により酸化ケイ素膜を形成した
後、（０００、−１）炭素面の酸化ケイ素膜を選択的に
除去し、再び熱酸化して（０００１）シリコン面と対向
する（０００、−１）炭素面のゲート絶縁膜をほぼ同じ
膜厚にすることを特徴とする炭化ケイ素トレンチＦＥＴ
の製造方法。10. A first-conductivity-type drift layer of silicon carbide and a second-conductivity-type base layer of silicon carbide, each of which has an impurity concentration lower than that of a substrate, which is sequentially formed on a first-conductivity-type silicon carbide substrate, and a second layer thereof. The first conductivity type source region formed in a part of the surface layer of the conductivity type base layer and the first conductivity type drift layer from the surface of the first conductivity type source region, and the side surfaces thereof are approximately (0001), (000 , -1) plane, and a gate electrode provided in the trench via a gate insulating film, a source electrode provided in contact with the surface of the first conductivity type source region, and silicon carbide. In a method of manufacturing a silicon carbide trench FET including a drain electrode provided on a surface of a substrate, a silicon oxide film is formed inside the trench by thermal oxidation, and then a (000, -1) carbon surface is oxidized. A silicon carbide trench FET characterized in that the silicon film is selectively removed and then thermally oxidized again so that the gate insulating film on the (000, -1) carbon surface facing the (0001) silicon surface has almost the same thickness.
Manufacturing method.
上に順に形成された基板より不純物濃度の低い炭化ケイ
素の第一導電型ドリフト層と炭化ケイ素の第二導電型ベ
ース層と、その第二導電型ベース層の表面層の一部に形
成された第一導電型ソース領域と、その第一導電型ソー
ス領域の表面から第一導電型ドリフト層に達し、側面が
ほぼ（０００１）、（０００、−１）面であるトレンチ
とを有し、そのトレンチ内にゲート絶縁膜を介して設け
られたゲート電極と、第一導電型ソース領域の表面に接
して設けられたソース電極と、炭化ケイ素サブストレー
トの表面に設けられたドレイン電極とを備える炭化ケイ
素トレンチＦＥＴの製造方法において、 トレンチ内部にＣＶＤ法により、トレンチの両側面に同
じ膜圧のゲート絶縁膜を堆積することを特徴とする炭化
ケイ素トレンチＦＥＴの製造方法。11. A first-conductivity-type drift layer of silicon carbide and a second-conductivity-type base layer of silicon carbide, each of which has an impurity concentration lower than that of a substrate, which is sequentially formed on a first-conductivity-type silicon carbide substrate, and a second layer thereof. The first conductivity type source region formed in a part of the surface layer of the conductivity type base layer and the first conductivity type drift layer from the surface of the first conductivity type source region, and the side surfaces thereof are approximately (0001), (000 , -1) plane, and a gate electrode provided in the trench via a gate insulating film, a source electrode provided in contact with the surface of the first conductivity type source region, and silicon carbide. In a method of manufacturing a silicon carbide trench FET including a drain electrode provided on a surface of a substrate, a gate insulating film having the same film pressure is deposited on both side surfaces of the trench by a CVD method inside the trench. A method of manufacturing a silicon carbide trench FET, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8065745A JPH09260650A (en) | 1996-03-22 | 1996-03-22 | Silicon carbide trench fet and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8065745A JPH09260650A (en) | 1996-03-22 | 1996-03-22 | Silicon carbide trench fet and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09260650A true JPH09260650A (en) | 1997-10-03 |
Family
ID=13295871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8065745A Pending JPH09260650A (en) | 1996-03-22 | 1996-03-22 | Silicon carbide trench fet and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09260650A (en) |
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