JP2023000604A - Insulating gate type semiconductor device and method for manufacturing insulating gate type semiconductor device - Google Patents

Abstract

To provide an insulating gate type semiconductor device that can reduce a variation in gate threshold voltage and prevent a deterioration in reliability of the semiconductor device, and a method for manufacturing an insulating gate type semiconductor device.SOLUTION: An insulating gate type semiconductor device comprises: a gate insulating film 5 that is formed of a SiO2 film and is provided on a top face of a channel formation region 3 formed of SiC; a nitrogen termination layer 6 that is provided on the interface between the channel formation region 3 and the gate insulating film 5 and obtained by terminating Si with N; and a gate electrode 7 that is provided on the gate insulating film 5 and controls the surface potential of the channel formation region 3. When measurement is conducted by SIMS in a depth direction from the surface of the gate insulating film 5, the integrated value of the concentration of C atoms from an interface defined at a peak position of the concentration of N atoms to a position where the concentration of C atoms becomes 1×1020 cm-3 or less in the gate insulating film 5 is 5×1015 cm-2 or less, and the width in the depth direction at which the concentration of N atoms becomes half the concentration of N atoms at the peak position is 2 nm or less.SELECTED DRAWING: Figure 1

Description

The present invention relates to an insulated gate semiconductor device and a method of manufacturing an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device using silicon carbide (SiC) and a method of manufacturing an insulated gate semiconductor device.

In a MOS field effect transistor (FET) using SiC, a high density interface state is generated when a gate insulating film is formed on a semiconductor layer. Therefore, there is a problem that the mobility of the channel is lowered and the electrical characteristics such as on-resistance of the MOSFET are degraded. After forming the gate insulating film, heat treatment is performed in a gas containing nitrogen (N) to form a high-concentration nitrided region at the interface between the silicon oxide (SiO ₂ ) film and the SiC layer, thereby reducing the interface state density at the interface of the gate insulating film. It is proposed to reduce (Dit) and increase the mobility. During actual use of such a MOSFET, if a positive voltage and a negative voltage are alternately applied to the gate electrode, the gate threshold voltage (Vth) will fluctuate. Therefore, the practical life of the MOSFET is limited.

Patent Document 1 discloses a technique of prescribing the ratio of the integrated value of the N atom concentration to the integrated value of the carbon (C) atom concentration in the vicinity of the interface between the SiO ₂ film and SiC in order to suppress the Vth shift. there is Specifically, the interface state density is reduced by increasing the N atom concentration in the carbon transition layer formed by the C atoms remaining in the SiO ₂ film near the interface. However, the technique of Patent Document 1 has a problem that the N atom concentration in the SiO ₂ film adjacent to the carbon transition layer also increases, generating an electron trap level, which easily causes a Vth shift accompanying driving of the MOSFET. . Patent Document 2 describes that impurities such as alkaline earth metals and C atoms are contained in the vicinity of the interface between the SiO ₂ film and SiC to suppress the leak current of the gate insulating film.

International Publication No. 2014/103186 JP 2017-204644 A

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides an insulated gate semiconductor device and a method of manufacturing an insulated gate semiconductor device that can reduce variations in gate threshold voltage and suppress deterioration in reliability of the semiconductor device. for the purpose.

To achieve the above object, one embodiment of the present invention provides (a) a gate insulating film made of a silicon oxide film provided on an upper surface of a channel formation region made of silicon carbide, and (b) a channel formation region and a gate insulator. and (c) a gate electrode provided on the gate insulating film and controlling the surface potential of the channel forming region to provide a gate insulating film. When measured by secondary ion mass spectrometry in the depth direction from the surface of the film, the carbon atom concentration in the gate insulating film is 1×10 ²⁰ cm ⁻³ or less from the interface defined by the peak position of the nitrogen atom concentration. ^Insulation in which the integrated ^value of the carbon atom concentration up to the position where the The gist is that it is a gate type semiconductor device.

Another aspect of the present invention comprises the steps of (a) forming a gate insulating film made of a silicon oxide film on the upper surface of a channel forming region made of silicon carbide; and (b) adding boron atoms to the gate insulating film. and (c) heat-treating the gate insulating film with a gas containing nitrogen atoms to form a nitride terminating layer at the interface between the channel forming region and the gate insulating film, and reducing the boron atom concentration in the gate insulating film to 1×10 ¹⁹ . cm ⁻³ or more and 5×10 ²⁰ cm ⁻³ or less; and (d) forming on the gate insulating film a gate electrode for controlling the surface potential of the channel forming region. The gist is a method for manufacturing a semiconductor device.

According to the present invention, it is possible to provide an insulated gate semiconductor device and a method for manufacturing an insulated gate semiconductor device that can reduce variations in gate threshold voltage and suppress deterioration in reliability of the semiconductor device.

1 is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to an embodiment of the present invention; FIG. It is a figure explaining the evaluation method by SIMS of an insulated gate structure. FIG. 4 is a schematic cross-sectional view for explaining an example of steps of a method for manufacturing an insulated gate semiconductor device according to Example 1 of the embodiment; FIG. 4 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 3 in the method of manufacturing the insulated gate semiconductor device according to Example 1 of the embodiment; FIG. 5 is a schematic cross-sectional view for explaining an example of a process subsequent to FIG. 4 in the method of manufacturing an insulated gate semiconductor device according to Example 1 of the embodiment; 6 is a schematic cross-sectional view for explaining an example of a process following FIG. 5 in the method of manufacturing the insulated gate semiconductor device according to Example 1 of the embodiment; FIG. FIG. 7 is a schematic cross-sectional view for explaining an example of the process subsequent to FIG. 6 in the method of manufacturing the insulated gate semiconductor device according to Example 1 of the embodiment; FIG. 10 is a schematic cross-sectional view for explaining an example of steps of a method for manufacturing an insulated gate semiconductor device according to Example 2 of the embodiment; FIG. 9 is a schematic cross-sectional view for explaining an example of a process following FIG. 8 in the method of manufacturing an insulated gate semiconductor device according to Example 2 of the embodiment; FIG. 10 is a schematic cross-sectional view for explaining an example of a step subsequent to FIG. 9 in the method of manufacturing an insulated gate semiconductor device according to Example 2 of the embodiment; 3 is a schematic cross-sectional view showing an example of an insulated gate semiconductor device according to Comparative Example 1; FIG. FIG. 10 is a diagram showing an example of SIMS measurement results near the interface of the insulated gate structure according to Example 1; FIG. 10 is a diagram showing an example of SIMS measurement results near the interface of the insulated gate structure according to Example 2; FIG. 10 is a diagram showing an example of SIMS measurement results near the interface of the insulated gate structure according to Comparative Example 1; 5 is a table showing an example of evaluation results of the insulated gate semiconductor device according to the embodiment;

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and overlapping descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may differ from the actual ones. In addition, portions having different dimensional relationships and ratios may also be included between drawings. Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention. etc. are not specified below.

In this specification, the source region of the MOS transistor is "one main region (first main region)" that can be selected as the emitter region of the insulated gate bipolar transistor (IGBT). Also, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), one of the main regions can be selected as the cathode region. The drain region of the MOS transistor is the "other main region (second main region)" of the semiconductor device which can be selected as the collector region in the IGBT and the anode region in the thyristor. In the present specification, the term “main region” simply means either the first main region or the second main region, which is appropriate from the common technical knowledge of those skilled in the art.

Further, the definitions of directions such as up and down in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. For example, if an object is observed after being rotated by 90°, it will be read with its top and bottom converted to left and right, and if it is observed after being rotated by 180°, it will of course be read with its top and bottom reversed. Further, in the following description, a case where the first conductivity type is p-type and the opposite second conductivity type is n-type will be exemplified. However, the conductivity types may be selected in the opposite relationship, so that the first conductivity type is n-type and the second conductivity type is p-type. Moreover, + and - attached to n and p mean semiconductor regions having relatively high or low impurity densities, respectively, compared to semiconductor regions not marked with + and -. However, even if the semiconductor regions are given the same n and n, it does not mean that the impurity density of each semiconductor region is exactly the same. Also, in this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

An insulated gate semiconductor device according to an embodiment of the present invention is a lateral MOSFET using an oxide film made of SiO ₂ as a gate insulating film. As shown in FIG. 1, a first conductivity type (p-type) channel forming region (base region) 3 is provided, and an inversion channel is formed on the surface of the channel forming region 3 . Above the channel forming region 3, main regions 4a and 4b of a second conductivity type (n ⁺ -type) with high impurity density, such as a source region (first main region) 4a and a drain region (second main region) 4b, are provided. It is provided selectively. An insulated gate electrode structure (5, 7) is provided on the upper surface of the channel forming region 3 across the source region 4a and the drain region 4b via a nitride termination layer 6 terminated with nitrogen (N). The insulated gate electrode structure (5, 7) is composed of a gate insulating film 5 made of SiO ₂ film and a gate electrode (control electrode) 7 on the gate insulating film 5 . The gate electrode 7 electrostatically controls the surface potential of the channel forming region 3 via the gate insulating film 5 to form an inversion channel on the surface of the channel forming region 3 .

The gate insulating film 5 of the MOSFET is an oxide film made of SiO ₂ , and is thermally oxidized by oxygen (O ₂ ) dry oxidation or wet oxidation, or by sputtering, thermal chemical vapor deposition (thermal CVD), plasma CVD, or the like. A deposited oxide can be employed. Gate insulating film 5 contains boron (B) atoms diffused by a solid diffusion source such as boron nitride (BN) in a concentration range of 1×10 ¹⁹ cm ⁻³ to 5×10 ²⁰ cm ⁻³ . As a material for the gate electrode 7, a metal film such as aluminum (Al), a polysilicon layer (doped polysilicon layer) in which an impurity such as phosphorus (P) is added at a high concentration, or the like can be used.

As shown in FIG. 1, the channel forming region 3 is provided by epitaxial growth on the substrate 1 made of an n-type SiC semiconductor. A source electrode 8a and a drain electrode 8b are provided so as to be physically in contact with the source region 4a and the drain region 4b, respectively. The source electrode 8a and the drain electrode 8b are ohmic-connected to the source region 4a and the drain region 4b, respectively. For the source electrode 8a and the drain electrode 8b, for example, a single layer film made of Al or a metal film in which nickel silicide (NiSi _x ), titanium nitride (TiN), and Al are laminated in this order can be used. Although not shown, a p ⁺ -type contact region electrically connecting the source electrode 8a and the channel forming region 3 is arranged in the channel forming region 3 separately from the source region 4a.

SiC crystals have crystal polymorphism, the main ones being cubic 3C and hexagonal 4H and 6H. The forbidden band width at room temperature is reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. Insulated gate semiconductor devices according to embodiments of the present invention will be described using 4H—SiC. In the insulated gate semiconductor device according to the embodiment, a semiconductor substrate made of SiC (SiC substrate) is used as the substrate 1 . When a SiC substrate is used, the channel forming region 3 exemplifies a structure composed of an epitaxial layer (SiC layer) made of SiC. The plane orientation of the SiC substrate is described using the (0001) plane (Si plane), but the (11-20) plane (a plane), (1-100) plane (m plane), and (000-1) plane. A plane (C plane) may also be used.

As shown in FIG. 1, in the insulated gate semiconductor device according to the embodiment, a voltage is applied to the gate electrode 7 to form an inversion layer that will serve as a channel at the interface between the gate insulating film 5 and the channel forming region 3 . At this time, by applying a voltage between the source electrode 8a and the drain electrode 8b, carriers (electrons) are injected into the channel from the source region 4a. The injected carriers run through the channel and flow into the drain region 4b.

Generally, when an oxide film used for the gate insulating film 5 is formed by thermal oxidation or the like, carbon (C) atoms remain at the interface between the oxide film and the SiC semiconductor layer, forming a high-density interface level. When electrons are trapped in the interface state, the electron mobility decreases due to Coulomb scattering or the like. A method has been proposed for reducing the interface state density by nitriding the interface between the oxide film and the SiC semiconductor layer with nitrogen atoms. However, when a high-concentration nitrided region is formed at the interface between the oxide film and the SiC semiconductor layer, N atoms increase in the oxide film near the interface. Further, after the nitriding treatment of the interface, high-temperature heat treatment at 900° C. or higher, such as contact heat treatment for reducing the contact resistance of the source electrode 8a and the drain electrode 8b and reflow heat treatment for smoothing the interlayer insulating film (not shown), is performed. is carried out. By such a high-temperature heat treatment, not only N atoms from the nitrided region but also C atoms from the SiC semiconductor diffuse into the oxide film, and defect structures (electron trap levels and hole trap levels) are formed in the oxide film. generated. Therefore, the gate threshold voltage fluctuation (Vth shift) of the semiconductor device occurs in the AC drive in which a positive voltage and a negative voltage are alternately applied to the gate electrode with reference to the potential of the source electrode.

In the insulated gate semiconductor device according to the embodiment, after B atoms are diffused and added into the oxide film forming the gate insulating film 5 , nitriding treatment is performed to form the nitride terminating layer 6 at the interface between the gate insulating film 5 and the channel forming region 3 . prepare. In the gate insulating film 5 in which B atoms are added in a concentration range of 1×10 ¹⁹ cm ⁻³ to 5×10 ²⁰ cm ⁻³ , the gate insulating film of N atoms and C atoms can be removed even by the high temperature heat treatment performed after the nitriding treatment. Diffusion into 5 can be suppressed. If the B atom concentration exceeds 5×10 ²⁰ cm ⁻³ , the electron trap level in the gate insulating film 5 will increase and the Vth shift will deteriorate. If the B atom concentration is less than 1×10 ¹⁹ cm ⁻³ , it becomes difficult to suppress diffusion of N atoms and C atoms into the gate insulating film 5 .

FIG. 2 is a schematic diagram illustrating an evaluation method by secondary ion mass spectroscopy (SIMS) near the interface of an insulated gate structure. In FIG. 2, depth on the horizontal axis is on a linear scale and concentration on the vertical axis is on a logarithmic scale. The interface between the oxide film and the SiC semiconductor layer is defined as depth 0 on the horizontal axis of FIG. The interface is defined by the peak position of the N atom concentration distribution. As shown in FIG. 2, N atoms are distributed near the interface on the SiC semiconductor layer side and the oxide film side, and C atoms are distributed so as to decrease from the SiC semiconductor layer into the oxide film. The half width d _H is the width from the interface to the position where the N atom concentration in the oxide film is 1/2 of the peak value, and can be used as a determination index for the amount of N atoms diffused into the oxide film. The transition width d is the width from the interface to the position where the C atom concentration in the oxide film is at a noise level, for example, 1×10 ²⁰ cm ⁻³ or less. The amount of C atoms remaining in can be obtained. In the embodiment, the half width d _H of the N atom concentration distribution is 2 nm or less, and the carbon (C) areal density, which is the integrated value of the C atom concentration within the transition width d of the C atom concentration distribution, is 5×10 ¹⁵ cm ^{− 2} or less, the concentrations of N atoms and C atoms in the oxide film are reduced. As a result, it is possible to suppress the generation of defect structures such as electron trap levels and hole trap levels in the oxide film, thereby suppressing gate threshold voltage fluctuations of the semiconductor device.

Further, the surface density of nitrogen (N) at the interface can be evaluated by measuring the surface of the SiC semiconductor layer from which the oxide film has been removed with an etchant such as hydrofluoric acid (HF) by X-ray electron spectroscopy (XPS). In the XPS measurement, aluminum (Al) Kα rays are used as an X-ray source, and surface analysis is performed at a detection angle of 90 degrees. The N surface density is calculated from the area intensity ratio of the XPS signals of the spectral signal (N1s signal) resulting from the 1s orbital of N atoms obtained by XPS and the spectral signal (Si2p signal) resulting from the 2p orbital of Si atoms. In the embodiment, the N surface density of the interface obtained by XPS measurement is set to 3×10 ¹⁴ cm ⁻² or more and 1×10 ¹⁵ cm ⁻² or less, thereby ensuring the N surface density necessary for reducing the interface state. ing. If the N surface density is less than 3×10 ¹⁴ cm ⁻² , the characteristics of the MOSFET are significantly degraded. The upper limit of N surface density for passivation by nitridation of the interface is about 1×10 ¹⁵ cm ⁻² . The surface density of N atoms at the interface is determined by using the _N atom concentration distribution obtained by SIMS shown in FIG. It is also possible to evaluate from the integrated value of the concentration.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing a semiconductor device according to the embodiment will be described using a lateral MOSFET as an example. The method of manufacturing the MOSFET described below is merely an example, and it is of course possible to implement various other manufacturing methods, including this modified example, within the scope of the scope of the claims. is.

(Example 1)
A method of manufacturing a MOSFET according to Example 1 will be described with reference to process drawings shown in FIGS. First, an n-type SiC substrate (substrate) 1 doped with an n-type impurity such as nitrogen (N) is prepared. The substrate 1 is a 4H-SiC substrate and has a plane orientation of (0001) plane (Si plane). First, the substrate 1 is subjected to RCA cleaning in which alkali or acid is added to hydrogen peroxide and heated to clean, treated with hydrogen fluoride (HF), and dried. A p-type channel forming region (base region) 3 is epitaxially grown on the upper surface of the substrate 1 . An n-type impurity such as N is selectively implanted from the upper surface side of the channel forming region 3 by photolithography technology, ion implantation technology, or the like. The implanted n-type impurity ions are activated by heat treatment. As a result, as shown in FIG. 3, an n ⁺ -type source region 4a and an n ⁺ -type drain region 4b are selectively buried above the channel forming region 3 .

As shown in FIG. 4, an oxide film 5a made of SiO ₂ having a thickness of about 50 nm is formed on the upper surface of the channel forming region 3 by heating at a temperature of about 1200° C. for about 160 minutes in a 100% O ₂ gas atmosphere. Although a dry oxide film is exemplified as the oxide film 5a, a wet oxide film may be used, or an oxide film deposited by thermal CVD, plasma CVD, or the like may be used. For example, the oxide film 5b may be deposited at a pressure of about 0.2 _Pa and a temperature of about _600.degree .

A solid diffusion source 20 made of a boron nitride (BN) wafer or the like is placed opposite to the upper surface of the oxide film 5a with a spacer 22 of quartz having a thickness of about 1.5 mm interposed therebetween. In an atmosphere of an inert gas such as argon (Ar) gas or nitrogen (N ₂ ) gas, heating is performed at a temperature of 900° C. or higher and 1200° C. or lower, for example, about 950° C. for about 30 minutes to form B atoms in the oxide film 5a. is diffusely added. As a result, as shown in FIG. 5, oxide film 5b containing B atoms in the range of 5×10 ²⁰ cm ⁻³ to 1×10 ²¹ cm ⁻³ is formed. Note that the B diffusion addition treatment may be performed in a gas atmosphere in which a maximum of about 10% of O ₂ gas is added to an inert gas. Alternatively, when a deposited oxide film is used, a B atom-containing gas such as diborane (B ₂ H ₆ ) or boron trichloride (BCl ₃ ) may be added to the deposition gas to deposit the oxide film 5b. .

Next, nitriding is performed by heating at a temperature of 1150° C. or higher and 1300° C. or lower, for example, about 1250° C. for about 60 minutes in a gas atmosphere in which 10% of nitrogen monoxide (NO) gas is added to N ₂ gas. By this nitriding treatment, an intermediate nitride layer 6a is formed at the interface between the oxide film 5b and the channel forming region 3, the source region 4a and the drain region 4b, as shown in FIG. Note that N ₂ O gas may be used instead of NO for the nitriding treatment. Also, by performing this step, the B atom concentration in the oxide film 5b is set in the range of 1×10 ¹⁹ cm ⁻³ to 5×10 ²⁰ cm ⁻³ .

After the nitriding process, a source contact hole and a drain contact hole are opened in the oxide film 5b by photolithography, dry etching, or the like. As a result, as shown in FIG. 7, patterns of the gate insulating film 5 and the nitride terminating layer 6 that span the source region 4a and the drain region 4b are selectively left on the upper surface of the channel forming region 3. Next, as shown in FIG.

A metal layer such as a nickel (Ni) film having a thickness of about 50 nm is deposited on the upper surfaces of the gate insulating film 5, the source contact hole, and the drain contact hole by a sputtering method, an electron beam evaporation method, or the like. The Ni metal layer is patterned using photolithography technology, RIE technology, or the like. Thereafter, rapid thermal annealing (RTA) is performed at a temperature of 900° C. or higher and 1000° C. or lower, for example, about 950° C. for about 3 minutes in an N ₂ gas atmosphere. In this manner, contact layers made of silicide (NiSi _x ) films are selectively formed on the upper surfaces of the source contact holes and the drain contact holes. A metal film such as Al having a thickness of about 100 nm is deposited by a sputtering method, a vacuum deposition method, or the like, and the Al metal film is patterned by photolithography, dry etching, or the like to form a gate electrode 7, a source electrode 8a, and a drain electrode. 8b. As a result, an insulated gate electrode structure (5, 7) is formed on the upper surface of the channel forming region 3 via the nitride terminating layer 6 so as to straddle part of the ends of the source region 4a and the drain region 4b. . Thus, the MOSFET of Example 1 is completed as the insulated gate semiconductor device according to the embodiment shown in FIG.

(Example 2)
In Example 1, B atoms are added to the gate insulating film 5 in order to suppress the diffusion of N atoms and C atoms into the oxide film. In the process, the diffusion of N atoms and C atoms is suppressed by limiting the heat treatment temperature. A method of manufacturing a MOSFET according to Example 2 will be described with reference to process drawings shown in FIGS.

First, as shown in FIG. 4, an oxide film 5a is formed on the upper surface of the channel forming region 3 in which the source region 4a and the drain region 4b are selectively buried. After that, nitriding is performed by heating at a temperature of 1150° C. or higher and 1300° C. or lower, for example, about 1250° C. for about 60 minutes in a gas atmosphere in which 10% of NO gas is added to N ₂ gas. By this nitriding treatment, an intermediate nitride layer 6a is formed at the interface between the oxide film 5a and the channel forming region 3, the source region 4a and the drain region 4b, as shown in FIG. Note that N ₂ O gas may be used instead of NO for the nitriding treatment.

After the nitriding process, a source contact hole and a drain contact hole are opened in the oxide film 5a by photolithography, dry etching, or the like. As a result, as shown in FIG. 9, patterns of the gate insulating film 5c and the nitride terminating layer 6 that span the source region 4a and the drain region 4b are selectively left on the upper surface of the channel forming region 3. Next, as shown in FIG.

A metal layer such as a Ni film having a thickness of about 50 nm is deposited on the upper surfaces of the gate insulating film 5c, the source contact hole, and the drain contact hole by a sputtering method, an electron beam evaporation method, or the like. The Ni metal layer is patterned using photolithography technology, RIE technology, or the like. After that, by performing RTA at a temperature of less than 900° C., for example, about 875° C. for about 8 minutes in an N ₂ gas atmosphere, a contact layer made of a NiSi _x film is selectively formed on the upper surface of the source contact hole and the drain contact hole. to form A metal film such as Al having a thickness of about 100 nm is deposited by a sputtering method, a vacuum deposition method, or the like, and the Al metal film is patterned by photolithography, dry etching, or the like to form a gate electrode 7, a source electrode 8a, and a drain electrode. 8b. As a result, as shown in FIG. 10, an insulated gate electrode structure (5c) is formed on the upper surface of the channel forming region 3 via the nitride terminating layer 6 so as to straddle part of the ends of the source region 4a and the drain region 4b. , 7) are formed. Thus, the MOSFET of Example 2 is completed.

<MOS interface evaluation>
For Examples 1 and 2 produced as described above, using the analysis pattern (analysis TEG) produced on the same substrate, SIMS measurement, XPS measurement and AC drive test were performed to evaluate the MOS interface characteristics. there is In order to compare with Examples 1 and 2, Comparative Example 1 was also evaluated, which was produced by a conventional manufacturing method in which a contact layer made of a NiSi _x film was formed by RTA at about 950° C. for about 3 minutes in a N ₂ gas atmosphere. doing. In Comparative Example 1, as shown in FIG. 11, the gate insulating film 5d is formed on the upper surface of the channel forming region 3 with the nitride terminating layer 6 interposed therebetween. 12 to 14 show SIMS analysis results near the SiC/SiO ₂ interface by analytical TEG of Example 1, Example 2, and Comparative Example 1, respectively. Also, FIG. 15 shows the SIMS and XPS measurement results near the interface and the evaluation results of the Vth shift amount of the MOSFET by the AC application drive test.

As shown in FIG. 12, the B atom concentration in the gate insulating film 5 of Example 1 is about 4.5×10 ²⁰ cm ⁻³ or less, and the average is about 4.5×10 ²⁰ cm ⁻³ . The diffusion of N atoms and C atoms in the oxide film near the interface between the SiC semiconductor layer and the oxide film is suppressed in Examples 1 and 2 as compared to Comparative Example 1, as shown in FIGS. It turns out that The diffusion of N atoms into the oxide film is evaluated by the half width d _H defined by the width from the interface to the position in the depth direction where the N atom concentration in the oxide film is 1/2 of the peak value. The diffusion of C atoms into the oxide film is within the transition width d defined by the width from the interface to the position where the C atom concentration in the oxide film is at the noise level, for example, 1×10 ²⁰ cm ⁻³ or less. The integrated value of the C atom concentration is evaluated as the C atom areal density.

Specifically, as shown in the table of FIG. 15, in Example 1 in which B atoms were added to the oxide film corresponding to the gate insulating film 5, the half width d _H in the N atom concentration distribution by SIMS was 0.8 nm. and decreased. Also in Example 2 in which the heat treatment temperature for forming the contact layer after the nitridation treatment was set at about 875° C., which is less than 900° C., the half-value width d _H is suppressed to about 1.8 nm, which is 2 nm or less. On the other hand, in Comparative Example 1 in which the heat treatment temperature for forming the contact layer was set at about 950° C., the half width d _H was as large as about 2.6 nm, and N atom diffusion was not suppressed. Further, as shown in the table of FIG. 15, the C atom areal density obtained from the C atom concentration distribution by SIMS is about 5.7×10 ¹⁵ cm ⁻² in Comparative Example 1, while that in Example 1 is 1.5 cm −2 . It is suppressed to about 8×10 ¹⁵ cm ⁻² and to about 4.5×10 ¹⁵ cm ⁻² in Example 2. By adding B atoms to the oxide film in this manner, diffusion of N atoms and C atoms into the oxide film can be suppressed. Also, by lowering the heat treatment temperature after the nitriding treatment, it is possible to suppress the diffusion of N atoms and C atoms into the oxide film.

In addition, using an analytical TEG, XPS measurement is performed on the surface of the SiC semiconductor layer from which the oxide film has been removed with an etching solution such as hydrofluoric acid (HF), and the N surface density of the surface of the SIC semiconductor layer, which will be the interface channel formation region, is evaluated. doing. As shown in the table of FIG. 15, both Examples 1 and 2 and Comparative Example 1 have N surface densities of about 4×10 ¹⁴ cm ⁻² and can maintain the interface characteristics.

For Examples 1 and 2 of the manufactured lateral MOSFETs, a driving test by AC voltage application is carried out to evaluate the Vth shift. AC application driving is performed by alternately applying bias voltages of +20 V and -5 V or +20 V and -10 V to the gate electrode at room temperature at a time ratio of 1:1 at a frequency of 200 kHz. The Vth shift amount is obtained from the difference between the Vth value after 2000 hours of AC application and the initial Vth value. As shown in the table of FIG. 15, the Vth shift amount due to +20 V/−5 VAC application driving is 0.1 V in Comparative Example 1, 0.06 V in Example 1, and 0.08 V in Example 2. and small. Further, the Vth shift amount due to +20 V/−10 VAC application driving is 0.2 V in Comparative Example 1, 0.1 V in Example 1, and 0.15 V in Example 2, which are small. As described above, in Examples 1 and 2, the Vth shift can be reduced, and deterioration of the reliability of the semiconductor device can be suppressed.

(Other embodiments)
Although insulated gate semiconductor devices according to embodiments of the present invention have been described above, the discussion and drawings forming part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

As described above, in the semiconductor device related to the insulated gate semiconductor device according to the embodiment, the lateral MOSFET using 4H-SiC was exemplified, but it can be applied to semiconductor devices using 6H-SiC and 3C-SiC. is also possible. Furthermore, it can also be applied to a planar gate vertical MOSFET and a trench gate vertical MOSFET.

As described above, the present invention naturally includes various embodiments and the like not described here, such as configurations in which the configurations described in the above embodiments and modifications are arbitrarily applied. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the valid scope of claims based on the above description.

1, 2... Substrate (SiC substrate)
3... Channel formation region (base region)
4a... Source region (first main region)
4b... Drain region (second main region)
5, 5c, 5d Gate insulating films 5a, 5b Oxide film 6 Nitride termination layer 6a Intermediate nitride layer 7 Gate electrode (control electrode)
8a... Source electrode 8b... Drain electrode 10... Front surface electrode 11... Back surface electrode 20... Solid diffusion source 22... Spacer

Claims (7)

a gate insulating film made of a silicon oxide film provided on the upper surface of a channel forming region made of silicon carbide;
a nitride terminating layer formed by terminating silicon with nitrogen and provided at an interface between the channel forming region and the gate insulating film;
a gate electrode provided on the gate insulating film and controlling a surface potential of the channel forming region;
with
When measured by secondary ion mass spectrometry in the depth direction from the surface of the gate insulating film, the carbon atom concentration in the gate insulating film is 1×10 ²⁰ from the interface defined by the peak position of the nitrogen atom concentration. cm ⁻³ or less, the integrated value of the carbon atom concentration is 5×10 ¹⁵ cm ⁻² or less, and the nitrogen atom concentration is 1/2 of the nitrogen atom concentration at the peak position. An insulated gate semiconductor device having a width of 2 nm or less in a vertical direction. When the gate insulating film is removed and the surface of the channel forming region at the interface is measured by X-ray photoelectron spectroscopy, the areal density of nitrogen atoms is 3×10 ¹⁴ cm ⁻² or more and 1×10 ¹⁵ cm ⁻² or less. 2. The insulated gate semiconductor device according to claim 1, wherein: 3. The insulated gate semiconductor device according to claim ¹ , wherein said gate insulating film contains boron atoms in a range of 1.times.10.sup.19 ^cm.sup. -3 to ^{5.times.10.sup.20 cm.sup.} -3. forming a gate insulating film made of a silicon oxide film on the upper surface of a channel forming region made of silicon carbide;
adding boron atoms into the gate insulating film;
heat-treating the gate insulating film with a gas containing nitrogen atoms to nitridize the gate insulating film to form a nitride terminating layer at an interface between the channel forming region and the gate insulating film; and a step of making the boron atom concentration in the range of 1×10 ¹⁹ cm ⁻³ or more and 5×10 ²⁰ cm ⁻³ or less;
and forming, on the gate insulating film, a gate electrode for controlling a surface potential of the channel forming region. When measured by secondary ion mass spectrometry in the depth direction from the surface of the gate insulating film, the carbon atom concentration in the gate insulating film is 1×10 ²⁰ from the interface defined by the peak position of the nitrogen atom concentration. cm ⁻³ or less, the integrated value of the carbon atom concentration is 5×10 ¹⁵ cm ⁻² or less, and the nitrogen atom concentration is 1/2 of the nitrogen atom concentration at the peak position. 5. The method of manufacturing an insulated gate semiconductor device according to claim 4, wherein the width in the vertical direction is 2 nm or less. When the surface of the channel formation region at the interface after removing the gate insulating film is measured by X-ray photoelectron spectroscopy, the nitrogen atom concentration is 3×10 ¹⁴ cm ⁻² or more and 1×10 ¹⁵ cm ⁻² or less. 6. The method of manufacturing an insulated gate semiconductor device according to claim 4, wherein: The insulated gate semiconductor according to any one of claims 4 to 6, wherein the boron atoms are diffused and added at a temperature of 900°C or higher and 1200°C or lower using a boron nitride wafer as a solid diffusion source. Method of manufacturing the device.

Images