JP4956904B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a voltage-driven MOS type power semiconductor device such as a MOSFET or IGBT using silicon carbide as a semiconductor material, particularly a trench type semiconductor device.

Silicon carbide semiconductors have a band gap of 4H-SiC, 3.25 eV and about 3 times larger than 1.12 eV of Si, and the electric field strength is nearly an order of magnitude larger than Si (0.3 MV / cm) (2 to 4 MV / cm). It has the characteristics. In a power semiconductor device, the on-resistance when the device is in an on state decreases in inverse proportion to the third power of the electric field strength and decreases in proportion to the reciprocal of mobility as shown in the following equation. R _DRIFT = (4BV ² ) / (μεE _CR ³ ) ・ ・ Equation (1) where BV is the withstand voltage, μ is the carrier mobility, ε is the dielectric constant of the semiconductor, and E _CR is the critical electric field strength of the semiconductor. is there. This _RDRIFT is the minimum on-resistance of the unipolar device, and the relationship between this on-resistance and the withstand voltage is called a unipolar limit.
Therefore, even if it is considered that the mobility is lower than that of Si, the on-resistance can be reduced to several hundredth of that of Si, which is expected as a next-generation power semiconductor device. To date, devices with various structures such as diodes, transistors, and thyristors have been prototyped, and some of them have been put into practical use.

FIG. 3 shows a cross-sectional view of one cell of a UMOSFET having a trench gate structure which is one form of a transistor. An n-type drift layer 2 is epitaxially grown on the n-type low resistance substrate 1, and a p-type base region 3 is further epitaxially grown. Thereafter, the source region 4 is formed by ion implantation of nitrogen (N) or phosphorus (P). Thereafter, a trench 11 is formed by a reactive ion etching method, a gate oxide film 6 is formed so as to cover the trench 11, and a gate electrode 7 is formed on the gate oxide film 6. After the gate electrode 7 is covered with the interlayer insulating film 10, the interlayer insulating film 10 is etched to open a window so that the source electrode can come into contact with the base layer 3 and the source region 4, thereby forming the source electrode 8. Finally, the drain electrode 9 is formed on the back surface of the wafer to complete the n-channel UMOSFET.
In actual operation, when the source electrode 8 is set to the ground potential in advance and a negative bias is applied to the gate electrode 7, holes are induced in the channel region 5 sandwiched between the N-type source region 4 and the N-type drift layer 2. In this n-channel MOSFET, electrons are used as conduction carriers, so no current flows. When a positive high voltage is applied to the drain electrode 9, the junction between the base region 3 and the drift layer 2 is in a reverse bias state, so that the depletion layer extends into the base region 3 and the drift layer region 2, and the current is kept low. The high voltage is maintained and this is in the off state. When a positive bias is applied to the gate electrode 7 from this state, an inverted state is brought about in which electrons are induced in the channel region 5 on the surface of the base region 3 sandwiched between the source region 4 and the drift layer 2. The region 4, the inverted channel region 5, the drift layer 2, the substrate 1, and the drain electrode 9 are turned on in this order. When a negative bias is applied again to the gate electrode, the inversion of the channel region 5 disappears, the electron flow path is cut off, and the transistor is turned off.

  The on-resistance in this on-state is the contact resistance of the source electrode, the resistance of the source region, the channel resistance of the channel region, the resistance in the thickness direction of the drift layer 2, along the current path, as shown by the arrow 13 in FIG. 1 sum of resistance and drain contact resistance. Since the channel region 5 is structurally formed on the side surface of the trench 11 in the UMOSFET, the on-resistance in the on state is the accumulation resistance when electrons move near the interface of the gate oxide film added in the planar MOSFET, and n Since there is no JFET resistance generated when the type drift layer is sandwiched between the p-type base layers, there is an advantage that the storage resistance and the JFET resistance can be reduced. Further, since there is no JFET resistance, the distance between the adjacent p-type base layers 3 can be reduced, so that there is an advantage that the cell pitch can be reduced and the on-resistance can be made smaller than that of the planar MOSFET.

Since this UMOSFET has no built-in voltage in principle, the on-voltage can be made lower than that of a bipolar device. Since it is a unipolar device, there is no accumulation in the carrier device in the on state, so switching loss is small. Further, since the voltage driving is performed by applying a small positive / negative voltage to the gate electrode to perform the on / off operation, there is an advantage that the driving circuit is simplified.
For the above reasons, in particular, in a transistor having a withstand voltage of about 1 to 2 kV, the on-resistance cannot be ignored. Therefore, a UMOSFET that can reduce the on-resistance by miniaturization is promising.
However, in the actual device, there are various resistance components as described above, and the ratio of these resistance components to the resistance of the drift layer increases as the withstand voltage decreases. Is a problem.
In addition, in the MOSFET, there is a problem that a channel resistance component represented by the following formula occupies a large proportion. _{R CH = L / {WC OX} μ n (V G -V T)} ·· formula (2) where, L is the channel length, W is the channel width, C _OX is oxide capacitance, mu _n is the movement of the carrier V _G is the gate voltage and _VT is the gate threshold voltage. From this equation (2), it is understood that R _CH is greatly affected by the electron mobility μ _n .

In a MOSFET, electrons are trapped at the trap level existing at the interface between silicon carbide and the gate oxide film, and the number of electrons actually contributing to conduction is reduced, or the mobility is increased due to Coulomb scattering by the trapped electrons. There is a problem that it falls below the bulk value. Examples of efforts to improve mobility will be described below sequentially.
First, the crystal structure and crystal plane of SiC from which a UMOSFET is fabricated will be described. FIG. 4 shows the crystal plane of hexagonal silicon carbide mainly used for the unit cell structure and the MOS interface. The main hexagonal silicon carbide includes 4H-SiC, which has a structure in which a pair of Si-C layers are stacked in the c-axis direction at a four-layer cycle, and 6H-SiC, which is stacked at a six-layer cycle. is there. 4H-SiC includes 5 layers in the unit cell of FIG. 4, and 6H-SiC includes 7 layers.
4 (a) shows that the top surface of the hexagonal column is the (0001) surface and the bottom surface is the (000-1) surface, (b) is the side surface of the hexagonal column is the (1-100) surface, and (c) is (1). (11-20) plane that is perpendicular to the (-100) plane, (d) is a 4H (03-38) plane or a plane that shares one side of the hexagon on the top surface and has an angle of 54.7 ° with the bottom surface. This surface is called the 6H (01-14) surface. Here, when describing the symbols on the lattice plane, for negative indices, a superscript bar (-) is used in numbers for crystallography, but (-) in front of the numbers because of electronic application. The sign of A plane having equivalent symmetry is represented by {}, when indicating a direction in the crystal by [], and when indicating all equivalent directions, it is represented by <>.

Currently, a silicon carbide single crystal ingot whose main surface is the (0001) plane or the (000-1) plane is bulk-grown, and the wafer is cut out and polished so that the (0001) plane and the (000-1) plane are the main surfaces. A silicon carbide wafer as a surface is produced.
Referring to the description of Non-Patent Document 1, as a result of forming a MOS interface on each crystal face of 4H-SiC and investigating the mobility of the MOSFET at that time, the effective mobility is (0001), (11 -20), (03-38) plane, respectively, than 3.8cm ² /Vs,5.4cm ² /Vs,10.6cm ² / Vs and the (0001) plane (11-20) plane and (03-38) plane It has been reported that the mobility of MOSFETs is high. This is because the (0001) plane of 4H or 6H-SiC is the Si (111) plane, the (11-20) plane of 4H or 6H-SiC, and the (1-100) plane of 4H or 6H-SiC is Si (110). ) Surface and 4H-SiC (03-38) surface or 6H-SiC (01-14) surface are described as equivalent to Si (100) surface, and even in Si, (100) surface, (110) surface The mobility is higher in the order of (111) planes. This is explained by the fact that the lower the surface density of the atoms, the lower the interface state density, the less the conduction electrons trapped in the interface states, and the less Coulomb scattering from the trapped electrons. Yes.

Assuming that these characteristics are used for SiC-UMOSFET, in Patent Document 1, the main surface is the SiC (000-1) surface, and the groove of the gate trench penetrates from the main surface to the source and base layers and penetrates to the drift layer. In addition, in the structure with the (11-20) plane as a trench sidewall and in Patent Document 2, the SiC (000-1) plane is the main surface, and the trench of the gate trench penetrates the source and base layers from the main surface to the drift layer. A structure that penetrates and has a (1-100) plane as a trench sidewall is described.
Furthermore, Patent Document 3 describes various cases in which the (11-20) plane is used as the MOS channel plane and the main surface is the (1-100) plane, (0001) plane, and (11-20) plane. Are listed.
FIG. 5 is a cross-sectional view showing the manufacturing process of the UMOSFET. First, on the n-type 4H-SiC or 6H-SiC substrate 1 (n +), 5 μm, 10 ¹⁶ cm ^-3 n-type drift layer 2 (n-), 1 μm, 10 ¹⁷ cm ^-3 are sequentially deposited by thermal CVD. A p-type base layer 3 (p), an n-type source layer 4 (n +) of 0.5 μm and 10 ¹⁹ cm ⁻³ is formed by epitaxial growth (FIG. 5A).

The substrate 1 is vertically etched by a reactive ion etching method to a depth at which the source layer 4 and the base layer 3 can be completely removed, thereby forming a trench 11 having a depth of 2.1 μm (FIG. 5 ( b)).
After forming the trench 11 in this way, a gate oxide film 6 of about 30 nm is formed. As the formation of the gate oxide film, the substrate 1 having the trench 11 formed therein is introduced into a high-temperature oxygen atmosphere, and the sidewall of the trench 11 is directly oxidized. In the case of a planar type in which a gate oxide film is formed by direct oxidation on the surface of a single crystal substrate, an oxide film is not formed on a plane having a different plane orientation, so that there is no problem of variation in oxide film. However, in the method of directly oxidizing the trench sidewall, the oxidation rate differs between the trench sidewalls having different plane orientations, so that the thickness of the formed gate oxide film varies between the sidewalls. In order to prevent this variation, as described in Non-Patent Document 2, a polycrystalline silicon film 10 is formed on the substrate surface provided with the trench 11 by the thermal decomposition of monosilane using the CVD method (FIG. 5). (c)). The deposition rate of the polycrystalline silicon film 10 is determined by the temperature of the substrate surface and does not depend on the substrate surface orientation of the growth surface. Therefore, it is possible to form a film with a uniform film thickness on the trench sidewalls having different plane orientations. Next, the polycrystalline silicon film 10 is changed to the oxide film 12 by heating in a high-temperature oxygen atmosphere of about 1000 ° C. Further, poly-Si doped with boron is deposited so as to cover the entire gate trench, thereby forming the gate electrode 7. Further, only the surface of the poly-Si gate electrode 7 is oxidized to form an oxide film as an interlayer insulating film 10. Thereafter, a part of the n-type source layer 4 is selectively removed by reactive ion etching until the p-type base layer 3 is exposed. Thereafter, a metal electrode 8 a is formed on the exposed p base layer 3. Thereafter, a metal for n source contact is formed to form the source electrode 8, and the oxide film on the back surface is removed to form the drain electrode 9. (Figure 5 (d)).
Japanese Patent Laid-Open No. 9-19724 Japanese Patent Laid-Open No. 10-247732 Japanese Unexamined Patent Publication No. 7-11016 Hiroshi Yano, Taichi Hirao, Tsuneenobu kimoto, and Hiroyuki Matsunami “Sio Itsu / SIC Interface Properties on Various Surface Orientations” ), Materials Research Society Symposium Proc. (Mat. Res. Soc. Symp. Proc., Vol.742, 2003 Materials Research Society pp.219-226) Wy. Lee, GA. A. Cooper. Junior, M. A. Capano (Y-Li, JACooper, Jr., Fellow, IEEE, and MACapano) "High-Voltage (3kV) UMOSFETs in 4H-SiC" (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.49, NO.6, JUNE 2002)

  However, unlike single crystal silicon, polycrystalline silicon is composed of many fine single crystal grains. Since the crystal axes of the single crystal particles exist with a certain distribution rather than one type, the interface between the crystal particles and the crystal particles is discontinuous. When the surface of the polycrystalline silicon was actually observed with a high-magnification scanning electron microscope or atomic force microscope (AFM), it was observed that a step was present at the crystal grain interface. That is, irregularities corresponding to the size of the crystal particles exist on the surface of the polycrystalline silicon film. This unevenness is amplified by volume expansion in the process of oxidizing the polycrystalline silicon film. In other words, it is estimated that the volume increases approximately twice in the process of silicon becoming silicon oxide, so that compressive stress acts on the interface between adjacent crystal grains, and surface irregularities are amplified in the process of relaxing this compressive stress. It is thought that it is done. In fact, in an experiment to form an oxide film having a thickness almost twice as large by oxidizing a polycrystalline silicon thin film having a thickness of 50 nm, the surface irregularities of the oxidation time (oxidation at 1000 ° C. in an oxygen atmosphere) for 1 hour and 2 hours were observed. In comparison, the result is that the surface unevenness of the material oxidized for 2 hours is approximately twice that of the material oxidized for 1 hour. The unevenness of the surface of the oxide film has a problem that the breakdown voltage is lowered when the oxide film is used as a gate oxide film.

Therefore, the present invention relates to a method of forming an oxide film on the inner surface of a trench provided on a silicon carbide single crystal substrate, and forming an amorphous silicon film having a surface irregularity of 0.3 nm to 0.4 nm on at least the inner surface of the trench. The amorphous silicon film may be a polycrystalline silicon film in a solid phase, and the polycrystalline silicon film may be oxidized to an oxide film having a surface unevenness of 3 nm to 4 nm.
The amorphous silicon film may be non-doped.
The silicon carbide single crystal substrate includes a first region of a first conductivity type, a second region of a second conductivity type, and a third region of a first conductivity type, and the trench penetrates the second region and the third region. It is preferable that the oxide film having a surface irregularity of 3 nm to 4 nm is a gate oxide film.

According to the present invention, a gate oxide film having high surface flatness and high withstand voltage can be formed regardless of the surface orientation of the trench sidewall.
In addition, the surface roughness of the oxide film obtained by depositing polycrystalline silicon (the number of surface irregularities measured by atomic force microscope (AFM) method: 10 to 200 nm) is polycrystalline. The number of irregularities on the surface of the silicon is about 10 to 200 nm, whereas the irregularity of the oxide film obtained by oxidizing the amorphous silicon obtained by the present invention can be reduced to about 3 to 4 nm. I understood.

  In the process of growing a polycrystalline silicon film, amorphous silicon that is amorphous is formed instead of polycrystalline silicon constituted by crystal grains, and the amorphous silicon is oxidized after heat treatment or the amorphous silicon is directly oxidized. This prevents the surface flatness of the oxide film from being lowered due to the unevenness corresponding to the polycrystalline silicon crystal grains.

FIG. 1 is a sectional view showing a part of a manufacturing process of a MOSFET having a trench according to an embodiment of the present invention. The process up to the trench formation in FIG. 5B and the process after the oxide film formation in FIG. In this embodiment, the process from the trench formation to the oxide film formation will be described with reference to the drawings. First, n-type 4H-SiC or 6H-SiC substrate 1 (in this embodiment, n-type 4H-SiC having a surface of 11-20 surfaces) is sequentially deposited by thermal CVD to 4.9 μm and n of 10 ¹⁶ cm ⁻³ . A drift layer 2, a 1 μm, p-type base layer ³ of 10 ¹⁷ cm ⁻³ , and an n-type source layer 4 of 0.5 μm, 10 ¹⁹ cm ⁻³ are formed by epitaxial growth. The substrate 1 is vertically etched by a reactive ion etching method to a depth at which the source layer 4 and the base layer 3 can be partially removed completely to form a trench 11 having a depth of 2.1 μm, and RCA cleaning is performed. Do. Up to this point, the process is the same as in FIG.
First, an amorphous silicon film 14 having an amorphous structure is formed to a thickness of 50 nm on the uneven substrate surface including the trench 11 at a film forming temperature of preferably 520 ° C. or less by using a low pressure CVD method (FIG. 1). (A)). The film formation conditions were a film formation temperature of 480 ° C., a film formation pressure of 70 Pa to 100 Pa (80 Pa in this example) using 20% monosilane (SiH ₄ ) gas with helium as a carrier gas. Subsequently, the amorphous silicon film is oxidized at a temperature of 1000 ° C. or less (preferably 800 ° C. to 1000 ° C.) in an atmospheric pressure atmosphere of O ₂ of 7 sccm (O ₂ is a ratio of N to 5). 14 is converted into an oxide film 15 (FIG. 1B). The subsequent steps are the same as those in FIG.

FIG. 2 is a cross-sectional view showing a part of a manufacturing process of a MOSFET having a trench, which is an example of another manufacturing process. As in the first embodiment, in this embodiment, the process from the trench formation to the oxide film formation will be described with reference to the drawings.
First, an amorphous silicon film 14 having an amorphous structure is formed to a thickness of 50 nm on the uneven substrate surface including the trench 11 at a film forming temperature of preferably 520 ° C. or less by using a low pressure CVD method (FIG. 1). (A)). The film forming conditions were a film forming temperature of 485 ° C., a film forming pressure of 70 Pa to 100 Pa (80 Pa in this example) using 20% monosilane (SiH ₄ ) gas as a carrier gas and helium as a carrier gas. Subsequently, the amorphous silicon film 14 is polycrystallized in a solid phase by baking in a nitrogen atmosphere at 800 ° C. to 900 ° C. to form a polycrystalline silicon film 16 (FIG. 2B). Subsequently, the polycrystalline silicon film 16 is converted to the oxide film 15 by oxidizing at a temperature of 1000 ° C. or lower (preferably 900 ° C. to 1000 ° C.) in an atmospheric pressure atmosphere of O ₂ of 7 sccm (FIG. 2C). . The subsequent steps are the same as those in FIG.

When a polycrystalline silicon thin film is oxidized, irregularities corresponding to crystal grains present on the surface of the polycrystalline silicon film are amplified, and the surface flatness of the oxide film is deteriorated. However, when the film is formed as an amorphous silicon film as in Example 1, since the film does not have crystal grains, the surface of the amorphous silicon film is a very flat film (measured by the AFM method). The result is a flat film of about 0.3 to 0.4 nm. The polycrystalline silicon film formed by solid-phase polycrystallizing an amorphous silicon film at a relatively low temperature of 800 ° C. to 900 ° C. as in Example 2 is also a flat surface equivalent to the amorphous silicon film ( As a result of measurement by the AFM method, the film has a flat film of about 0.3 to 0.4 nm.
In Example 1, the amorphous silicon film is oxidized at a relatively low temperature of 800 ° C. to 1000 ° C. after the formation of the amorphous silicon film. At this time, the amorphous silicon film is oxidized on the surface, but is solid below the surface. Polycrystallization occurs in the phase. For this reason, polycrystalline silicon is oxidized except for the outermost surface. In Example 2, after converting amorphous silicon into polycrystalline silicon by solid phase polycrystallization, silicon oxide is formed.

Amorphous silicon deposited to a thickness of 50 nm at 485 ° C. is oxidized at 900 ° C. and 1200 ° C., and then the surface is measured by atomic force microscopy (a method for measuring surface irregularities with a probe method). .
First, the unevenness on the surface of the oxide film was 1.13 nm in terms of the average roughness of AFM under the oxidizing condition of 900 ° C. for 1 hour without firing conditions. Similarly, 900 ° C., 2 hours 0.45 nm, 900 ° C. 5 hours 0.63 nm, 1200 ° C., 5 minutes 4.5 nm, 1200 ° C., 10 minutes 9.9 nm, 1200 ° C., 20 minutes 16.1 nm, 1200 ° C., 1 hour And 17.5 nm at 1200 ° C. for 2 hours. When the oxidation condition was 900 ° C. for 5 hours and the firing condition was 1300 ° C. for 1 hour, it was 0.66 nm. Comparing the samples with an oxidation temperature of 900 ° C. and 1200 ° C., the surface unevenness of the oxide film of the 900 ° C. sample was small (0.66 nm or less), and the surface unevenness of the oxide film of the 1200 ° C. sample was large (4.5 nm or more) . Further, even if the oxide film once oxidized at 900 ° C. is fired at 1300 ° C. for 1 hour thereafter, the surface unevenness is maintained at the same level as that of the group of samples not oxidized at 900 ° C.

The reason why the surface of the polycrystalline silicon formed by polycrystallizing the amorphous film from the solid phase at a relatively low temperature has the same flatness as the amorphous silicon film is considered as follows.
When growing polycrystalline silicon from the vapor phase, silicon atoms are first grown on a random crystal plane as a seed (or nucleus) with many irregularities on the substrate surface as seeds (or nuclei). At this time, the surface of the polycrystalline grain is two-dimensional (plane), and silicon atoms supplied from the air to the growth surface continue to grow while migrating on the growth surface of the crystal grain. In this process, since the surface of the crystal grain starting to grow is the nucleus of crystal growth, the cross section of the polycrystalline silicon grows in a columnar shape. On the other hand, in the case of polycrystallization in the solid phase of amorphous silicon, the nucleus of crystal growth is the density in the amorphous structure (unstable structure such as density fluctuation), and so on. Start from every point. For this reason, when forming polycrystalline silicon at the same temperature, polycrystalline silicon with finer crystal grains is formed from the solid phase than when formed from the vapor phase. In addition, since the density of amorphous silicon grown at a low temperature of 500 ° C. or lower is lower than that of polycrystalline silicon formed at 800 ° C., when amorphous silicon is polycrystallized in a solid phase, crystal grains The phenomenon that the grains collide with each other and the surface irregularities are amplified does not occur.

  Therefore, the surface of the silicon oxide film starting from the amorphous silicon formed according to the present invention is in a very flat state.

  It can be applied not only to power conversion devices such as inverter devices using MOSFETs and IGBTs, but also to switching elements for automotive electrical components with severe usage environments such as temperature.

Process sectional drawing which shows the manufacturing process of UMOSFET of Example 1 Process sectional drawing which shows the manufacturing process of UMOSFET of Example 2 Partial sectional view showing a conventional SiC vertical UMOSFET Explanatory drawing showing the structure and crystal plane of hexagonal silicon carbide unit cell Cross-sectional process diagram showing the conventional UMOSFET fabrication process

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon carbide substrate 2 N-type drift layer 3 Base region 4 Source region 5 Channel region 6 Gate oxide film 7 Gate electrode 8 Source electrode 9 Drain electrode 10 Interlayer insulating film 11 Trench 12 Oxide film 14 Amorphous silicon film 15 Oxide film 16 Polycrystalline silicon film

Claims (4)

In the method of forming an oxide film on the inner surface of a trench provided on a silicon carbide single crystal substrate, an amorphous silicon film having a surface irregularity of 0.3 nm to 0.4 nm is formed at least on the inner surface of the trench, and the amorphous silicon film is fixed. A method of manufacturing a silicon carbide semiconductor device, characterized in that a polycrystalline silicon film is formed in a phase, and the polycrystalline silicon film is oxidized to form an oxide film having surface irregularities of 3 nm to 4 nm. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the amorphous silicon film is non-doped.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a baking temperature for forming the amorphous silicon film in a solid phase and a polycrystalline silicon film is 900 ° C. or less. The silicon carbide single crystal substrate includes a first conductivity type first region, a second conductivity type second region, and a first conductivity type third region, and the trench penetrates the second region and the third region. 2. The silicon carbide semiconductor device formed by the manufacturing method according to claim 1, wherein the silicon carbide semiconductor device is a stripe-shaped trench gate reaching one region, and the oxide film having a surface unevenness of 3 nm to 4 nm is a gate oxide film.

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