JP3395522B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. The present invention provides a method for eliminating the adverse effect of processing strain caused by RIE and the like.
A technique for improving the breakdown voltage of a power device represented by OSFET is provided.

[0002]

2. Description of the Related Art In the process of manufacturing a semiconductor device, crystal distortion may occur on the processed surface due to the processing performed on the semiconductor substrate.

When such crystal strain cannot be ignored, the crystal layer itself having the strain is generally removed.

[0004]

[Problems to be Solved by the Invention]

(1) It may be difficult to remove the above-mentioned surface having non-negligible strain due to manufacturing restrictions of semiconductor devices, design restrictions, and the like (for example, the problem of dimensional control accuracy). In other words, there are cases where it is desired to be able to ignore the distortion of the crystal without “removing the surface”.

(2) When a trench (groove) in a vertical device such as UMOSFET is formed by RIE (reactive ion etching), etching damage occurs on the side wall portion of the trench, and therefore it must be removed. .

Further, when the trench having the vertical side wall is formed, "a sharp corner" is inevitably formed, and the voltage is concentrated at this corner, which causes another problem that the gate breakdown voltage is lowered. The details will be described below.

FIGS. 14A to 14C show an example of a conventional manufacturing process for forming a trench gate.

As shown in FIG. 14A, an etching mask 510 is formed on the semiconductor substrate 500, and then,
As shown in FIG. 14B, the trench 520 is formed by RIE.
To form. At this time, processing distortion occurs in the side wall portion 535. In addition, sharp edge portions 530 and 540 are generated. After that, a gate oxide film 600 is formed by gate oxidation, and a gate electrode and the like (not shown) are formed to complete the device (FIG. 14c).

However, in the device manufactured by the above process, the withstand voltage of the gate oxide film is considerably lowered due to the existence of the edge portions 530 and 540 having the acute angles. Further, the mobility of carriers is reduced due to the etching damage remaining on the side wall of the trench.

As a countermeasure against etching damage, a sacrificial oxide film is formed and strain is introduced into the sacrificial oxide film.
A method of removing the sacrificial oxide film is known. This method is effective in removing the damage on the side wall. However, in the ordinary sacrificial oxidation, the above-mentioned “sharp edge part” is used.
Rounding is impossible.

Therefore, in order to round a sharp edge, for example, isotropic dry etching (chemical dry etching) and sacrificial oxidation under special conditions as shown in JP-A-7-263692 are combined. , It will be necessary to carry out a method of repeating this.

However, the method disclosed in Japanese Unexamined Patent Publication No. 7-263692 is complicated, and the lateral dimension of the trench is widened due to repeated etching, which hinders miniaturization and deteriorates controllability. Furthermore, in order to round the edge portion, it is necessary to perform sacrificial oxidation at a high temperature of, for example, 1150 ° C. or higher, and this heat treatment step changes the distribution of impurities in the semiconductor substrate, which greatly limits the process.

That is, it is difficult for the conventional method to effectively realize both "removal of processing damage" and "rounding of edges" in the ultrafine device. Such problems have been clarified by the study by the inventors of the present application.

Therefore, an object of the present invention is to provide a novel method for eliminating the adverse effects of processing strain caused by RIE and the like, and to provide a novel technique suitable for rounding the sharp corners of a trench. It is in.

[0015]

(1 ) A method for manufacturing a semiconductor device according to the present invention comprises a step of forming an amorphous semiconductor layer on the surface of a semiconductor single crystal substrate having crystal distortion in the surface portion, Solid phase epitaxial growth (SPE) using the surface of the semiconductor single crystal substrate as a seed crystal part by a predetermined heat treatment.
Is generated, the amorphous semiconductor layer is made into a single crystal, and a single crystal layer that covers the distortion of the crystal is formed.

Originally, the SPE technology was SOI (Silic
Although this is a technique positioned as a method for constructing an on-on-insulator structure, the present invention uses this SPE technique for a new application. That is,
It is used to coat the surface of a strained crystal layer.

The amorphous layer can be deposited only in a desired region by a normal CVD method, can be single-crystallized by annealing at a low temperature of about 600 ° C., and can easily be a defect-free single-crystal layer (without processing damage). A single crystal layer) can be formed. Therefore, the damaged layer can be easily and reliably masked.

The solid phase epitaxial growth (SPE) used in the present invention is only the SPE in the vertical direction and is not restricted by the SPE distance in the horizontal direction (L-SPE distance).
The thickness of the defect-free single crystal layer can also be adjusted freely.

(2 ) The present invention is a semiconductor device manufactured by the above method for manufacturing a semiconductor device.

A fine semiconductor device which is not affected by processing damage is realized.

(3 ) The method of manufacturing a semiconductor device according to the present invention comprises:
Forming a groove in a part of the semiconductor single crystal substrate, and forming an amorphous semiconductor layer on the surface of the semiconductor single crystal substrate defining the cross-sectional shape of the groove and on the surface of the semiconductor substrate around the groove. A solid phase epitaxial growth (Solid Phase) using the surface of the semiconductor single crystal substrate as a seed crystal part is performed by a forming step and a predetermined heat treatment.
Epitaxy; SPE) is generated, and the amorphous semiconductor layer is monocrystallized.

[0022] In this onset bright involves the formation of trenches, for "rounding sharp edges""elimination of adverse effects of etching damage" and, using a SPE techniques.

In the SPE method, first, an amorphous semiconductor layer is formed by the CVD method. In this case, it is known that the vapor growth film is deposited with a curvature (that is, sufficiently rounded) at the corner portion of the groove. And SP
When the amorphous layer is single-crystallized by E, the single-crystal layer is formed while maintaining the shape of the vapor phase growth film having the curvature. Therefore, rounding of an acute corner portion is easily achieved. The manufacturing process is also simplified compared to the conventional method of repeating oxidation and etching.

At the same time, since a defect-free single crystal layer having no processing strain can be formed on the side wall of the groove where etching damage remains, the damage is masked and a good crystal surface is easily realized.

(4 ) The semiconductor device manufacturing method of the present invention is
Forming a groove in a part of the semiconductor single crystal substrate whose surface is a {100} plane; and the semiconductor substrate on the surface of the semiconductor single crystal substrate defining the cross-sectional shape of the groove and around the groove. Solid phase epitaxial growth (Solid Phase Epitaxy; S) using the surface of the semiconductor single crystal substrate as a seed crystal part by a step of forming an amorphous semiconductor layer on the {100} plane of
PE) to single crystallize the amorphous semiconductor layer to form a single crystal layer, and to sacrifice the surface of the single crystal layer formed by the SPE to form a sacrificial oxide film. And a step of removing the sacrificial oxide film.

In the present invention , after the SPE film is formed, the SPE film is formed.
A sacrificial oxide film is formed on the film. At this time, by performing the sacrificial oxidation by selecting the crystal plane, the oxidation at the corner portion of the groove can be promoted more than the oxidation at the side wall portion. Can be rounded.

A single crystal film formed by SPE (hereinafter,
It has been clarified by the study of the applicant of the present application that the oxidation speed of the SPE film) varies depending on the crystal plane (Japanese Patent Application No. 7-353527).

The (100) plane and planes equivalent thereto (collectively referred to as {100} planes) have the slowest oxidation speed, and the oxidation speeds of the other planes are faster than that. For example, in a plane having an inclination angle in the range of 30 to 60 degrees with respect to the (100) plane, the oxidation rate is about 1.5 than that of the (100) plane.
It will be about double. Focusing on this difference in oxidation rate, sacrificial oxidation is used for "further rounding of corners".

The "sacrificial oxidation" in the present invention is 1
The oxidation may be performed at about 000 ° C., and the conventional high temperature oxidation of 1150 ° C. or higher for rounding the edge is not required. Therefore, the fluctuation of the concentration profile of the impurity layer in the semiconductor substrate is suppressed, the controllability is good, and the element can be miniaturized.

Further, unlike the conventional case, it is not necessary to repeat the sacrificial oxidation, the process can be simplified, and the controllability of the lateral width of the groove is improved. In other words, after the SPE film is laminated, the surface is etched by the sacrificial oxidation step, which is the opposite of the conventional method of “shaving”. Therefore, it is possible to achieve a value close to the lateral width of the original groove processed by RIE. is there. That is, dimensional controllability is also improved.

[0031] (5) Oite to the onset bright, the groove is a groove having a substantially vertical sidewalls formed by anisotropic etching, also, the amorphous semiconductor layer is formed by a CVD method Is characterized by.

A method suitable for manufacturing fine transistors such as UMOSFETs is provided.

(6 ) The present invention is a semiconductor device manufactured by any of the methods described above .

A fine and highly reliable transistor is realized.

[0035] (7) The onset Oite bright, the semiconductor device is characterized by comprising a vertical insulated gate transistor.

The breakdown voltage of power devices such as UMOSFETs and IGBTs can be remarkably improved by a simplified process while preventing adverse effects on the trench profile and the concentration profile of other diffusion layers. .

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) The feature of the present embodiment is that an SPE film is formed on the surface of a semiconductor substrate having processing strain (damage) and the damage is masked.

As shown in FIG. 1, it is assumed that processing strain 12 is generated on the surface of the single crystal semiconductor substrate 10. This processing strain adversely affects the operation of devices that use the surface of a substrate, such as a MOS device, as a channel.

Therefore, first, as shown in FIG. 2, an amorphous semiconductor layer is formed on the single crystal semiconductor substrate 10, and then by the solid phase epitaxial growth in the vertical direction, the single crystal layer 16 as shown in FIG. To form.

In this case, solid phase epitaxial growth (SP
In order to effectively generate E), it is necessary to suppress the formation of a natural oxide film on the surface of the semiconductor substrate, and it is usually necessary to use an ultrahigh vacuum device such as a molecular beam epitaxial device. However, the applicant of the present application has previously proposed a method for forming an SOI structure by SPE suitable for mass production using a low pressure CVD apparatus or the like used in the production site of LSI (Japanese Patent Application No. 6-193604). ), This method is used in the present embodiment.

That is, specifically, the semiconductor substrate 10 is immersed in a dilute HF solution to remove the native oxide film on the substrate surface, and at the same time, the unbonded bonds on the surface are terminated by H (hydrogen) atoms. After activation, the single crystal semiconductor substrate 10 is loaded into a quartz tube of a low pressure CVD apparatus in a low temperature state, the temperature is raised, and a silane-based gas (for example, Si
(H ₄ gas) to flow through the quartz tube for a few mTo
Until the amorphous semiconductor layer 14 is formed under an atmosphere of rr pressure, the single crystal semiconductor substrate 10 is formed.
Prevents the natural oxide film from regrowth on the exposed surface of the
Film forming gas (eg, Si ₂ H ₆ ) after reaching the film forming temperature
Is introduced to form an amorphous semiconductor layer 14, and then heat treatment is performed at about 600 ° C. for a predetermined time to perform solid phase epitaxial growth using the surface of the single crystal semiconductor substrate 10 as a seed crystal. Then, the single crystal layer 16 is formed. This method is very low in cost because a normal low pressure CVD apparatus can be used for forming the amorphous semiconductor layer, and is excellent in mass productivity.

In this way, the processing damage layer 12 is covered by the single crystal layer 16 and can be ignored.
The thickness of the single crystal layer 16 depends on the degree of processing damage,
The damage can be set as appropriate in consideration of the subsequent movement distance.

Next, as shown in FIG. 4, the semiconductor substrate 17
A gate insulating film 18 is formed on (the substrate 10 and the single crystal layer 16 are combined to form a semiconductor substrate).

Then, as shown in FIG. 5, for example, a polysilicon gate 20 and a mask 22 are formed, arsenic ions are implanted by self-alignment, and as shown in FIG.
Impurity layers 26 and 28 are formed. As a result, the lateral MOSFET is completed.

(Second Embodiment) Next, the second embodiment of the present invention will be described.
The embodiment will be described. A feature of the present embodiment is that the SPE technique is used for "elimination of adverse effects of etching damage" and "rounding of sharp-edged portions" associated with the formation of trenches.

A detailed description will be given below with reference to FIGS. 7 to 11.

First, as shown in FIG. 7, a semiconductor substrate (N
A mask 130 is formed on the layer 100, the P layer 110, and the N layer 120.

Next, as shown in FIG. 8, a trench (U groove) 14 is formed by RIE (reactive ion etching).
Form 0.

Next, as shown in FIG. 9, an amorphous silicon layer 150 is formed by using the CVD method described in the first embodiment. This amorphous silicon layer 15
The thickness of 0 is about 0.1 μm to 0.2 μm.

It should be noted that the amorphous silicon layer 150 formed by the CVD method is deposited with a certain curvature (that is, sufficiently rounded) at the edge portions (corner portions) 170 and 180 of the grooves. It is that.

Next, as shown in FIG. 10, by annealing at 600 ° C. for a predetermined time, SPE is generated to single crystal the amorphous silicon layer 150, and the single crystal layer 15 is formed.
Form 2.

At this time, if the amorphous layer is single-crystallized by SPE, the single-crystal layer is completed while maintaining the form of the amorphous layer (vapor-phase growth film) having the above-mentioned curvature. Therefore, rounding of the corner portions (portions indicated by 171 and 180 in FIG. 10) is easily achieved. The manufacturing process is also simplified compared to the conventional method of repeating oxidation and etching.

At the same time, since the defect-free single crystal layer 152 having no processing strain can be formed on the side wall of the groove where etching damage remains, the damage is masked and a good crystal surface is easily realized.

After that, as shown in FIG. 11, an oxide film (gate insulating film) 190 is formed by thermal oxidation. At this time, since the corner portion is rounded, the influence of stress concentration is mitigated, so that the gate oxide film 190 also has a larger film thickness in the corner portion than in the flat portion.

That is, when the surface of the device of FIG. 10 is oxidized, the corner portion (reference numeral 17
The film thickness of the portion indicated by 1,180) is automatically increased as compared with the film thickness of the vertical side wall portion. As you know, M
The characteristics of the OS device are better when the thickness of the vertical side wall portion is smaller, and the reliability of the gate oxide film is higher when the thickness of the corner portion is thicker. Therefore, according to the manufacturing method described above, further improvement in the reliability of the gate oxide film can be automatically achieved.

Finally, a conductor layer 200 of polysilicon or the like is embedded in the groove. Thus, the vertical MOSFET having the N layer 120 as a source, the P layer 110 as a channel, the N layer 100 as a drain, and the conductor layer 200 as a gate.
Is completed. If a P layer is further added under the N layer 100, an IGBT (Insulated Gate B)
It is also possible to form an icolor Transistor).

In the transistor of this embodiment, since the corner portion of the groove is rounded, the electric field concentration is relieved, so that the reduction of the gate breakdown voltage is suppressed. Further, since the channel region is defect-free, carrier mobility does not decrease and on-resistance is low.

(Third Embodiment) In the present embodiment,
After forming the single crystal 152 shown in FIG. 10, a sacrificial oxide film (not shown) is formed on the surface of the single crystal 152, and the sacrificial oxide film is removed to further round the corner portion.

A single crystal film formed by SPE (hereinafter,
It has been clarified by the study of the applicant of the present application that the oxidation speed of the SPE film) varies depending on the crystal plane (Japanese Patent Application No. 7-353527).

The (100) plane and planes equivalent thereto (collectively referred to as {100} planes) have the slowest oxidation speed, and the other planes have higher oxidation rates. For example,
The oxidation rate of the surface having an inclination angle in the range of 30 to 60 degrees with respect to the (100) plane is about 1.5 times that of the (100) plane. Paying attention to this difference in oxidation rate, sacrificial oxidation
It is used for "further rounding of corners".

Regarding this, FIGS. 12 (a) to 12 (c)
Will be explained.

As shown in FIG. 12A, an insulating layer 121 for forming a step is formed on a semiconductor substrate 111 whose main surface is the (100) plane, and then an SPE film 131 is formed by the above method. Form. In this case, for example, the (110) plane is exposed at the slope portion of the step portion (A).

Next, as shown in FIG. 12B, SPE
When the surface of the film 131 is thermally oxidized, the stress is relieved due to the corners being rounded in the SPE film, so that the oxidation is further promoted at the step. That is, {1
The (00) plane has the slowest oxidation speed, and the (110) plane and the like are rapidly oxidized. Therefore, the film thickness of the step portion of the oxide film 151 is thicker than that of the flat portion.

Therefore, when the oxide film 151 is removed,
As shown in FIG. 12C, the stepped portion (a) is further rounded.

As a reference, in FIG. 13, a base oxide film having a film thickness of 500 nm is formed, and the width of the base oxide film is 0.4 to 3.0.
An opening of μm is formed and the film thickness is 600 nm by SPE method.
Of the semiconductor single crystal layer of 1.0 μm
m oxidation, the oxide film is removed with an HF solution, and 100n again
m oxide film is formed, and finally S is formed by the plasma CVD method.
The result of SEM (scanning electron microscope) observation of the shape of the single crystal layer after forming the iN film is shown. As shown in FIG. 12B, it can be seen that the film thickness of the oxide film is thick at the step portion.

Therefore, when the sacrificial oxide film is formed in the state shown in FIG. 10 and then the sacrificial oxide film is removed, the corner portion 171 is further rounded. Therefore, the gate breakdown voltage of the transistor is further improved.

The sacrificial oxidation in the present embodiment is
The oxidation may be performed at about 1000 ° C., and the conventional high temperature oxidation of 1150 ° C. or higher for rounding the edge portion is not necessary. Therefore, the fluctuation of the concentration profile of the impurity layer in the semiconductor substrate is suppressed, the controllability is good, and the element can be miniaturized.

Further, unlike the prior art, it is not necessary to repeat the sacrificial oxidation, the process can be simplified, and the controllability of the lateral width of the groove is improved. In other words, after the SPE film is laminated, the surface is etched by the sacrificial oxidation step, which is the opposite of the conventional method of “shaving”. Therefore, it is possible to achieve a value close to the lateral width of the original groove processed by RIE. is there. That is, dimensional controllability is also improved.

[0070]

[Brief description of drawings]

FIG. 1 is a sectional view of a device showing a first manufacturing step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a device showing a second manufacturing step of the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a sectional view of a device showing a third manufacturing step of the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 4 is a cross-sectional view of the device showing a fourth manufacturing step of the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a cross-sectional view of the device showing the fifth manufacturing step of the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a cross-sectional view of the device showing the sixth manufacturing step of the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 7 is a cross-sectional view of the device showing a first manufacturing step of the method for manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 8 is a sectional view of a device showing a second manufacturing step of the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a sectional view of a device showing a third manufacturing step of the method for manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 10 is a cross-sectional view of the device showing a fourth manufacturing step of the method for manufacturing the semiconductor device according to the second embodiment of the invention.

FIG. 11 is a sectional view of a device showing a fifth manufacturing step of the method for manufacturing the semiconductor device according to the second embodiment of the invention.

12 (a) to 12 (c) are views for explaining the features of the third embodiment of the present invention.

FIG. 13 is a scanning electron micrograph of an SOI device using SPE.

14A to 14C are views for explaining a conventional manufacturing process for forming a trench gate, respectively.

[Explanation of symbols]

10 Semiconductor substrate 12 Processing strain 14 Amorphous layer 16 Single crystal layer formed by SPE 17 board 18 Gate insulation film 20 Polysilicon gate 22,24 Ion implantation mask

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-61254 (JP, A) JP-A 5-152321 (JP, A) JP-A 61-229317 (JP, A) JP-A 62- 105476 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (4)

(57) [Claims] 1. A step of forming a groove in a part of a semiconductor single crystal substrate, and a surface of the semiconductor single crystal substrate defining a sectional shape of the groove and a surface of the semiconductor substrate around the groove. A step of forming an amorphous semiconductor layer and a predetermined heat treatment, solid phase epitaxial growth (Solid P) using the surface of the semiconductor single crystal substrate as a seed crystal part.
hase Epitaxy; SPE) brought occur, the amorphous semiconductor layer possess a step of single crystal, the substantially vertical the groove formed by anisotropic etching
It is a groove with straight sidewalls, and the amorphous semiconductor
A method of manufacturing a semiconductor device, wherein the body layer is formed by a CVD method. 2. A step of forming a groove in a part of a semiconductor single crystal substrate whose surface is a {100} plane, and a step of defining a cross-sectional shape of the groove on the surface of the semiconductor single crystal substrate and in the groove. A step of forming an amorphous semiconductor layer on the {100} plane of the semiconductor substrate in the surroundings, and a solid phase epitaxial growth (Solid P) using the surface of the semiconductor single crystal substrate as a seed crystal part by a predetermined heat treatment.
phase epitaxy (SPE) to form a single crystal layer by single crystallizing the amorphous semiconductor layer, and sacrificing the surface of the single crystal layer formed by the SPE to form a sacrificial oxide film, Thereafter, possess removing the sacrificial oxide film, a substantially vertical the groove formed by anisotropic etching
It is a groove with straight sidewalls, and the amorphous semiconductor
A method of manufacturing a semiconductor device, wherein the body layer is formed by a CVD method. 3. A semiconductor device manufactured by using the method according to claim 1 . 4. The semiconductor device according to claim 3, wherein the semiconductor device includes a vertical insulated gate transistor.