CN105655255A - Preparation method of strained germanium device - Google Patents
Preparation method of strained germanium device Download PDFInfo
- Publication number
- CN105655255A CN105655255A CN201510947001.1A CN201510947001A CN105655255A CN 105655255 A CN105655255 A CN 105655255A CN 201510947001 A CN201510947001 A CN 201510947001A CN 105655255 A CN105655255 A CN 105655255A
- Authority
- CN
- China
- Prior art keywords
- preparation
- germanium
- source
- substrate
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 38
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 230000006698 induction Effects 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims description 15
- 238000002513 implantation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 abstract description 4
- 230000008025 crystallization Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000348 solid-phase epitaxy Methods 0.000 abstract 2
- 238000005280 amorphization Methods 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 239000007787 solid Substances 0.000 description 10
- 238000000407 epitaxy Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
Classifications
-
- H01L29/66477—
-
- H01L29/7848—
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a preparation method of a strained germanium device, and belongs to the field of the semiconductor device manufacturing technology. According to the preparation method, pre-amorphization is performed on the surface of source and drain regions through ion injection and tensile strain induction elements are injected in the source and drain regions, and then annealing of a substrate is performed so that solid phase epitaxy of amorphous regions and then crystallization are enabled to be performed. The solid phase epitaxy method is adopted and diffusion of the strain induction atoms can be suppressed and then the strain induction atoms are enabled to be distributed at the surface in a concentrated way so that the composition of the tensile strain induction elements in the source and drain regions can be enhanced, and strain in channels can be increased. Besides, the preparation method is compatible with the existing technology and can be used for the technological base of the strained germanium MOS device.
Description
Technical field
The present invention relates to the preparation method of a kind of strained Germanium device, belong to process for fabrication of semiconductor device field.
Background technology
Along with device size constantly reduces, in silicon-based devices, carrier mobility degenerate problem is day by day serious, it is necessary to explores novel material, new texture and novel process and improves device performance. Germanium material is subject to extensive concern owing to possessing higher carrier mobility. In order to improve the mobility of current carrier in germanium base MOS device raceway groove further, it is possible to adopt the material different from sige lattice constant at source and drain areas, thus introduce stress in channels. In germanium base nmos device, by being less than the element of germanium in source and drain areas injection lattice parameter, it is possible to introduce single shaft tension stress in channels, thus improve the mobility of electronics in raceway groove.
But the strain size that conventional ion method for implanting is introduced in channels, by the restriction of impurity solid solubility in germanium, especially carbon, in germanium, solid solubility is extremely low, annealing process easily precipitates out, thus the Substitutional carbon content obtained is lower, and the strain of introducing is also less, thus have impact on the lifting of device performance.
Summary of the invention
In order to overcome the above problems, the present invention proposes the preparation method of a kind of strained Germanium device, and the method can improve the component of tensile strain induction element in source and drain areas, and the stress in raceway groove is increased, and with existing process compatible, it is possible to for the Process ba-sis of strained Germanium MOS device.
The concrete technical scheme of the present invention is as follows:
1. a preparation method for strained Germanium device, it specifically comprises the steps:
1) selecting germanium base substrate, substrate surface forms grid structure;
2) source and drain areas is carried out first time ion implantation, form amorphous layer;
3) source and drain areas carrying out second time ion implantation, introducing tensile strain induction element, second time injects the amorphous layer thickness that the degree of depth is less than first time ion implantation formation;
4) before or after source and drain is adulterated, germanium base substrate is annealed, make non-crystalline areas be converted into monocrystalline;
5) carry out subsequent technique, complete the preparation of MOS device.
For NMOS preparation, described germanium base substrate is P type, and substrate can be that germanium substrate, silicon base epitaxial Germanium substrate or germanium cover insulating substrate, but is not limited to above-mentioned materials, it is also possible to is the substrate that epitaxial germanium layer is contained on any surface.
Described grid structure comprises gate medium and gate electrode.
Described first time ion implantation, injecting element is Ge element, and implantation dosage is 1 �� 1013cm-2��1 �� 1016cm-2, injecting energy should determine according to required amorphous layer thickness.
Described second time ion implantation, injecting element can be the tensile strain induction elements such as C, Si, and implantation dosage is 1 �� 1013cm-2��5 �� 1016cm-2, inject energy relevant to raceway groove strained layer thickness, inject the amorphous layer thickness that the degree of depth should be less than first time ion implantation formation.
Wherein, annealing temperature is 300��700 DEG C, and annealing time should determine according to the crystallization rate of amorphous layer thickness and solid epitaxy.
Advantage of the present invention is as follows:
First source drain region surface is undertaken pre-amorphous by ion implantation by the present invention, and injects tensile strain induction element in source and drain areas, is then annealed by substrate, makes non-crystalline areas solid epitaxy recrystallize. Solid epitaxy method can suppress the diffusion of strain inducing atom so that it is integrated distribution is on surface, thus improves the component of tensile strain induction element in source and drain areas, and the stress in raceway groove is increased.
It is simple that the present invention injects the method technique with solid epitaxy by coupled ion, is easy to operation, it is possible to compatible with existing CMOS technology.
Accompanying drawing explanation
Fig. 1��Fig. 5 is the schema of preparation method's specific embodiment of the strained Germanium device adopting the present invention to propose.
Wherein: 1 germanium substrate; 2 gate mediums; 3 gate electrodes; 4 amorphous layers; 5 C injection zones; 6-GeC alloy; 7 source and drain; 8 side walls; 9 metal interconnecting wires; 10 isolation.
Embodiment
The method injects the method with solid epitaxy by coupled ion, first by ion implantation, germanium base substrate is carried out non-crystallization, then injects strain inducing element, is finally annealed by substrate, thus realize solid epitaxy, make non-crystalline areas be converted into monocrystalline. The method can improve the component of strain inducing element, thus the stress in raceway groove is increased, and the method technique is simple, is easy to operation, it is possible to compatible with existing CMOS technology.
For germanium substrate, the strained Germanium device preparation method that the present invention proposes is as follows:
Step 1. provides germanium substrate 1, and germanium substrate 1 surface is formed with grid structure, and grid structure comprises gate medium 2 and gate electrode 3, as shown in Figure 1.
Source and drain areas is carried out first time ion implantation by step 2., and as shown in Figure 2, injection element is Ge, and implantation dosage is 1 �� 1014cm-2, injection energy is 40keV, forms amorphous layer 4, and amorphous layer 4 thickness is about 40nm.
Source and drain areas is carried out second time ion implantation by step 3., and injection element is C, and implantation dosage is 1 �� 1015cm-2, injection energy is 7keV, forms C injection zone 5, the C injection degree of depth and is about 30nm, as shown in Figure 3.
Germanium substrate 1 is annealed by step 4., and annealing temperature is 500 DEG C, and annealing time is 300s, completes the solid epitaxy of GeC alloy 6, as shown in Figure 4.
Step 5. carries out subsequent technique, completes the preparation of germanium base tensile strain nmos pass transistor, formed source and drain 7, side wall 8, metal interconnecting wires 9 and and device layer between isolation 10, as shown in Figure 5.
Germanium substrate is carried out annealing and can carry out before or after source and drain is adulterated by the present invention, and annealing time should determine according to the crystallization rate of amorphous layer thickness and solid epitaxy.
Embodiment described above is not intended to limit the present invention, the technician of any this area, without departing from the spirit and scope of the present invention, all can utilize aforesaid method and technology contents that technical solution of the present invention is made many possible amendments and retouching. Therefore, every content not departing from technical solution of the present invention, the technical spirit of foundation the present invention, to any equivalent variations made for any of the above embodiments or modification, all still belongs to the covering scope of technical solution of the present invention.
Claims (5)
1. the preparation method of a strained Germanium device, it is characterised in that, specifically comprise the steps:
1) selecting germanium base substrate, substrate surface forms grid structure, and grid structure both sides are formed with side wall;
2) source and drain areas is carried out first time ion implantation, form amorphous layer;
3) source and drain areas carrying out second time ion implantation, introducing tensile strain induction element, second time injects the amorphous layer thickness that the degree of depth is less than first time ion implantation formation;
4) before or after source and drain is adulterated, germanium base substrate is annealed, make non-crystalline areas be converted into monocrystalline;
5) carry out subsequent technique, complete the preparation of MOS device.
2. preparation method as claimed in claim 1, it is characterised in that, described germanium base substrate is that germanium substrate, silicon base epitaxial Germanium substrate or germanium cover insulating substrate.
3. preparation method as claimed in claim 1, it is characterised in that, step 2) in, described first time the injection element of ion implantation be Ge element, implantation dosage is 1 �� 1013cm-2��1 �� 1016cm-2��
4. preparation method as claimed in claim 1, it is characterised in that, step 3) in, described second time ion implantation, injection element is C or Si, and implantation dosage is 1 �� 1013cm-2��5 �� 1016cm-2��
5. preparation method as claimed in claim 1, it is characterised in that, step 4) in, annealing temperature is 300��700 DEG C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510947001.1A CN105655255A (en) | 2015-12-17 | 2015-12-17 | Preparation method of strained germanium device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510947001.1A CN105655255A (en) | 2015-12-17 | 2015-12-17 | Preparation method of strained germanium device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105655255A true CN105655255A (en) | 2016-06-08 |
Family
ID=56476627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510947001.1A Pending CN105655255A (en) | 2015-12-17 | 2015-12-17 | Preparation method of strained germanium device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105655255A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257917A (en) * | 2016-12-28 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09307101A (en) * | 1996-05-15 | 1997-11-28 | Toyota Central Res & Dev Lab Inc | Semiconductor device and its manufacture |
| WO2007112432A3 (en) * | 2006-03-28 | 2009-03-26 | Ibm | Epitaxy of silicon-carbon substitutional solid solutions by ultra-fast annealing of amorphous material |
| TW200945448A (en) * | 2008-04-21 | 2009-11-01 | United Microelectronics Corp | Semiconductor device and method for manufacturing the same |
| CN101577229A (en) * | 2008-05-06 | 2009-11-11 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN102931222A (en) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
-
2015
- 2015-12-17 CN CN201510947001.1A patent/CN105655255A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09307101A (en) * | 1996-05-15 | 1997-11-28 | Toyota Central Res & Dev Lab Inc | Semiconductor device and its manufacture |
| WO2007112432A3 (en) * | 2006-03-28 | 2009-03-26 | Ibm | Epitaxy of silicon-carbon substitutional solid solutions by ultra-fast annealing of amorphous material |
| TW200945448A (en) * | 2008-04-21 | 2009-11-01 | United Microelectronics Corp | Semiconductor device and method for manufacturing the same |
| CN101577229A (en) * | 2008-05-06 | 2009-11-11 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN102931222A (en) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257917A (en) * | 2016-12-28 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102511081B (en) | For the formation of the method and structure of high performance field effect transistors with embedment stress source | |
| CN101322228B (en) | Technique for reducing crystal defects in strained transistors by tilted preamorphization | |
| US8551845B2 (en) | Structure and method for increasing strain in a device | |
| US7767540B2 (en) | Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility | |
| CN103094207A (en) | Method of manufacturing semiconductor device using stress memorization technique | |
| US8633096B2 (en) | Creating anisotropically diffused junctions in field effect transistor devices | |
| JP2006019727A (en) | Strained p-type metal oxide semiconductor field effect transistor (mosfet) structure having slanted, incorporated silicon-germanium source-drain and/or extension, and manufacturing method for the same | |
| WO2006074438A1 (en) | Device with stepped source/drain region profile | |
| CN102906880A (en) | Delta monolayer dopant epitaxy for embedded source/drain silicide | |
| CN100527370C (en) | Method for manufacturing metal-oxide-semiconductor transistor | |
| US20160020153A1 (en) | Method to fabricate a transistor wherein the level of strain applied to the channel is enhanced | |
| US8273642B2 (en) | Method of fabricating an NMOS transistor | |
| US7952122B2 (en) | Strained semiconductor device and method of making same | |
| CN105702582A (en) | Formation method of transistor | |
| CN102110710A (en) | Semiconductor structure with channel stress layer and forming method thereof | |
| CN202633241U (en) | Transistor with a metal gate electrode | |
| US20130277685A1 (en) | Soi transistors with improved source/drain structures with enhanced strain | |
| US20110097868A1 (en) | Method for fabricating p-channel field-effect transistor (fet) | |
| CN105655255A (en) | Preparation method of strained germanium device | |
| CN104916540B (en) | A kind of strained channel transistor and preparation method thereof | |
| CN103943504A (en) | Semiconductor device and manufacturing method thereof | |
| US20080206965A1 (en) | STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY | |
| CN105575810B (en) | The forming method of transistor | |
| US20130052783A1 (en) | Methods of Forming Stressed Silicon-Carbon Areas in an NMOS Transistor | |
| CN202633240U (en) | Transistor with a metal gate electrode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160608 |