JP2021086896A - Insulated gate type semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide an insulated gate type semiconductor device and a manufacturing method thereof that can reduce the interface state density and suppress the deterioration of reliability of a semiconductor device.SOLUTION: A manufacturing method of an insulated gate type semiconductor device includes the steps of forming a gate insulating film made of a silicon oxide film on the upper surface of a channel forming region made of silicon carbide, nitriding the gate insulating film by heat-treating the gate insulating film with gas containing nitrogen atoms to form an intermediate nitride layer at the interface between the channel forming region and the gate insulating film, heat-treating the gate insulating film with gas containing carbon dioxide to remove some of nitrogen atoms in the gate insulating film and form a nitriding terminal layer at the interface, and forming a gate electrode that controls the surface potential of the channel forming region on the gate insulating film.SELECTED DRAWING: Figure 1

Description

The present invention relates to a method for manufacturing an insulated gate type semiconductor device and an insulated gate type semiconductor device, and more particularly to a method for manufacturing an insulated gate type semiconductor device and an insulated gate type semiconductor device using silicon carbide (SiC).

In a MOS field effect transistor (FET) using SiC, a high-density interface state is formed when a gate insulating film is formed on a semiconductor layer. Therefore, there is a problem that the mobility of the channel becomes low and the electrical characteristics such as the on-resistance of the MOSFET deteriorate. After forming the gate insulating film, heat treatment is performed in a gas containing nitrogen (N) _{to form a high-concentration nitrided region at the interface between the silicon oxide (SiO 2} ) film and the SiC, thereby forming the interface state density (interface level density) at the interface of the gate insulating film. It has been proposed to reduce Dit) and increase the mobility. However, there is a problem that the operational reliability of the semiconductor device cannot be ensured depending on the driving conditions due to the negative bias temperature instability (NBTI) in which the gate threshold voltage, which is the on-off voltage of the device, fluctuates with respect to the stress applied to the negative bias. There is. Non-Patent Document 1 points out the possibility of hole trap generation by nitrogen atoms entering the _{SiO 2} film, which is a gate insulating film, as a cause of the problem of NBTI.

Patent Document 1 discloses a technique for defining the N concentration in the vicinity of the _{SiO 2} film and the SiC interface in order to improve NBTI. Specifically, the position where the oxygen (O) concentration is _{90% of the O concentration in the SiO 2} film is defined as the interface, and the N concentration contained in the region ± 5 nm from the interface is defined as 5 × 10 ¹³ cm- ² . High, 1.6 x 10 ¹⁴ cm ^-less than -2. However, in the technique of Patent Document 1, since the amount of N atoms contributing to the passivation of the interface is reduced, the nitriding effect is not sufficient, the channel mobility is lowered, and the positive bias temperature instability (PBTI) is a problem. Become.

Japanese Unexamined Patent Publication No. 2011-82454

J. Rosen et al., "Increase in oxide hole trap density associated with nitrogen incorporation at the SiO2 / SiC interface", Journal of Applied Physics (J. Appl. Phys.), Vol. 103, 2008, p. 124513

In view of the above problems, the present invention provides an insulated gate type semiconductor device and a method for manufacturing an insulated gate type semiconductor device, which can reduce the interface state density and suppress deterioration of the reliability of the semiconductor device. The purpose is.

In order to achieve the above object, one aspect of the present invention includes (a) a step of forming a gate insulating film made of a silicon oxide film on the upper surface of a channel forming region made of silicon carbide, and (b) a gas containing a nitrogen atom. By heat-treating the gate insulating film in the above step, the interface between the gate insulating film and silicon carbide is nitrided to form an intermediate nitride layer at the interface between the channel forming region and the gate insulating film, and (c) carbon dioxide. By heat-treating the gate insulating film with a gas containing the above, a part of the nitrogen atom in the gate insulating film is removed to form a nitriding terminal layer at the interface, and (d) channel formation on the gate insulating film. The gist of the present invention is a method of manufacturing an insulated gate type semiconductor device including a step of forming a gate electrode for controlling the surface potential of the region.

Another aspect of the present invention is provided at the interface between (a) a gate insulating film made of a silicon oxide film provided on the upper surface of a channel forming region made of silicon carbide and (b) a channel forming region and a gate insulating film. It is provided with a nitride termination layer made of silicon nitride and (c) a gate electrode provided on the gate insulating film and controlling the surface potential of the channel forming region, and X-rays the interface between the gate insulating film and silicon carbide. when measured by photoelectron spectroscopy, the ratio I _N / I _Si of the spectrum of the intensity I _Si due to the 2p orbital of the silicon from the intensity I _N and the channel formation region of the spectrum due to the 1s orbital of nitrogen, the gate When the insulating film is left with a film thickness between 2 nm and 3 nm from the interface, it is 0.02 or more and less than 0.03, and when the gate insulating film is removed, the nitride terminal layer is larger than 0.01 and 0. The gist is that the insulating gate type semiconductor device is less than .02.

According to the present invention, it is possible to provide an insulated gate type semiconductor device and a method for manufacturing an insulated gate type semiconductor device, which can reduce the interface state density and suppress deterioration of the reliability of the semiconductor device.

It is sectional drawing which shows an example of the insulated gate type semiconductor device which concerns on embodiment of this invention. It is sectional drawing for demonstrating an example of the process of the manufacturing method of the MOS capacitor used for the evaluation of the insulating gate structure which concerns on embodiment. FIG. 5 is a schematic cross-sectional view for explaining an example of a step following FIG. 2 of a method for manufacturing a MOS capacitor used for evaluating an insulated gate structure according to an embodiment. FIG. 5 is a schematic cross-sectional view for explaining an example of a step following FIG. 3 of a method for manufacturing a MOS capacitor used for evaluating an insulated gate structure according to an embodiment. FIG. 5 is a schematic cross-sectional view for explaining an example of a step following FIG. 4 of a method for manufacturing a MOS capacitor used for evaluating an insulated gate structure according to an embodiment. It is sectional drawing which shows an example of the MOS capacitor of the comparative example 1. FIG. It is a figure which shows an example of the XPS spectrum of Si2p used for the evaluation of the vicinity of the interface of a MOS gate structure. It is a figure which shows an example of the XPS spectrum of N1s used for the evaluation of the vicinity of the interface of a MOS gate structure. It is a figure which shows an example of the analysis result of the XPS intensity ratio near the interface of the insulating gate structure which concerns on embodiment. It is a table which shows an example of the evaluation result of the insulation gate structure which concerns on embodiment. It is sectional drawing for demonstrating an example of the process of the manufacturing method of the insulated gate type semiconductor device which concerns on embodiment. It is sectional drawing for demonstrating an example of the process following FIG. 11 of the manufacturing method of the insulated gate type semiconductor device which concerns on embodiment. It is sectional drawing for demonstrating an example of the process following FIG. 12 of the manufacturing method of the insulated gate type semiconductor device which concerns on embodiment. It is sectional drawing for demonstrating an example of the steps following FIG. 13 of the manufacturing method of the insulated gate type semiconductor device which concerns on embodiment. It is sectional drawing for demonstrating an example of the process following FIG. 14 of the manufacturing method of the insulated gate type semiconductor device which concerns on embodiment. It is sectional drawing for demonstrating an example of the steps following FIG. 15 of the manufacturing method of the insulated gate type semiconductor device which concerns on embodiment. It is sectional drawing which shows an example of the insulated gate type semiconductor device of the comparative example 2. FIG. It is a table which shows an example of the evaluation result of the insulated gate type semiconductor device which concerns on embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are designated by the same or similar reference numerals, and duplicate description will be omitted. However, the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. may differ from the actual ones. In addition, parts having different dimensional relationships and ratios may be included between the drawings. In addition, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention describes the material, shape, structure, and arrangement of constituent parts. Etc. are not specified as the following.

In the present specification, the source region of the MOS transistor is a “one main electrode region (first main electrode region)” that can be selected as the emitter region of the insulated gate bipolar transistor (IGBT). Further, in a thyristor such as a MOS-controlled electrostatic induction thyristor (SI thyristor), one of the main electrode regions can be selected as a cathode region. The drain region of the MOS transistor is the “other main electrode region (second main electrode region)” of the semiconductor device, which can be selected as the collector region in the IGBT and the anode region in the thyristor. In the present specification, the term "main electrode region" simply means either the first main electrode region or the second main electrode region, which is appropriate from the common general technical knowledge of those skilled in the art.

Further, the definition of the vertical direction in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present invention. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read. Further, in the following description, the case where the first conductive type is the p-type and the second conductive type, which is the opposite of the p-type, is the n-type will be exemplified. However, the conductive type may be selected in the opposite relationship, the first conductive type may be the n type, and the second conductive type may be the p type. Further, + and-attached to n and p mean that the impurity density is relatively high or low, respectively, as compared with the semiconductor region to which + and-are not added. However, even if the semiconductor regions have the same n and n, it does not mean that the impurity densities of the respective semiconductor regions are exactly the same. Further, in the present specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and "-" is added before the index to represent a negative index.

The insulated gate type semiconductor device according to the embodiment of the present invention is a horizontal MOSFET in which a _{silicon oxide film (SiO 2) film is used as the gate insulating film.} As shown in FIG. 1, a first conductive type (p type) channel forming region (base region) 3 is provided, and an inverted channel is formed on the surface of the channel forming region 3. In the upper part of the channel formation region 3, a second conductive type (n ⁺ type) main electrode region 4a and 4b having a high impurity density, for example, a source region (first main electrode region) 4a and a drain region (second main electrode region) ) 4b is selectively provided. An insulated gate type electrode structure (5, 7) is provided on the upper surface of the channel forming region 3 across the source region 4a and the drain region 4b via a nitriding termination layer 6 terminated with nitrogen (N). The insulated gate type electrode structure (5, 7) is _{composed of a gate insulating film 5 made of a SiO 2} film and a gate electrode (control electrode) 7 on the gate insulating film 5. The gate electrode 7 electrostatically controls the surface potential of the channel forming region 3 via the gate insulating film 5 to form an inverted channel on the surface of the channel forming region 3.

The nitriding terminal layer 6 is a nitrogen terminating layer provided by nitriding the interface between the gate insulating film 5 and the channel forming region 3 and then _{heat-treating with carbon dioxide (CO 2) gas. As the silicon oxide film (SiO 2} film) which is the gate insulating film 5 of the MOSFET, a thermal oxide film such as oxygen (O ₂ ) dry oxidation or wet oxidation, or sputtering, thermochemical vapor deposition (CVD), plasma CVD, etc. Deposited oxide film can be adopted. As the material of the gate electrode 7, a metal film such as aluminum (Al), a polysilicon layer (doped polysilicon layer) in which impurities such as phosphorus (P) are added at a high concentration, and the like can be used.

As shown in FIG. 1, the channel formation region 3 is formed by epitaxially growing on a substrate 1 made of an n-type SiC semiconductor. Further, the source electrode 8a and the drain electrode 8b are provided so as to be in physical contact with the source region 4a and the drain region 4b, respectively. The source electrode 8a and the drain electrode 8b are ohmic-connected to the source region 4a and the drain region 4b, respectively. As the source electrode 8a and the drain electrode 8b, for example, a single-layer film made of Al or a metal film in which nickel silicide (NiSi _x ), titanium nitride (TiN), and Al are laminated in this order can be used. ^{Although not shown, a p +} type contact region that electrically connects the source electrode 8a and the channel forming region 3 is separated from the source region 4a and arranged in the channel forming region 3.

Crystal polymorphs exist in SiC crystals, and the main ones are cubic 3C and hexagonal 4H and 6H. Forbidden band widths at room temperature have been reported to be 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the insulated gate type semiconductor device according to the embodiment of the present invention, 4H-SiC will be used for description. In the insulated gate type semiconductor device according to the embodiment, a semiconductor substrate (SiC substrate) made of SiC is used as the substrate 1. When a SiC substrate is used, the channel forming region 3 exemplifies a structure composed of an epitaxial layer (SiC layer) made of SiC. The plane orientation of the SiC substrate will be described using the (0001) plane (Si plane), but the (11-20) plane (a plane), the (1-100) plane (m plane), and (000-1). A surface (C surface) may be used.

As shown in FIG. 1, in the insulated gate type semiconductor device according to the embodiment, a voltage is applied to the gate electrode 7 to form an inversion layer serving as a channel at the interface between the gate insulating film 5 and the channel forming region 3. At this time, by applying a voltage between the source electrode 8a and the drain electrode 8b, carriers (electrons) are injected into the channel from the source region 4a. The injected carrier travels through the channel and flows into the drain region 4b.

_{Normally, when the SiO 2} film used for the gate insulating film 5 is formed by a thermal oxidation method or the like, _{C atoms remain at the interface between the SiO 2} film and the SiC semiconductor layer, and a high-density interface state is formed. When electrons are captured at the interface state, the electron mobility decreases due to Coulomb scattering and the like. A method of reducing the interface state density has been proposed by terminating the interface between the SiO _{2 film and the SiC semiconductor layer with N atoms.} However, _{when a high-concentration nitrided region is formed at the interface between the SiO 2} film and the SiC semiconductor layer, the gate threshold voltage of the semiconductor device fluctuates in response to the gate negative voltage application stress.

In the insulated gate type semiconductor device according to the embodiment, the intermediate nitriding terminal layer formed at the interface between the gate insulating film 5 and the channel forming region 3 _{by nitriding treatment is heat-treated with carbon dioxide (CO 2} ) gas to form the nitriding terminal layer 6. Provide. As will be described later, the CO ₂ heat treatment _{breaks the Si—N bond in the SiO 2} film and at the interface of the SiC semiconductor layer to remove N atoms. When removing all of the gate insulating film 5, X-ray photoelectron spectroscopy of N and Si nitride termination layer 6 (XPS) signal intensity ratio I _N / I _Si greater than 0.01, so as to be less than 0.02 CO ₂ heat treatment. At this time, XPS signal intensity ratio I _N / I _Si when leaving the gate insulating film 5 near the interface 2nm or more 3nm or less than 0.02, less than 0.03. In this way, _{the Si—N bond between the nitriding terminal layer 6 and the gate insulating film 5 is broken by the CO 2} heat treatment, excess N atoms can be eliminated, and hole traps in the gate insulating film 5 can be removed. As a result, it becomes possible to suppress fluctuations in the gate threshold voltage of the semiconductor device.

Fluctuations in the gate threshold voltage of the semiconductor device can be evaluated, for example, by shifting the flat band voltage (Vfb) of the MOS capacitor. Therefore, a MOS capacitor corresponding to the insulated gate structure according to the embodiment was produced and the interface characteristics of the MOS capacitor were evaluated. A method of manufacturing a MOS capacitor corresponding to the insulated gate structure according to the embodiment will be described with reference to the process diagrams shown in FIGS. 2 to 5. The MOS capacitor manufacturing method described below is an example, and it may be feasible by various other manufacturing methods including this modification as long as it is within the scope of the claims. Of course.

First, an n-type SiC substrate (substrate) 2 to which an n-type impurity such as nitrogen (N) is added is prepared. The substrate 2 is a 4H-SiC substrate, and the plane orientation is (0001) plane (Si plane). First, the substrate 2 is RCA-cleaned by adding an alkali or acid to hydrogen peroxide and heating to clean it, and is treated with hydrogen fluoride (HF) and dried. As shown in FIG. 2, an oxide film 5a made _{of SiO 2} having a diameter of about 50 nm is formed on the upper surface of the washed substrate 2 by heating at a temperature of about 1200 ° C. for about 160 minutes _{in a 100% O 2 gas atmosphere.} As the oxide film 5a, a dry oxide film is exemplified, but a wet oxide film may be used, or a deposited oxide film by thermal CVD, plasma CVD, or the like may be used. For example, the oxide film 5a may be deposited at a pressure of about 0.2 Pa and a temperature of about 600 ° C. using _{silane (SiH 4} ) gas and oxygen (O ₂ ) gas in reduced pressure thermal CVD.

Next, in a gas atmosphere in which 10% of nitric oxide (NO) gas is added to nitrogen (N ₂ ) gas, the nitriding treatment is performed by heating at a temperature of about 1250 ° C. for about 60 minutes. By this nitriding treatment, as shown in FIG. 3, an intermediate nitriding layer 6a is formed at the interface between the oxide film 5a and the substrate 2. _{Nitrous oxide (N 2} O) gas may be used instead of NO for the nitriding treatment.

Next, in a CO ₂ gas atmosphere, heat treatment is performed at three different temperatures for about 30 minutes each. The three temperatures are 1400 ° C. for Example 1, 1300 ° C. for Example 2, and 1200 ° C. for Example 3. By these three types of heat treatment, as shown in FIG. 4, the concentration of N atoms in the oxide film 5a near the interface between the oxide film 5a and the substrate 2 is reduced, and some N atoms are removed from the intermediate nitride layer 6a. The removed nitriding termination layer 6 is produced in three different modes. In the CO ₂ heat treatment, 100% CO ₂ gas is used, but _{a mixed gas of CO 2} gas and _{an inert gas such as N 2} or argon (Ar) may be used.

As shown in FIG. 5, a circular pattern of a metal film having a diameter of about 200 μm is formed on the upper surface of the oxide film 5a by using a lift-off or a usual photolithography method. As the metal film that is the premise of the circular pattern, a metal film such as Al having a thickness of about 100 μm may be deposited on the upper surface of the oxide film 5a by a sputtering method, a vacuum vapor deposition method, or the like. Subsequently, a metal film such as Al having a thickness of about 100 μm is deposited on the entire back surface of the substrate 2 by a sputtering method, a vacuum vapor deposition method, or the like. In this way, the front electrode 10 and the back electrode 11 are formed.

XPS measurement and CV measurement are performed on the three types of Examples 1 to 3 produced to evaluate the MOS interface characteristics. Further, in order to compare with Examples 1 to 3, as shown in FIG. 6, Comparative Example 1 in which the front surface electrode 10 and the back surface electrode 11 are formed without performing the CO2 heat treatment after the intermediate nitride layer 6a of FIG. 3 is formed is also prepared. And evaluate.

For XPS measurement, aluminum (Al) Kα rays are used as an X-ray source, and surface analysis is performed at a detection angle of 90 degrees. The oxide film 5a is gradually step-etched from the surface with dilute phosphoric acid, for example, an aqueous solution having a fluoroacid concentration of 1%, and the measurement is repeated for each step etching. The spectral signal (Si2p signal) caused by the Si2p orbit is detected by a narrow scan in the binding energy range of 98 eV to 108 eV. At the same time, the spectral signal (N1s signal) caused by the N1s orbit is detected by a narrow scan in the binding energy range of 394eV to 402eV. As shown in FIG. 7, regarding the Si2p signal, the signal of the SiC component derived from the substrate 2 and the signal of the SiO ₂ component derived from the oxide film 5a are peak-separated. The peak position of the signal of the SiC component is 101 eV to 102 eV, and the peak position of the signal of the _{SiO 2 component is 103 eV to 104 eV.} From the peak-separated Si2p signal, the energy integral value S (SiC) of the spectral signal of the SiC component and the energy integral value S (SiO _{2 ) of the spectral signal of the SiO 2} component are calculated. As shown in FIG. 8, the energy integral value S (N) of the N1s signal is calculated.

An energy integration value S of the SiC component (SiC) and SiO ₂ component of the energy integration value S (SiO _2), from the theoretical density of SiO _2, to calculate the residual film thickness of the oxide film 5a for each step etching. Intensity ratio I _N / I _Si in the vicinity of the interface between the N and Si, the ratio S between the energy integration value S of the N1s signal (N) and the SiC component energy integration value S (SiC) (N) / S (SiC) calculate. FIG. 9 shows the XPS measurement results of the nitriding terminal layer 6 and the intermediate nitriding layer 6a in the vicinity of the interface of the oxide film 5a for Example 2 and Comparative Example 1, respectively. As shown in FIG. 9, the intensity ratio I _N / I _Si when 2.5nm from thickness interfacial oxide film 5a in Example 2 and Comparative Example 1, saturated with respectively about 0.026 and about 0.040 Tend to do. In Example 2, the intensity ratio _IN / I _Si sharply decreases when the oxide film thickness becomes thinner than about 0.2 nm, and becomes about 0.017 at the interface of the substrate 2 which is the SiC surface. On the other hand, in Comparative Example 1, the intensity ratio _IN / I _Si sharply decreases from the position where the thickness of the oxide film is about 0.4 nm, and becomes about 0.025 at the interface which becomes the SiC surface of the substrate 2.

FIG. 10 shows the XPS measurement results for Examples 1 to 3 and Comparative Example 1, the interface state density D _it and the flat band voltage (Vfb) shift by CV measurement. The SiC surface _I N _{/ I Si} of XPS measurement results, the intensity ratio when the oxide thickness 0nm in FIG. 9, the saturation _I The N _{/ I Si,} oxide thickness 2nm or more 3nm following in FIG The intensity ratio of time is described. The interface state density D _it is the level density at the energy position of 0.2 eV from the conduction band edge Ec. The Vfb shift is measured after bias stress under the conditions of + 6 MV / cm for positive bias and -6 MV / cm for negative bias, respectively. In particular, the negative bias condition is a severe condition in which a gate leak current starts to occur, and serves as a guideline for the amount of hole traps in the oxide film 5a. The smaller the Vfb shift amount, the smaller the hole trap.

_{As shown in the table of FIG. 10, the intensity ratio IN} / I _Si of the SiC surface of the substrate 2 from which the oxide film 5a was completely removed was high in Comparative Example 1 in which the CO _{2 heat treatment was not performed, and the CO 2} heating temperature was high. It decreases as it increases. Further, the saturation intensity ratio _IN / I _Si in the oxide film 5a is also high in Comparative Example 1 in which the _{CO 2} heat treatment is not performed, and decreases as the _{CO 2 heating temperature increases.} As described above, _{it can be seen that the CO 2} heat treatment breaks the Si—N bond in the SiC surface of the substrate 2 at the interface and in the oxide film 5a, and N is eliminated.

Further, as shown in the table of FIG. 10, in _{Example 1 in which the CO 2} heating temperature was 1400 ° C., the N decrease on the SiC surface was remarkable, and the interface state density D _it increased to 3 × 10 ¹² cm ⁻² / eV. doing. In _{Examples 2 and 3 where the CO 2} heating temperatures are 1300 ° C and 1200 ° C, the interface state density D _it is as low as 9 × 10 ¹¹ cm ^-2 / eV and 8 × 10 ¹¹ cm ^-2 / eV, respectively. .. In Examples 1 to 3, the Vfb shift amount is about 0.1 V under the positive bias condition and about -2 V to -2.6 V under the negative bias condition, both of which are small. _{On the other hand, in Comparative Example 1 in which CO 2} heating is not performed only by the conventional nitriding treatment with NO gas _{, the interface state density D it} is as low as 7 × 10 ¹¹ cm ⁻² / eV due to the effect of N passivation. However, in Comparative Example 1, the Vfb shift after the bias stress is remarkable, and is as large as about 1.0 V under the positive bias condition and about -4.9 V under the negative bias condition. As described above, in Examples 2 and 3, the Vfb shift under the negative bias condition is improved while maintaining _{the interface state density D it} less than 1 × 10 ¹² cm ^{−2 / eV.}

In the insulated gate structure according to the embodiment, after the oxide film 5a is formed, the NO nitriding treatment is followed by the CO ₂ treatment. In the CO ₂ treatment, the Si—N bond or the Si—ON bond in the _{SiO 2} film of the nitriding terminal layer 6 near the interface between the oxide film 5a introduced by the nitriding treatment and the substrate 2 is broken. The CO ₂ gas is decomposed into _{CO as a reducing gas and O 2} as an oxidizing gas at about 800 ° C. to 1400 ° C. O ₂ gas also has the effect of breaking the Si—N bond and converting it into a Si—O bond, but the SiC surface of the substrate 2 is also oxidized, destroying the N passivation of the interface formed by the nitriding treatment. Since CO gas is generated in _{CO 2} gas, the N passivation at the interface is less likely to be destroyed than _{in O 2} gas, and the Si—N bond in the _{SiO 2 film can be broken. Therefore, it} is possible to suppress an increase in the interface state density D it, eliminate N in the nitriding terminal layer 6 in the vicinity of the interface of the oxide film 5a, and reduce hole traps due to N.

In the above description, as the substrate 2, a SiC substrate having a plane orientation of (0001) plane (Si plane) is used. The Si plane has a higher oxidation rate than the (11-20) plane (a plane), the (1-100) plane (m plane), and the (000-1) plane (C plane). Therefore, on the Si surface, the CO ₂ treatment temperature is preferably in the range of 1000 ° C. to 1400 ° C., preferably in the range of 1100 ° C. to 1300 ° C. On the a-plane, m-plane, and C-plane, the CO ₂ treatment temperature is preferably in the range of 800 ° C. to 1200 ° C., preferably in the range of 1000 ° C. to 1200 ° C.

(Manufacturing method of insulated gate type semiconductor device)
Next, the manufacturing method of the insulated gate type semiconductor device according to the embodiment will be described as an example in the case of a horizontal MOSFET by using the process diagrams shown in FIGS. 11 to 16. It should be noted that the MOSFET manufacturing method described below is an example, and of course, it can be realized by various other manufacturing methods including this modification as long as it is within the scope of the claims. Is.

First, an n-type SiC substrate (substrate) 1 to which an n-type impurity such as nitrogen (N) is added is prepared. The substrate 1 is a 4H-SiC substrate, and the plane orientation is (0001) plane (Si plane). A p-type channel forming region (base region) 3 is epitaxially grown on the upper surface of the substrate 1. N-type impurities such as N are selectively injected from the upper surface side of the channel formation region 3 by a photolithography technique, an ion implantation technique, or the like. The injected n-type impurity ions are activated by performing a heat treatment. As a result, as shown in FIG. 11, an n ⁺ type source region (first main electrode region) 4a and a drain region (second main electrode region) 4b are selectively embedded in the upper part of the channel formation region 3.

As shown in FIG. 12, a silicon oxide film 5b made _{of SiO 2} having a diameter of about 50 nm is formed on the upper surface of the channel forming region 3 by heating at a temperature of about 1200 ° C. for about 160 minutes _{in a 100% O 2 gas atmosphere.} Although a dry oxide film is exemplified as the silicon oxide film 5b, a wet oxide film may be used, or a deposited oxide film by thermal CVD, plasma CVD, or the like may be used. For example, a silicon oxide film 5b may be deposited at a pressure of about 0.2 Pa and a temperature of about 600 ° C. using _{silane (SiH 4} ) gas and oxygen (O ₂ ) gas in reduced pressure thermal CVD.

Next, _{in a gas atmosphere in which 10% of nitric oxide (NO) gas is added to N 2} gas, nitriding is performed by heating at a temperature of about 1250 ° C. for about 60 minutes. By this nitriding treatment, as shown in FIG. 13, an intermediate nitriding layer 6a is formed at the interface between the silicon oxide film 5b and the channel forming region 3, the source region 4a and the drain region 4b. In the nitriding treatment, N ₂ O gas may be used instead of NO.

After the nitriding treatment, _{heat treatment is performed in a CO 2} gas atmosphere at two different temperatures for about 30 minutes each. As the two temperatures, 1300 ° C. is adopted as Example 4 and 1200 ° C. is adopted as Example 5. By heat treatment at these two temperatures, as shown in FIG. 14, the concentration of N atoms in the silicon oxide film 5b near the interface between the silicon oxide film 5b and the channel forming region 3, the source region 4a and the drain region 4b. However, it is reduced in two ways. Further, in two ways, the nitriding terminal layer 6 in which some N atoms are removed from the intermediate nitriding layer 6a is generated. In the CO ₂ heat treatment, 100% CO ₂ gas is used, but _{a mixed gas of CO 2} gas and _{an inert gas such as N 2} or argon (Ar) may be used.

A source contact hole and a drain contact hole are opened in the silicon oxide film 5b by photolithography technology, dry etching or the like. As a result, as shown in FIG. 15, the pattern of the gate insulating film 5 selectively remains on the upper surface of the channel forming region 3 so as to straddle the source region 4a and the drain region 4b.

A metal film such as Al having a thickness of about 100 μm is deposited on the upper surfaces of the gate insulating film 5, the source contact hole and the drain contact hole by a sputtering method, a vacuum vapor deposition method or the like. The metal film is separated by photolithography technology, dry etching, or the like to form a pattern of the gate electrode 7, the source electrode 8a, and the drain electrode 8b. As a result, the insulated gate type electrode structure (5, 7) is formed on the upper surface of the channel forming region 3 via the nitriding end layer 6 so as to straddle a part of the end portions of the source region 4a and the drain region 4b. .. In this way, the insulated gate type semiconductor device according to the embodiment shown in FIG. 16 is completed.

Transistor characteristics are measured for Examples 4 and 5 of the two types of horizontal MOSFETs produced in this manner, and field effect mobility, threshold voltage Vth, and threshold voltage (Vth) shift are evaluated by a bias application test. The bias application test is performed at 200 ° C. for 100 hours under a positive bias condition of + 20 V and at 200 ° C. for 100 hours under a negative bias condition of −10 V. Further, as shown in FIG. 17, for comparison with Examples 4 and 5, the gate insulating film 5, the gate electrode 7, the source electrode 8a, and the gate electrode 7 and the source electrode 8a are not subjected to CO2 heat treatment after the intermediate nitride layer 6a of FIG. 13 is formed. Comparative Example 2 in which the drain electrode 8b is formed is also evaluated in the same manner.

FIG. 18 shows the evaluation result of the transistor. As shown in the table of FIG. 18, the field effect mobilities of Examples 4 and 5 that were heat-treated with _{CO 2} ^{at 1300 ° C. and 1200 ° C. are 25 cm 2} / Vs and 22 cm ² / Vs, respectively. The field effect mobility of Comparative Example 2 using only the conventional nitriding treatment is 21 cm ² / Vs. As described above, in Examples 4 and 5, the mobility of the electric field effect is at the same level as that of Comparative Example 2 or slightly improved. Further, the threshold voltage Vth is also at the same level as in Comparative Example 2. The Vth shift under the positive bias condition is not different between Examples 4, 5 and Comparative Example 2, but under the negative bias condition, Comparative Example 2 is −0.15 V and Example 4 is −0. The Vth shift is suppressed to 06V and −0.08V in Example 5. As described above, in the insulated gate type semiconductor device according to the embodiment, the electric field effect mobility can be improved, the Vth shift can be suppressed, and the deterioration of the reliability of the semiconductor device can be suppressed.

(Other embodiments)
As described above, the insulated gate semiconductor device according to the embodiment of the present invention has been described, but the statements and drawings that form a part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure.

As described above, in the semiconductor device related to the insulated gate type semiconductor device according to the embodiment, the horizontal MOSFET using 4H-SiC has been exemplified, but it is applied to the semiconductor device using 6H-SiC and 3C-SiC. Is also possible. Further, it can be applied to a planar gate vertical MOSFET and a trench gate vertical MOSFET.

As described above, it goes without saying that the present invention includes various embodiments not described here, such as a configuration in which the above-described embodiment and each configuration described in each modification are arbitrarily applied. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

1, 2 ... Substrate (SiC substrate)
3 ... Channel formation region (base region)
4a ... Source region (first main electrode region)
4b ... Drain region (second main electrode region)
5 ... Gate insulating film 5a, 5b ... Oxidized film 6 ... End nitriding layer 6a ... Intermediate nitriding layer 7 ... Gate electrode (control electrode)
8a ... Source electrode 8b ... Drain electrode 10 ... Front electrode 11 ... Back electrode

Claims (6)

A process of forming a gate insulating film made of a silicon oxide film on the upper surface of a channel forming region made of silicon carbide, and
By heat-treating the gate insulating film with a gas containing a nitrogen atom, the interface between the gate insulating film and silicon carbide is nitrided to form an intermediate nitride layer at the interface between the channel forming region and the gate insulating film. And the process to do
A step of removing a part of nitrogen atoms in the gate insulating film by heat-treating the gate insulating film with a gas containing carbon dioxide to form a nitriding terminal layer at the interface.
A method for manufacturing an insulated gate type semiconductor device, which comprises a step of forming a gate electrode for controlling the surface potential of the channel forming region on the gate insulating film. When the interface between the gate insulating film and the silicon carbide was measured by X-ray photoelectron spectroscopy, the spectrum due to the 2p orbital of the silicon from the intensity I _N of the spectrum due to the 1s orbital of nitrogen in said channel formation region intensity ratio I _N / I _Si and I _Si is 0.02 or more when left the gate insulating film between 2nm or more 3nm or less from the interface is less than 0.03, removing the gate insulating film The method for manufacturing an insulated gate type semiconductor device according to claim 1, wherein the nitrided terminal layer is larger than 0.01 and less than 0.02. The insulated gate type semiconductor device according to claim 1 or 2, wherein the nitriding terminal layer is formed in a gas containing carbon dioxide at a heat treatment temperature in the range of 800 ° C. or higher and 1400 ° C. or lower. Production method. Any of claims 1 to 3, wherein the surface orientation of the upper surface of the channel forming region is the (0001) plane, and the nitride termination layer is formed at a heat treatment temperature of 1100 ° C. or higher and 1300 ° C. or lower. The method for manufacturing an insulated gate type semiconductor device according to item 1. The plane orientation of the upper surface of the channel forming region is any of the (000-1) plane, the (11-20) plane, and the (1-100) plane, and the nitride termination layer is 1000 ° C. or higher and 1200 ° C. or lower. The method for manufacturing an insulated gate type semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is formed at the heat treatment temperature of the above. A gate insulating film made of a silicon oxide film provided on the upper surface of a channel forming region made of silicon carbide, and a gate insulating film made of silicon oxide.
A nitriding termination layer made of silicon nitride provided at the interface between the channel forming region and the gate insulating film, and
A gate electrode provided on the gate insulating film and controlling the surface potential of the channel forming region,
With
When the interface between the gate insulating film and the silicon carbide was measured by X-ray photoelectron spectroscopy, the spectrum due to the 2p orbital of the silicon from the intensity I _N of the spectrum due to the 1s orbital of nitrogen in said channel formation region intensity ratio I _N / I _Si and I _Si is 0.02 or more when left the gate insulating film between 2nm or more 3nm or less from the interface is less than 0.03, removing the gate insulating film An insulated gate type semiconductor device, wherein the nitrided terminal layer is larger than 0.01 and less than 0.02.

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