JP5017855B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention, a silicon carbide as a main material, relates to the production how a semiconductor device having a trench gate type MOS structure to a thermal oxide film and the gate insulating film.

  Silicon carbide has characteristics such as a large band gap, a high saturation drift speed, a high thermal conductivity, and a dielectric breakdown electric field strength that is about one digit higher than silicon. Therefore, silicon carbide is expected as a power device material having characteristics exceeding the limit of silicon.

  In a trench gate type MOSFET (UMOSFET) whose main material is silicon carbide, when a certain trench gate is formed, it is impossible or extremely difficult to form all the side walls of the trench with crystallographically equivalent surfaces. For example, when one trench is formed, the side walls facing each other are composed of C (carbon) and Si (silicon) surfaces, and the atomic arrangement is not equivalent, or the plane index is different and the atomic arrangement is not equivalent There are many.

  In addition, in compound semiconductors composed of two types of elements (for example, Si and C), there is a difference in atomic arrangement between the front surface and the back surface. Therefore, even if oxidation is performed under the same conditions, the oxidation rate is greatly increased. There is a phenomenon that changes. For example, in the (0001) plane, which is usually called the Si plane, and the (000-1) plane, which is usually called the C plane, the crystal plane has a front-back relationship. The difference between this Si plane and the C plane is whether or not a minus sign is attached to the index representing the plane orientation. However, physically, there is a difference between whether the element exposed on the outermost surface is Si or C, and as a result, it is known that the oxidation rate is nearly one digit faster on the C plane.

  Further, in the silicon carbide MOSFET, the (03-38) plane of 4H—SiC, which has been reported to have a very high electron mobility in the MOS channel, is also in a front-back relationship (0-33). -8) The atomic arrangement is different on the surface, and as a result, the oxidation rate also varies.

  As described above, in a compound semiconductor, there are many pairs of plane orientations having physical properties that are significantly different in physical properties depending on whether or not a minus sign is added to the plane index. As another example, since gallium arsenide (GaAs) is a compound semiconductor, for example, the (111) plane and the (-1-1-1) plane have different physical properties.

  In compound semiconductors, there are pairs of plane orientations that have a front-back relationship and the same atomic arrangement. For example, the (11-20) plane and the (-1-120) plane of 4H—SiC have a front / back relationship, but have the same atomic arrangement and no difference in physical properties. Further, the hexagonal Miller index is (hkil) (where h + k + i = 0) and changing the order of hki is equivalent. The sign of l differs because it varies between the Si surface side and the C surface side.

  As another example, in GaAs, the (110) plane and the (-1-10) plane are front-back, but the atomic arrangement is equivalent and the physical properties are not different. However, there are very few pairs of plane orientations in the compound semiconductor that have the same front-back relationship, but have the same atomic arrangement and no difference in physical properties.

  On the other hand, in a material composed of a single element such as silicon or germanium, the atomic arrangement differs depending on the front and back of the crystal plane, and as a result, there is no problem that the physical properties are different. Of course, the face index is not a positive or negative relationship, and physical properties differ between faces having completely different face indices.

  Incidentally, when the gate insulating film is formed by thermal oxidation in the trench formed in the surface region of the silicon carbide substrate, the oxidation rate depends on the plane orientation as shown in FIG. FIG. 20 shows the speed of the oxidation rate when the angle is changed from the C-plane. The oxidation rate is the fastest on the C-plane and tends to become slower as the angle is changed.

  The speed is lowest on the Si surface. As a result, in the trench gate type MOSFET whose planar pattern is a cell shape, on the plurality of sidewalls surrounding one trench, in the trench gate type MOSFET whose planar pattern is a stripe shape, the oxide film is present on the two opposite trench sidewalls. There may be a difference in the film thickness.

  A silicon carbide surface is etched to form a recess, and then a particle beam such as an ion beam is irradiated from above the surface to form a damaged layer at least on the bottom surface of the recess, and an insulating film is formed on at least the side surface and bottom surface of the recess. And forming a gate electrode on the insulating film is disclosed (for example, see Patent Document 1 below).

JP 2000-31003 A

  However, in the conventional technique described above and the conventional technique described in Patent Document 1, the thickness of the gate oxide film differs for each side wall having a different plane orientation. At this time, the breakdown voltage of the gate oxide film is most likely to cause dielectric breakdown on the side wall having the thinnest oxide film. That is, the breakdown voltage of the semiconductor device is determined by the side wall.

  When the MOSFET is on, the threshold voltage (Vth) is low on the inner wall where the gate oxide film in the trench is thin, and a conduction channel is immediately formed. On the other hand, even if the inner wall having a thick gate oxide film does not reach Vth or reaches Vth, sufficient channel current cannot be secured. Thus, when there is a difference in the thickness of the gate oxide film in one trench, only the side wall where the gate oxide film is substantially thin carries the channel current. For this reason, the entire area of the trench sidewall cannot be used effectively as a conduction channel, and there is a problem that the on-current is lowered and the operation speed of the semiconductor device is lowered.

  In order to effectively use the entire area of the inner wall of the trench as a conduction channel, the difference in thickness of the gate oxide film may be reduced. However, the gate oxide film on the inner wall having a low oxidation rate is formed thin, and the breakdown voltage of the gate oxide film is reduced. For this reason, there is a problem that the gate oxide film is easily broken down.

The present invention, in order to solve the problems in the conventional techniques described above, and an object thereof is to provide a manufacturing how high-speed operation, and simultaneously the semiconductor device capable of realizing a high breakdown voltage of the semiconductor device.

To solve the above problems and achieve an object, a method of manufacturing a semiconductor device according to this invention, first of forming a semiconductor region of higher resistance than the semiconductor substrate on the surface of a semiconductor substrate comprised of silicon carbide crystals Forming a trench reaching the semiconductor region formed by the first forming step, and a plurality of side walls having different oxidation rates constituting the inner side wall of the trench. An implantation step of implanting an amount of ions according to the oxidation rate of the substrate , and oxidizing the inner wall of the trench into which the ions have been implanted by the implantation step, and forming an insulating film having a substantially uniform thickness on the inner sidewall of the trench a third forming step of forming, only contains the implantation in the step, the other side wall excluding the highest oxidation speed is faster sidewalls of the trench as the rate of oxidation of each of the side walls of the trench are the same speed Separately implanting ions, characterized by implanting ions at the same time on the bottom of the trench when implanting ions into a side wall facing each other of the other side wall of the trench.

A method of manufacturing a semiconductor device according to this invention includes a first forming step of forming a semiconductor region of higher resistance than the semiconductor substrate on the surface of a semiconductor substrate made of silicon carbide, by the first forming step A second forming step for forming a trench reaching the formed semiconductor region; and an inner side wall of the trench formed by the second forming step is oxidized, and an oxidation rate is provided on each side wall of the trench at a side wall having a low oxidation rate. A third forming step of forming an insulating film so as to be thinner than a fast side wall, and implanting the same amount of ions into all the side walls of the trench through the insulating film formed by the third forming step it makes comprise, an injection step of injecting a large amount of ions than the side wall of the thick insulating film on the sidewall of the trench a thin insulating film is formed is formed the trenches And features.

A method of manufacturing a semiconductor device according to this invention is the invention described above, the insulating film and the removing step of removing from the inner wall of the trench, an inner wall of the trench in which the ions are implanted by the implantation step And a fourth formation step of forming a new insulating film on the inner side wall of the trench .

A method of manufacturing a semiconductor device according to this invention is the invention described above, the silicon carbide, characterized in that it is a four-layer periodic hexagonal.

A method of manufacturing a semiconductor device according to this invention is the invention described above, the major surface of the semiconductor substrate (11-20) plane or the (11-20) is a surface equivalent to the surface, the trench At least one of the constituting crystal faces is a (03-38) plane or a plane equivalent to the (03-38) plane.

According to the above-described invention, the thickness of the oxide film formed on the inner side wall of the trench constituted by different crystal planes can be formed substantially uniformly.

According to the above-described invention, ions can be implanted so that the oxidation rate of the inner wall of the trench constituted by different crystal planes is constant.

According to the manufacturing how the semiconductor device according to the present invention, substantially uniformly formed the thickness of the gate oxide film formed on the trench side wall, it is possible to achieve high breakdown voltage of the semiconductor device, and the simultaneous realization of high-speed operation There is an effect.

With reference to the accompanying drawings, illustrating a preferred embodiment of the manufacturing how the semiconductor device according to the present invention in detail.

(Embodiment 1)
First, the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention is demonstrated with reference to FIGS. 1, FIG. 2, and FIG. 7 to FIG. 9 are cross-sectional views showing the configuration in the middle of manufacturing the semiconductor device according to the first embodiment of the present invention. In the following description, an n-channel MOSFET is described as an example of a semiconductor device. However, an n-channel MOSFET and a p-channel MOSFET may be interchanged. Further, hereinafter, unless otherwise specified, a silicon carbide four-layer periodic hexagonal crystal (4H) is used.

First, as shown in FIG. 1, a low-resistance n ⁺ silicon carbide substrate 1 whose surface orientation is a (11-20) plane as a main surface is prepared. The surface region of the n ⁺ silicon carbide substrate 1, the n ⁺ high-resistance n than silicon carbide substrate 1 ^- the drift region (semiconductor region) 2 n ^- is formed by epitaxial deposition of silicon carbide thin film. At this time, the impurity concentration of n ⁻ drift region 2 is, for example, about 1 × 10 ¹⁶ cm ⁻³ and the thickness is, for example, about 10 μm.

Next, a silicon carbide thin film to be the n current diffusion region 3 is formed by epitaxial film formation with an impurity concentration of 2 × 10 ¹⁷ cm ⁻³ and a thickness of 0.4 μm, for example. Subsequently, a p-silicon carbide thin film to be the p-well region 4 is formed with an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ and a thickness of 2 μm, for example. Then, the n ⁺ silicon carbide thin film to be the n ⁺ source region 5, for example, 1 × 10 ¹⁸ cm ^-3, is formed to a thickness 0.5 [mu] m.

Then, the surface region of this substrate is pyrogenic oxidized at, for example, 1100 ° C. for 1 hour to form a protective oxide film 6 of about 30 nm to 50 nm. Next, an aluminum (Al) mask 7 is formed with a thickness of, for example, 0.5 μm on the surface region of the protective oxide film 6 by sputtering, and then the Al mask 7 is patterned by a photo process. Next, as shown in FIG. 2, ICP plasma etching is performed using SF ₆ (sulfur hexafluoride) and O ₂ gas using the Al mask 7 to form the trench 8. The trench 8 is formed so as to reach the n ⁻ drift region 2. When the trench 8 is formed, the Al mask 7 and the protective oxide film 6 are removed.

  Here, the plane orientation of the inner wall constituting the trench 8 will be described. FIG. 3 is an explanatory view showing the surface orientation of the side walls constituting the trench. In FIG. 3, the inner wall of the trench 8 is constituted by a crystal plane having plane orientations of (0001), (−1100), (000-1), and (1-100). Of these four crystal planes, the (1-100) plane and the (-1100) plane are equivalent in atomic arrangement, and have the same oxidation rate (oxidation rate). According to FIG. 20, the speed of the oxidation rate of the four inner walls constituting the trench 8 is as follows.

  (000-1) plane> (1-100) plane = (− 1100) plane> (0001) plane

  For this reason, in order to make the thickness of the formed oxide film uniform, the oxidation rate of the inner wall of each trench is made constant. In order to make the oxidation rate constant, the oxidation rate of the other surface is matched with the oxidation rate of the (000-1) surface having the fastest oxidation rate. Therefore, ion implantation is performed by irradiating the (1-100) plane, the (-1100) plane, and the (0001) plane with a silicon (Si) ion beam. Ion implantation is performed separately for each surface. Hereinafter, each ion implantation is referred to as a first ion implantation, a second ion implantation, and a third ion implantation. Further, the amount of Si ions implanted by each ion implantation is an amount necessary for the oxidation rate of the sidewall of the trench 8 to be the same as that of the fastest crystal plane. Next, ion implantation will be described.

FIG. 4 is an explanatory diagram showing a planar irradiation of the Si ion beam and a plan view of the trench during the first ion implantation. In FIG. 4, the Si ion beam 9 is selectively applied only to the side wall having the (0001) plane of the trench 8. At this time, the n ⁺ silicon carbide substrate 1 is rotated and stopped on the horizontal plane. This is because the Si ion beam 9 is irradiated only to the (0001) plane of the trench 8.

Next, Si ions implanted by the first implantation will be described. FIG. 5 is a cross-sectional view of the main part showing Si ions to be implanted. In FIG. 5, the Si ion beam 9 is irradiated at an angle θ _{1 with} respect to a normal to the surface with respect to the n ⁺ source region 5. The angle θ ₁ is an angle at which only the (0001) plane is selectively irradiated without the Si ion beam 9 being irradiated on the bottom surface of the trench 8. This angle θ ₁ is determined by an aspect ratio determined from the width of the opening of the trench 8 and the depth of the trench 8. Therefore, the value varies depending on the width of the opening of the trench 8 and the depth of the trench 8. In the first embodiment, Si ions are implanted at a dose of 5 × 10 ¹⁵ cm ⁻² at 30 keV, for example.

Next, the second ion implantation will be described. FIG. 6 is an explanatory view showing the planar irradiation of the Si ion beam and the plan view of the trench during the second ion implantation. In FIG. 9, the Si ion beam 9 is selectively applied only to the side wall having the (−1100) plane of the trench 8. At this time, the n ⁺ silicon carbide substrate 1 is rotated and stopped on the horizontal plane. This is because the Si ion beam 9 is irradiated only to the (−1100) plane of the trench 8.

Next, Si ions implanted by the second implantation will be described. FIG. 7 is a cross-sectional view of the main part showing Si ions implanted by the second implantation. In FIG. 7, the Si ion beam 9 is irradiated at an angle θ _{2 with} respect to a normal to the surface of the n ⁺ source region 5. This angle θ ₂ is an angle at which the Si ion beam 9 is selectively irradiated from the deepest part of the (1-100) plane and the bottom surface of the trench 8 to the plane from the (1-100) plane. This angle θ ₂ is determined by an aspect ratio determined from the width of the opening of the trench 8 and the depth of the trench 8 as in the angle θ ₁ . Therefore, the value varies depending on the width of the opening of the trench 8 and the depth of the trench 8. In the first embodiment, Si ions are implanted at a dose of 5 × 10 ¹⁴ cm ⁻² at 25 keV, for example.

Next, Si ions implanted by the third implantation will be described. FIG. 8 is a fragmentary cross-sectional view showing Si ions implanted by the third implantation. In FIG. 8, the third ion implantation is performed on the (−1100) plane in the same manner as the second ion implantation. At this time, the Si ion beam 9 is implanted at an angle of θ _{2 with} respect to a normal to the surface of the n ⁺ source region 5.

The (−1100) plane has the same atomic arrangement as the plane on which the second ion implantation is performed, that is, the (1-100) plane. Therefore, Si ions were implanted at 25 keV with a dose amount of 5 × 10 ¹⁴ cm ^{−2 which} is the same amount as the second ion implantation. By the second ion implantation and the third ion implantation described above, ions are implanted into the side wall and the bottom surface of the trench 8. The side wall into which Si ions are implanted has a higher rate of oxidation than before the Si ions are implanted. The oxide films are formed on the four side surfaces shown in FIG. 3 at substantially the same speed, and an oxide film having a substantially uniform thickness can be obtained.

Returning to the description of the manufacturing process, as shown in FIG. 9, gate oxidation is performed to form a gate oxide film 10 on the side wall, bottom surface, and n ⁺ source region 5 of the trench 8. At this time, the gate oxide film 10 is formed substantially uniformly with a thickness of about 50 to 100 nm from the sidewall of the trench 8. When the bottom of the trench 8 has a curvature and electric field concentration is likely to occur, the gate breakdown voltage can be maintained by forming the gate oxide film 10 slightly thicker.

The subsequent processes are the same as the generally known UMOSFET manufacturing process, and thus the description thereof is omitted. In the manufacturing process described above, the n current diffusion region 3, the p well region 4, and the n ⁺ source region 5 are formed by epitaxial film formation. Any or all of these films are formed by, for example, ion implantation and heat treatment (active It may be formed by annealing.

Further, the order of forming the p-well region 4, the n ⁺ source region 5, and the trench 8 can be changed. However, it is preferable to form at least the p-well region 4 before the trench 8.

Next, the UMOSFET manufactured by the above process will be described. FIG. 10 is an explanatory diagram showing the UMOSFET manufactured by the method for manufacturing the semiconductor device of the first embodiment. In FIG. 10, n ⁻ drift region 2 is formed on one main surface of n ⁺ silicon carbide substrate 1. An n current diffusion region 3 is provided on the n ⁻ drift region 2. A p-well region 4 is provided on the n-current diffusion region 3.

An n ⁺ source region 5 is provided on the p well region 4. A plurality of trenches 8 are selectively formed from the surface layer of the n ⁺ source region 5. The bottom of the trench 8 reaches the n ⁻ drift region 2. A gate electrode 11 is formed inside the trench 8 with an insulating gate oxide film 10 interposed therebetween. A second p ⁺ region 12 is formed between the trenches 8 from the direction of the n ⁺ source region 5. An interlayer insulating film 13 is provided so as to cover a part of n ⁺ source region 5 and trench 8.

A source metal electrode 14 is provided on interlayer insulating film 13 and second p ⁺ region 12, and is on the main surface opposite to the side on which source metal electrode 14 of n ⁺ silicon carbide substrate 1 is provided. Is provided with a drain metal electrode 15. A gate lead-out wiring 16 is provided on the gate electrode 11. In the configuration shown in FIG. 10, since the trench 8 has a cell-like pattern, the gate lead-out wiring 16 is required for each cell. However, in the case of the stripe-like pattern, the stripe It is only necessary to provide it at the end. This gate lead wiring 16 must be insulated from the source metal electrode 14.

  Next, the thickness of the oxide film described in the first embodiment will be described. FIG. 11 is a graph showing the thickness and acceleration energy of the oxide film. In FIG. 11, the vertical axis indicates the thickness (nm) of the oxide film, and the horizontal axis indicates the acceleration energy (eV). Reference numeral 21 indicates a change in the thickness of the oxide film formed when ions are implanted. Reference numeral 22 indicates the thickness of the oxide film formed when ions are not implanted. As indicated by reference numeral 21, when ions are implanted, the thickness of the oxide film formed increases as the acceleration energy increases.

  Next, the oxidation rate when ions are implanted into each crystal plane will be described. FIG. 12 is a graph showing the oxidation rate when ions are implanted into each crystal plane. In FIG. 12, the vertical axis indicates the oxidation rate (μm / h), and the horizontal axis indicates the angle (°) from the C plane. Reference numeral 31 indicates a change in oxidation rate when ions are not implanted, and reference numeral 32 indicates an oxidation rate when ions are implanted.

  When ions are not implanted, as shown by reference numeral 31, the oxidation rate decreases as the angle from the C plane increases. In addition, when ions are implanted, the oxidation rate does not change greatly even if the angle from the C plane increases. Thus, by implanting ions into the crystal plane, the oxidation rate of crystal planes with different atomic arrangements can be made substantially constant. Further, since the oxidation rates of the crystal planes are almost equal, the thickness of the gate oxide film can be made substantially uniform.

  As described above, according to the first embodiment, the oxidation rate of the side walls in the trench can be made substantially constant. Further, the gate oxide film formed on the side wall in the trench can be formed to have a substantially constant thickness.

(Embodiment 2)
Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described. First, up to the Al mask 7 shown in FIG. 1 is formed by the same process as in the first embodiment. Subsequently, the Al mask 7 is patterned by a photo process.

Next, trenches are formed by performing ICP plasma etching using SF ₆ (sulfur hexafluoride) and O ₂ gas using the Al mask 7. The trench is formed so as to reach the n ⁻ drift region 2. When the trench is formed, the Al mask 7 and the protective oxide film 6 are removed.

  Here, the plane orientation of the side surface constituting the trench will be described. FIG. 13 is an explanatory diagram showing the surface orientation of the side surfaces constituting the trench. In FIG. 13, the sidewall of the trench 41 is constituted by side surfaces having plane orientations of (0-338), (0-33-8), (03-3-8), and (03-38).

  Of these four crystal planes, the (03-38) plane and the (0-338) plane are equivalent in atomic arrangement. Further, the (0-33-8) plane and the (03-3-8) plane are equivalent in atomic arrangement. The oxidation rates of the surfaces equivalent to these atomic arrangements are equal. And according to FIG. 20, the speed of the oxidation rate of four surfaces which comprise the trench 41 is as follows.

  (03-38) plane = (0-338) plane> (0-33-8) plane = (03-3-8) plane

  For this reason, in order to make the formed oxide film uniform, the oxidation rates of the other surfaces are matched with the oxidation rates of the (03-38) plane and the (0-338) plane, which have high oxidation rates. Therefore, the (0-33-8) plane and the (03-3-8) plane are irradiated with a silicon (Si) ion beam 42 to perform ion implantation. Here, since the (0-33-8) plane and the (03-3-8) plane are equivalent in atomic arrangement and have the same oxidation rate, if the same amount of Si ions is implanted into both planes, Good.

Further, since the (03-3-8) plane and the (0-33-8) plane are equivalent in atomic arrangement and have the same oxidation rate, the (0-33-8) plane and the (03-3-8) plane Si ions may be implanted into the two surfaces. In Embodiment 2, since the difference in oxidation rate is small, the amount of Si ions implanted into the (0-33-8) plane and the (03-3-8) plane is 5 × 10 ¹⁵ cm ⁻² . The dose may be about 10 keV. In the second embodiment, ion implantation is performed in three stages, ie, first ion implantation, second ion implantation, and third ion implantation.

  FIG. 14 is an explanatory diagram showing the planar irradiation of the Si ion beam and the plan view of the trench at the time of the first ion implantation. As shown in FIG. 14, the first ion implantation was performed on the (0-33-8) plane. The cross-sectional view of the main part at this time is the same as that shown in FIG. The Si ion beam 42 is selectively irradiated only on the side wall having the (0-33-8) plane of the trench 41, so that the bottom surface of the trench 41 is not irradiated.

  Next, the second ion implantation was performed on the (03-3-8) plane. The main part sectional view at this time is the same as that in FIG. At this time, the Si ion beam 42 is selectively irradiated only to the side wall having the (03-3-8) plane of the trench 41 and is not irradiated to the bottom surface of the trench 41.

In the first ion implantation and the second ion implantation described above, Si ions are not implanted into the bottom surface of the trench 41. Therefore, in the third ion implantation, θ ₁ = 0 degree shown in FIG. 5 is used, and the ion implantation is performed only on the bottom surface of the trench 41 perpendicular to the surface of the n ⁺ source region 5. The amount of Si ions implanted by the third ion implantation is, for example, a dose amount of about 50 keV with a dose amount of 5 × 10 ¹⁵ cm ⁻² .

  After the above-described steps, gate oxidation can be performed to obtain a main part cross section similar to FIG. 9 shown in the first embodiment. In the subsequent process, a UMOSFET similar to that shown in FIG. 10 can be obtained by performing a generally known UMOSFET manufacturing process.

  In the second embodiment, the planar pattern of the trench 41 is a rhombus cell shape, which is somewhat difficult to handle, but the MOS channel is formed on the (03-38) plane and a crystal plane having an atomic arrangement equivalent to this plane. Therefore, it shows high channel mobility. Therefore, channel resistance can be suppressed more than in the first embodiment.

  As described above, according to the second embodiment, the oxidation rate of the side wall in the trench can be made substantially constant. Further, the gate oxide film formed on the side wall in the trench can be formed to have a substantially constant thickness. Further, the channel resistance can be suppressed as compared with the first embodiment.

(Embodiment 3)
Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. In the first embodiment, the Si ions are directly implanted into the side wall forming the trench. However, in the third embodiment, an oxide film is formed before the Si ions are implanted, and the oxide film is interposed through the oxide film. This is the point where ion implantation is performed. FIG. 15 is an explanatory view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention.

The cross-sectional shape shown in FIG. 2 is obtained through the same steps as in the first embodiment. Then, as shown in FIG. 15, screen oxidation is performed to form a screen oxide film 57 as an insulating film on the surface of the n ⁺ source region 55 and the inside of the trench 56 with a thickness of, for example, 10 to 50 nm. Next, as shown in FIG. 7, the Si ion beam is irradiated with the Si ion beam at a predetermined angle with respect to the normal to the surface of the n ⁺ source region 5. At this time, ion implantation is performed by irradiating Si ions while rotating the substrate.

  By irradiating the Si ion beam while rotating the substrate, it is possible to implant substantially the same amount of Si ions into the screen oxide film 57 inside the trench 56. However, since the thickness of the screen oxide film 57 formed on the sidewall of the trench 56 is not uniform, the amount of Si ions implanted into the sidewall of the trench 56 through the screen oxide film 57 is not uniform. Specifically, in the portion where the screen oxide film 57 is thick, the amount of Si ions implanted into the sidewall of the trench 56 is relatively small. On the other hand, in the portion where the screen oxide film 57 is thin, the amount of Si ions is relatively large.

  Subsequently, the screen oxide film 57 is removed, and a gate oxide film is formed as a new oxide film by oxidation. By this oxidation, the gate oxide film is formed almost uniformly. This is due to the following reason. Due to the screen oxidation, the screen oxide film 57 is formed thinner on the crystal surface having a low oxidation rate than the crystal surface having a high oxidation rate.

  Further, the screen oxide film 57 is formed relatively thick with respect to the crystal plane having a high oxidation rate. Since the amount of Si ions implanted into the side wall of the trench 56 is larger in the portion where the screen oxide film 57 is thin than in the portion where the screen oxide film 57 is thick, the oxidation rate of the side wall of the trench 56 is increased. Therefore, a substantially uniform gate oxide film can be formed on the sidewall of the trench 56. Further, since the substrate is rotated, the Si ion beam is sufficiently injected also into the trench bottom. Therefore, a sufficient thickness of the gate oxide film on the bottom surface of the trench 56 can be secured.

  As described above, according to the third embodiment, the oxidation rate of the side wall in the trench can be made substantially constant. Further, the gate oxide film formed on the side wall in the trench can be formed to have a substantially constant thickness. In addition, since it is not necessary to adjust the amount of ions implanted into each side surface forming the trench, the process can be simplified.

(Embodiment 4)
Next, a method for manufacturing a semiconductor device according to Embodiment 4 of the present invention will be described. In the first to third embodiments, the planar pattern of the trench is cellular, but in the fourth embodiment, the planar pattern of the trench is striped. Next, a trench whose planar pattern is a stripe shape is shown.

  FIG. 16 is an explanatory view showing a trench having a lattice-like planar pattern. In FIG. 16, the trench 61 extends in the <0001> direction and the <1-100> direction. FIG. 17 is an explanatory diagram showing a trench having a striped planar pattern. In FIG. 17, the crystal planes of the side walls forming the trench 62 are the (000-1) plane, the (1-100) plane, the (-1100) plane, and the (0001) plane, respectively. The (0001) plane and the (000-1) plane are rectangles extending in the <1-100> direction.

  Moreover, FIG. 18 is explanatory drawing which shows the trench which has a grid | lattice-like plane pattern. In FIG. 18, the crystal planes of the sidewalls forming the trench 63 are the (03-3-8) plane, the (0-338) plane, the (0-33-8) plane, and the (03-38) plane, respectively. The trenches 63 are formed in a lattice shape. The planar pattern of the trenches shown in FIGS. 16 to 18 is shown for the configuration of the lattice-like or stripe-like semiconductor device. FIG. 19 is a fragmentary cross-sectional view showing a semiconductor device having a striped planar pattern.

  In FIG. 19, the same reference numerals are assigned to the same names as those in FIG. The difference from FIG. 10 is that there is no gate lead-out wiring 16 on the gate electrode 11. This is because when the trench 8 has a stripe shape, the gate lead-out wiring 16 may be drawn from the stripe end portion of the stripe-like trench 8.

  In Embodiments 1 to 3 described above, silicon carbide is used as an example of a compound semiconductor, but other compound semiconductors can be similarly applied. When a compound semiconductor other than silicon carbide is used, the ions implanted into the trench side walls may be ions that can increase the oxidation rate.

As described above, according to the manufacturing how the semiconductor device, the thickness of the gate oxide film formed on the trench sidewalls substantially uniformly formed, a high withstand voltage of the semiconductor device, and is possible to realize a high speed operation simultaneously it can.

  In the above-described embodiment, the MOSFET has been described as an example of the semiconductor device. However, the present invention relates to a silicon carbide semiconductor element having an insulated gate, such as an IGBT or an insulated gate thyristor, and the insulated gate has a trench gate structure. This can be applied to all semiconductor devices.

As described above, manufacturing how the semiconductor device according to the present invention, MOSFET, is useful to the power converter such as an inverter device IGBT is used, is particularly suitable for electrical equipment of the switching element for a motor vehicle.

It is sectional drawing shown about the structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing shown about the structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is explanatory drawing shown about the surface orientation of the side wall which comprises a trench. It is explanatory drawing which shows the planar irradiation of the Si ion beam at the time of 1st ion implantation, and the top view of a trench. It is principal part sectional drawing shown about the Si ion implanted. It is explanatory drawing which shows the planar irradiation of the Si ion beam at the time of 2nd ion implantation, and the top view of a trench. It is sectional drawing shown about the structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing shown about the structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing shown about the structure in the middle of manufacture of the semiconductor device concerning Embodiment 1 of this invention. FIG. 6 is an explanatory diagram showing a UMOSFET manufactured by the method for manufacturing the semiconductor device of the first embodiment. It is a graph shown about the thickness and acceleration energy of an oxide film. It is a graph shown about the oxidation rate at the time of ion-implanting to each crystal plane. FIG. 6 is an explanatory view showing the surface orientation of the side surface constituting the trench 41. It is explanatory drawing which shows the planar irradiation of the Si ion beam at the time of 1st ion implantation, and the top view of a trench. It is explanatory drawing shown about the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. It is explanatory drawing which shows the trench which has a grid | lattice-like plane pattern. It is explanatory drawing which shows the trench which has a striped planar pattern. It is explanatory drawing which shows the trench which has a grid | lattice-like plane pattern. It is principal part sectional drawing which shows the semiconductor device which has a striped planar pattern. It is a graph shown about the relationship between the angle from C surface, and an oxidation rate.

Explanation of symbols

1 n ⁺ silicon carbide substrate 2 n ⁻ drift region 3 n current diffusion region 4 p well region 5 n ⁺ source region 6 protective oxide film 7 aluminum mask 8 trench 9 silicon ion beam 10 gate oxide film

Claims (5)

A first forming step of forming a semiconductor region having a higher resistance than the semiconductor substrate on the surface of the semiconductor substrate made of silicon carbide crystal;
A second forming step of forming a trench reaching the semiconductor region formed by the first forming step;
Implanting a plurality of side walls with different oxidation rates constituting the inner side wall of the trench with an amount of ions according to the oxidation rate of each side wall;
A third forming step of oxidizing an inner wall of the trench into which the ions have been implanted in the implantation step, and forming an insulating film having a substantially uniform thickness on the inner wall of the trench ;
Only including,
In the implantation step, ions are separately implanted into the other sidewalls except the sidewall having the fastest oxidation rate of the trench so that the oxidation rate of each sidewall of the trench becomes the same rate. A method of manufacturing a semiconductor device, wherein ions are implanted into the bottom surface of the trench at the same time when ions are implanted into opposite sidewalls . A first forming step of forming a semiconductor region having a higher resistance than the semiconductor substrate on the surface of the semiconductor substrate made of silicon carbide;
  A second forming step of forming a trench reaching the semiconductor region formed by the first forming step;
  A third formation in which the inner side wall of the trench formed by the second forming step is oxidized, and an insulating film is formed on each side wall of the trench so that the side wall has a low oxidation rate and is thinner than the side wall having a high oxidation rate. Process,
  By implanting the same amount of ions into all the sidewalls of the trench through the insulating film formed in the third forming step, a thick insulating film is formed on the sidewall of the trench where the thin insulating film is formed. Implanting a larger amount of ions than the trench sidewalls;
  A method for manufacturing a semiconductor device, comprising: Removing the insulating film from the inner wall of the trench;
  A fourth forming step of oxidizing the inner sidewall of the trench into which the ions have been implanted by the implantation step and forming a new insulating film on the inner sidewall of the trench;
  The method of manufacturing a semiconductor device according to claim 2, comprising: The method of manufacturing a semiconductor device according to claim 1, wherein the silicon carbide is a four-layer periodic hexagonal crystal. The plane orientation of the main surface of the semiconductor substrate is a (11-20) plane or a plane equivalent to the (11-20) plane, and at least one of crystal planes constituting the trench is (03-38). 5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a plane or a plane equivalent to the (03-38) plane.

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