JP2020191401A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

To provide a semiconductor device that reduces basal surface dislocation in a silicon carbide layer.SOLUTION: A semiconductor device comprises: an electrode layer 20; a first silicon carbide layer 11 of a first conductivity type which is arranged directly on the electrode layer, and has a basal surface dislocation density of 1 piece/cm2 or more; a second silicon carbide layer 12 of a first conductivity type which has a lower impurity concentration than the first silicon carbide layer 11, and is arranged on the first silicon carbide layer 11; and a silicon carbide region 13 of the second conductivity type which is arranged on the second silicon carbide layer 12 or in the second silicon carbide layer 12.SELECTED DRAWING: Figure 3

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In recent years, silicon carbide (SiC) has been attracting attention as one of the semiconductor materials to replace silicon (Si). Since the band gap of silicon carbide is as large as about 3 times that of silicon, it has high withstand voltage characteristics. By using a semiconductor device that operates with a large number of carriers, on-resistance can be reduced and excellent operating characteristics at high temperatures can be obtained. Further, since the thermal conductivity of silicon carbide is higher than that of silicon, the cooling device for cooling the semiconductor device can be made smaller. Silicon carbide having such characteristics is expected to be applied to semiconductor devices for electric power, for example.

A single crystal silicon carbide substrate is manufactured by using, for example, a sublimation method, and the silicon carbide substrate manufactured by this sublimation method has a defect called basal plane dislocation (BPD). It has been known.

It will be described below with reference to FIGS. 1 (A) to 1 (C) that if the silicon carbide substrate of the semiconductor device has a basal plane dislocation, deterioration of electrical characteristics with time may be observed. ..

As shown in FIG. 1A, the semiconductor device 100 includes a silicon carbide substrate 110, an n-type drift layer 111, and a p ⁺ type layer 112. If basal plane dislocations are present on the surface of the silicon carbide substrate 110, the basal plane dislocations BPD may propagate into the n-type drift layer 111 when the n-type drift layer 111 is epitaxially grown on the silicon carbide substrate 110. The basal plane dislocation BPD formed during epitaxial growth remains in the n-type drift layer 111.

As shown in FIG. 1 (B), when the semiconductor device 100 performs a bipolar operation such that a small number of carriers are generated, recombination of holes h and electrons e occurs in the vicinity of the basal dislocation BPD, resulting in high energy. Occur.

As shown in FIG. 1 (C), when high energy is applied to the basal dislocation BPD, a phenomenon is observed in which stacking defect SF occurs starting from the BPD. Since this stacking defect hinders the movement of carriers in a wide range, the on-resistance is increased, and an increase in the forward voltage of the semiconductor device 100 with time is observed.

Therefore, as shown in FIG. 2, a dislocation conversion layer 113 that converts dislocations of the basal plane of the silicon carbide substrate into blade-shaped dislocations is formed on the silicon carbide substrate 110, and an n-type drift layer 111 is formed on the dislocation conversion layer 113. And it has been proposed to epitaxially grow the p ⁺ type layer 112 in order (for example, Patent Document 1).

The dislocation conversion layer 113 converts the basal plane dislocations that have penetrated from the surface of the silicon carbide substrate 110 into blade-shaped dislocations when this layer is epitaxially grown on the silicon carbide substrate 110. It has been confirmed that the blade-shaped dislocations have less influence on the electrical characteristics of the semiconductor device than the basal plane dislocations. Therefore, even when the blade-shaped dislocation propagates from the dislocation conversion layer 113 to the n-type drift layer 111, it is considered that the influence on the electrical characteristics of the semiconductor device 200 is small.

International Publication No. 2017/199792

However, also in the semiconductor device 200 shown in FIG. 2, when a minority carrier reaches the basal plane dislocation of the silicon carbide substrate 110 during the operation of the semiconductor device 200, a stacking defect occurs starting from the basal plane dislocation, resulting in a stacking defect. May propagate into the n-type drift layer 111.

An object of the present specification is to provide a semiconductor device and a method for manufacturing the semiconductor device that reduce dislocations of the basal plane in the silicon carbide layer.

According to the semiconductor device disclosed in the present specification, the electrode layer, the first conductive type first silicon carbide layer arranged directly on the electrode layer and having a basal plane dislocation density of 1 piece / cm ² or less, and the like. A first conductive type second silicon carbide layer having a lower impurity concentration than the first silicon carbide layer and arranged on the first silicon carbide layer, and on the second silicon carbide layer or in the second silicon carbide layer. It includes a second conductive type silicon carbide region to be arranged. The electrode layer contains metal and silicon silicide, and / or metal.

According to other semiconductor devices disclosed in the present specification, the ratio of the number of carbon atoms to the number of silicon atoms in the electrode layer and the raw material gas containing silicon and carbon is 0.7 or more and 1.1 or less. After growing on the silicon carbide substrate using the raw material gas within the range of, the silicon carbide substrate is removed and formed, and the first conductive type first silicon carbide layer is arranged directly on the electrode layer. , A first conductive type second silicon carbide layer having a lower impurity concentration than the first silicon carbide layer and arranged on the first silicon carbide layer, and on the first silicon carbide layer or in the second silicon carbide layer. It is provided with a second conductive type third silicon carbide region arranged in.

In these semiconductor devices, the impurity concentration of the first silicon carbide layer is preferably in the range of 1 × 10 ¹⁷ cm ^-3 or more and 2 × 10 ¹⁹ cm ^-3 or less.

In these semiconductor devices, it is preferable that the region on the electrode layer side of the first silicon carbide layer contains first conductive type impurities and second conductive type impurities.

In these semiconductor devices, the interface on the electrode layer side of the first silicon carbide layer is preferably amorphous.

In these semiconductor devices, the total thickness of the first silicon carbide layer and the second silicon carbide layer is 50 μm or more, and the impurity concentration of the second silicon carbide layer is 3 × 10 ¹⁵ cm ^-3 or less. Is preferable.

In these semiconductor devices, the basal plane dislocation density of the second silicon carbide layer is preferably lower than that of the first silicon carbide layer.

These semiconductor devices are preferably MOSFETs or IGBTs.

Further, according to the method for manufacturing a semiconductor device disclosed in the present specification, the ratio of the number of carbon atoms to the number of silicon atoms in the raw material gas containing silicon and carbon is 0.7 or more and 1.1 or less. The first step of forming the first conductive type first silicon carbide layer on the silicon carbide substrate using the raw material gas within the range, and the first conductive type having an impurity concentration lower than that of the first silicon carbide layer. The second step of forming the second silicon carbide layer on the first silicon carbide layer and the second conductive type silicon carbide region are formed on the first silicon carbide layer or formed in the first silicon carbide layer. A third step of removing the silicon carbide substrate to expose the first silicon carbide layer, and a fifth step of forming an electrode layer on the exposed surface of the first silicon carbide layer. Including.

In the method for manufacturing this semiconductor device, in the first step, the ratio R1 of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the first silicon carbide layer is R1, and in the second step, silicon and carbon. A second silicon carbide layer is formed by using a raw material gas having a ratio R2 of carbon atoms to the number of silicon atoms, and the ratio R1 / R2 of the ratio R1 to the ratio R2 is It is preferably in the range of 0.46 to 0.99.

In the method for manufacturing a semiconductor device, in the first step, a gas containing an impurity that gives conductivity of the first conductive type and a gas containing an impurity that gives conductivity of the second conductive type can be added as a raw material gas. preferable.

In the method for manufacturing this semiconductor device, it is preferable to use dry etching or chemical mechanical polishing in the fourth step.

According to the semiconductor device disclosed in the present specification described above, dislocations of the basal plane in the silicon carbide layer can be reduced.

Further, according to the method for manufacturing a semiconductor device disclosed in the present specification described above, a semiconductor device in which dislocations of the basal plane in the silicon carbide layer are reduced can be obtained.

(A) to (C) are diagrams for explaining a conventional semiconductor device. It is a figure explaining another semiconductor device of the prior art. It is sectional drawing which shows the 1st Embodiment of the semiconductor device disclosed in this specification. It is sectional drawing which shows the modification 1 of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the modification 2 of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the modification 3 of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the modification 4 of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the 2nd Embodiment of the semiconductor device disclosed in this specification. It is a figure (the 1) explaining the process of one Embodiment of the manufacturing method of the semiconductor device disclosed in this specification. It is a figure (the 2) explaining the process of one Embodiment of the manufacturing method of the semiconductor device disclosed in this specification. It is a figure (the 3) explaining the process of one Embodiment of the manufacturing method of the semiconductor device disclosed in this specification. It is a figure (the 4) explaining the process of one Embodiment of the manufacturing method of the semiconductor device disclosed in this specification. It is a figure (the 5) explaining the process of one Embodiment of the manufacturing method of the semiconductor device disclosed in this specification. It is a figure (the 6) explaining the process of one Embodiment of the manufacturing method of the semiconductor device disclosed in this specification.

Hereinafter, a preferred embodiment of the semiconductor device disclosed in the present specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to those embodiments, but extends to the inventions described in the claims and their equivalents.

In the present specification and the accompanying drawings, the layer or region labeled n means that the electrons are multi-carriers, and the layer or region labeled p means that the holes are multi-carriers. .. Further, + attached to n or p means that the impurity concentration is higher than that of the layer or region without it, and-attached to n or p means that the impurity concentration is higher than that of the layer or region without it. It means that the concentration is low. In the following embodiments, the first conductive type will be referred to as n type, and the second conductive type will be referred to as p type.

Further, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and adding "-" in front of the Miller index indicates a negative index.

FIG. 3 is a cross-sectional view showing a first embodiment of the semiconductor device disclosed in the present specification. The semiconductor device 10 of the present embodiment is a semiconductor device having a first conductive type silicon carbide layer and a second conductive type silicon carbide layer. Specifically, the semiconductor device 10 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench-type gate electrode.

The semiconductor device 10 includes an n ⁺ type rearrangement conversion layer 11 which is a first conductive type silicon carbide epitaxial layer, a silicon carbide epitaxial layer 12, a second conductive type p-type silicon carbide epitaxial layer 13, and a first conductive type. The source region 14 and the second conductive type contact region 15 are provided. Further, the semiconductor device 10 includes a gate insulating film 16, a gate electrode 17, an interlayer insulating film 18, a source electrode 19, and a drain electrode 20.

First, the n ⁺ type dislocation conversion layer 11 will be described below. The n ⁺ type dislocation conversion layer 11 is a silicon carbide epitaxial layer to which impurities giving the polarity of the first conductive type, for example, nitrogen are added. The n ⁺ type dislocation conversion layer 11 is formed on a single crystal silicon carbide substrate in the manufacturing process of the semiconductor device 10 (see FIG. 9). n ⁺ -type dislocation conversion layer 11, in the manufacturing process of the semiconductor device 10, the basal plane dislocations penetrated from the silicon carbide substrate to the n ⁺ type dislocation conversion layer 11 converts the edge dislocations, the silicon carbide epitaxial layer 12 on Suppresses the propagation of basal dislocations into other layers or regions located in. In the manufacturing process of the semiconductor device 10, after the other components, such as silicon carbide epitaxial layer 12 is formed, the lower surface of the silicon carbide substrate of n ⁺ -type dislocation conversion layer 11 is removed on the n ⁺ -type dislocation conversion layer 11 The drain electrode 20 is formed.

Since the silicon carbide substrate is removed from the semiconductor device 10, even if a minority carrier passes through the n ⁺ type dislocation conversion layer 11 and reaches the drain electrode 20 during operation, the basal plane existing in the silicon carbide substrate is present. Stacking defects due to dislocations do not occur.

The n ⁺ type dislocation conversion layer 11 is a raw material gas containing silicon and carbon, and the C / Si ratio of the number of carbon atoms to the number of silicon atoms is in the range of 0.7 or more and 1.1 or less. Formed using gas. It is considered that the larger the C / Si ratio in the raw material gas, the more the n ⁺ type dislocation conversion layer 11 formed has an action of converting the basal plane dislocations of the silicon carbide substrate into blade-shaped dislocations. Since the n ⁺ type dislocation conversion layer 11 has a C / Si ratio of 0.7 or more in the raw material gas, when it grows on the silicon carbide substrate, the basal plane dislocation of the silicon carbide substrate is converted into blade-shaped dislocations. It is possible to sufficiently suppress the dislocation of the basal plane from propagating through the n ⁺ type dislocation conversion layer 11. On the other hand, if the C / Si ratio in the raw material gas is larger than 1.1, defects due to the C / Si ratio may occur in the n ⁺ type dislocation conversion layer 11. The C / Si ratio in the raw material gas can be determined, for example, by the flow rate ratio of the gas containing silicon and the gas containing carbon at the time of manufacturing the n ⁺ type dislocation conversion layer 11.

The C / Si ratio in the raw material gas is 0.8 or more and 1.0 or less, in particular, at the interface between the silicon carbide substrate and the n ⁺ type dislocation conversion layer 11, the basal dislocation of the silicon carbide substrate is cut. It is preferable from the viewpoint of converting to a state dislocation and preventing the basal plane dislocation from entering the n ⁺ type dislocation conversion layer 11.

Normally, the C / Si ratio of the raw material gas used to form the silicon carbide layer of the semiconductor device is in the range of 1.1 or more and 1.5 or less, so that the n ⁺ type dislocation conversion layer described above is used. The C / Si ratio of the source gas used to form 11 is different from the range normally used to form the silicon carbide layer.

As described above, the n ⁺ type dislocation conversion layer 11 of the semiconductor device of the present embodiment is a raw material gas containing silicon and carbon, and the C / Si ratio of the number of carbon atoms to the number of silicon atoms is 0.7. As described above, it is formed by using a raw material gas in the range of 1.1 or less. As described above, the semiconductor device of the present embodiment has a manufacturing process as a part of the components. Hereinafter, the reason why the semiconductor device of the present embodiment has a manufacturing process as a part of its features will be described. The difference between the semiconductor device of the present embodiment and the prior art is that when the n ⁺ type dislocation conversion layer, which is a silicon carbide layer, grows and is formed on the silicon carbide substrate, the basal plane dislocation of the silicon carbide substrate is blade-shaped dislocation. Although it has an action of converting to and does not contain many unnecessary defects, in light of the non-uniformity of the n ⁺ type dislocation conversion layer, a silicon carbide layer having no such action and n ⁺ It is very difficult to unequivocally specify the structure or characteristics related to the difference from the type dislocation conversion layer 11 by wording. On the other hand, the configuration of the n ⁺ type dislocation conversion layer may be possible in principle by using observation with an electron microscope, elemental analysis, etc., but the semiconductor device of the present embodiment and the semiconductor device of the prior art are used, respectively. Only a number that is statistically significant must be manufactured, the results of electron microscope observation and element analysis must be obtained, and after statistical processing, a meaningful index and its value that distinguish the present embodiment from the prior art must be found. However, it will take a huge amount of time and cost. Moreover, since there are enormous possibilities for the prior art, it is difficult to uniquely determine a statistically significant number. Therefore, it is not practical to find the above-mentioned index and its value and directly specify the characteristics of the semiconductor device of the present embodiment only by the structure or characteristics of the object. Based on the above idea, it is characterized by having the effect of converting the basal plane dislocations of the silicon carbide substrate into blade-shaped dislocations when grown and formed on the silicon carbide substrate and not containing many unnecessary defects. For the sake of specification, a manufacturing process is included as part of the configuration of the semiconductor device of the present embodiment.

Since the n ⁺ type dislocation conversion layer 11 converts the basal plane dislocations of the silicon carbide substrate into blade-shaped dislocations mainly at the interface between the silicon carbide substrate and the n ⁺ type dislocation conversion layer 11, the n ⁺ type dislocation conversion layer 11 The dislocation density of the basal plane is 1 piece / cm ² or less, preferably 0.1 piece / cm ² or less. The smaller the number of basal dislocations contained in the n ⁺ type dislocation conversion layer 11, the more preferable it is. However, the n ⁺ type dislocation conversion layer 11 usually has a basal dislocation density of at least 100 pieces / cm ² . The basal dislocation density of the n ⁺ type dislocation conversion layer 11 can be measured using, for example, an X-ray topography method.

in the thickness direction of the n ⁺ -type dislocation conversion layer 11, the basal plane dislocations contained in the n ⁺ -type dislocation conversion layer 11, in the direction from the drain electrode 20 side to the silicon carbide epitaxial layer 12 side, an n ⁺ -type dislocation conversion layer There may be a case where it exists so as to penetrate the eleven, a case where it is converted into a blade-shaped dislocation at an intermediate depth, and a case where it penetrates to an intermediate depth and stops. In this specification, the basal plane dislocation density of the n ⁺ -type dislocation conversion layer 11 in the thickness direction of the n ⁺ -type dislocation conversion layer 11, the number of basal plane dislocations is meant the density at a depth of maximum.

When the basal plane dislocation of the silicon carbide substrate is converted into a blade dislocation at the interface between the silicon carbide substrate and the n ⁺ type dislocation conversion layer 11, the basal plane dislocation of the silicon carbide substrate is n ⁺ type. Since it does not penetrate into the dislocation conversion layer 11, it is not included in the dislocation density of the basal plane of the n ⁺ type dislocation conversion layer 11.

Further, the concentration of impurities of the first conductive type added to the n ⁺ type dislocation conversion layer 11 is preferably in the range of 1 × 10 ¹⁷ cm ^-3 or more and 2 × 10 ¹⁹ cm ^-3 or less. When the impurity concentration is 1 × 10 ¹⁷ cm ^-3 or more, the basal plane dislocations of the silicon carbide substrate can be sufficiently converted into blade-shaped dislocations. On the other hand, if the impurity concentration is 2 × 10 ¹⁹ cm ^-3 or more, defects such as double shockley type stacking defects may occur in the n ⁺ type dislocation conversion layer 11.

It is preferable that the n ⁺ type dislocation conversion layer 11 and the drain electrode 20 are ohmic-bonded from the viewpoint of reducing electrical resistance. From this point of view, for example, the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11 is preferably in an amorphous state. At the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11, it is preferable that a region of 10% or more, particularly 50% or more, is amorphous from the viewpoint of obtaining ohmic contact.

Further, in the region near the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11, it is preferable that the impurity concentration of the first conductive type is 1 × 10 ¹⁸ cm ^-3 or more from the viewpoint of obtaining ohmic contact. .. The region of the n ⁺ type dislocation conversion layer 11 near the interface on the drain electrode 20 side may be, for example, in the range of a depth of up to 0.3 μm from the interface on the drain electrode 20 side, particularly up to 0.05 μm. it can.

Further, a silicide region of metal and silicon may be formed in a region near the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11 to make ohmic contact with the drain electrode 20. As the metal, for example, nickel can be used.

Further, a second conductive type impurity such as boron may be added to the region near the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11. Boron, so to form a deep acceptor level in the n ⁺ -type dislocation conversion layer 11 to trap positive holes, to reduce the hole density in the n ⁺ -type dislocation conversion layer 11. Further, even when the holes trapped in boron are thermally excited, the n ⁺ type dislocation conversion layer 11 has a high concentration of impurities of the first conductive type, so that it recombines with electrons, so that the holes, which are minority carriers, The life can be reduced. Here, the region near the interface is a region 1 μm from the interface. In the region near the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11, for example, the concentration of boron can be in the range of 1 × 10 ¹⁴ cm ^-3 or more and 1 × 10 ¹⁷ cm ^-3 or less. .. The above is the description of the n ⁺ type dislocation conversion layer 11.

The silicon carbide epitaxial layer 12 is arranged on the n ⁺ type dislocation conversion layer 11. The silicon carbide epitaxial layer 12 has a first conductive type n-type region 12a and a first conductive type n ⁺ type region 12b.
It has a second conductive type first p ⁺ base region 12c and a second conductive type second p ⁺ base region 12d.

The n-type region 12a is arranged on the n ⁺ -type dislocation conversion layer 11. The n-type region 12a is an n-type drift layer in which impurities that give the polarity of the first conductive type, for example, nitrogen, are added to the silicon carbide epitaxial layer at an impurity concentration lower than that of the n ⁺ type dislocation conversion layer 11.

The total thickness of the n-type region 12a and the n ⁺ -type dislocation conversion layer 11 is preferably 50 μm or more in order to secure the mechanical strength of the semiconductor device 10. For example, when the thickness of the n ⁺ type dislocation conversion layer 11 is 20 μm, the thickness of the n-type region 12a is preferably at least 30 μm. Here, from the viewpoint of setting the withstand voltage of the semiconductor device 10 to 3300 volts, the impurity concentration in the n-type region 12a is preferably 3 × 10 ¹⁵ cm ^-3 or less. Further, if the impurity concentration of the n-type region 12a is 3 × 10 ¹⁵ cm ^-3 or less and the thickness of the n-type region 12a is 60 μm, the withstand voltage of the semiconductor device 10 can be increased to 6500 volts. The lower limit of the impurity concentration in the n-type region 12a and the upper limit of the thickness of the n-type region 12a and the n ⁺ type dislocation conversion layer 11 are determined from the viewpoint of electrical characteristics such as on-resistance of the semiconductor device 10 and withstand voltage. It will be decided as appropriate. The lower limit of the impurity concentration in the n-type region 12a is usually about 1 × 10 ¹³ cm ^-3 .

The n-type region 12a is a raw material gas containing silicon and carbon, and uses a raw material gas in which the C / Si ratio of the number of carbon atoms to the number of silicon atoms is in the range of 1.1 or more and 1.5 or less. Is preferably formed. When the C / Si ratio in the raw material gas is 1.1 or more, the uptake amount of nitrogen, which is an impurity giving n-type conductivity, can be stabilized. Further, the basal dislocation density of the n-type region 12a is preferably lower than that of the n ⁺ -type dislocation conversion layer 11. On the other hand, if the C / Si ratio in the raw material gas is 1.5 or more, defects due to the C / Si ratio may occur in the formed n-type region 12a. The C / Si ratio in the raw material gas can be determined, for example, by the flow rate ratio of the gas containing silicon and the gas containing carbon at the time of manufacturing the n-type region 12a.

Silicon in the raw material gas used to form the n ⁺ type rearrangement conversion layer 11 with respect to the ratio R1 (C / Si ratio) of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the n-type region 12a. The ratio R2 / R1 of the number of carbon atoms to the number of atoms of carbon R2 (C / Si ratio) is preferably in the range of 0.46 to 0.99.

The n ⁺ type region 12b is arranged on the n type region 12a. The n ⁺ type region 12b is formed by adding an impurity that gives the polarity of the first conductive type, for example, nitrogen, to the silicon carbide epitaxial layer at a higher impurity concentration than the n-type region 12a.

The first p ⁺ base region 12c and the second p ⁺ base region 12d are selectively arranged in the n ⁺ type region 12b. The first p ⁺ base region 12c and the second p ⁺ base region 12d are formed by adding an impurity giving the polarity of the second conductive type, for example, aluminum to the silicon carbide epitaxial layer.

The p-type silicon carbide epitaxial layer 13 is arranged on the silicon carbide epitaxial layer 12. In the p-type silicon carbide epitaxial layer 13, impurities giving the polarity of the second conductive type, for example, aluminum, are added to the silicon carbide epitaxial layer at an impurity concentration lower than that of the first p ⁺ base region 12c and the second p ⁺ base region 12d. It is formed. p-type silicon carbide epitaxial layer 13 and the n-type region 12a and the n ⁺ -type region 12b forms the inner PN diode. Further, the 1p ⁺ base region 12c and the 2p ⁺ base region 12d and, n-type region 12a and the n ⁺ -type region 12b forms the inner PN diode. Although the MOSFET having an internal PN diode is a unipolar device, it may perform a bipolar operation in which a small number of carriers are generated.

The trench 10a is arranged so as to penetrate the p-type silicon carbide epitaxial layer 13 and reach the silicon carbide epitaxial layer 12. A gate insulating film 16 and a gate electrode 17 are arranged inside the trench 10a. The gate insulating film 16 is arranged at the bottom and sides of the trench 10a along the inner surface of the trench 10a. The gate electrode 17 is arranged inside the gate insulating film 16. A part of the gate electrode 17 may protrude upward from the trench 10a. In the example shown in FIG. 3, the semiconductor device 10 has two trenches 10a (gate insulating film 16 and gate electrode 17), but the semiconductor device 10 may have more trenches.

The portion of the p-type silicon carbide epitaxial layer 13 in the vicinity of the gate insulating film 16 forms a channel region. During operation of the semiconductor device 10, the current between the source electrode 19 and the drain electrode 20 passes through the channel region.

The second p ⁺ base region 12d is located below the trench 10a. The first p ⁺ base region 12c is arranged between two adjacent trenches 10a. A part of the first p ⁺ base region 12c may be extended toward the trench 10a and connected to the second p ⁺ base region 12d.

The source region 14 and the contact region 15 are selectively arranged on the upper part of the p-type silicon carbide epitaxial layer 13.

The source region 14 is arranged so as to surround the trench 10a in a plan view. The source region 14 is formed by adding an impurity giving the polarity of the first conductive type, for example, nitrogen, to the silicon carbide epitaxial layer at an impurity concentration higher than that of the n-type region 12a.

The contact region 15 is arranged between two adjacent source regions 14. The contact region 15 is formed by adding impurities that give a second conductive type polarity, such as aluminum, to the silicon carbide epitaxial layer at an impurity concentration higher than that of the first p ⁺ base region 12c and the second p ⁺ base region 12d.

The interlayer insulating film 18 is arranged on the gate electrode 17 so as to cover the gate electrode 17. The interlayer insulating film 18 has an opening in which the source electrode 19 is exposed between two adjacent gate electrodes 17.

The source electrode 19 is electrically connected to the source region 14 and the contact region 15. The source electrode 19 is electrically insulated from the gate electrode 17 by the interlayer insulating film 18 and the gate insulating film 16.

(3, lower ^{n +} -type dislocation conversion layer 11) lower surface on the n ⁺ -type dislocation conversion layer 11, the drain electrode 20 are disposed. The drain electrode 20 is formed by, for example, laminating titanium, nickel, and gold layers in order from the n ⁺ type dislocation conversion layer 11 side.

The semiconductor device 10 is a switching element capable of making the channel region between the source electrode 19 and the drain electrode 20 conductive by applying a voltage equal to or higher than the threshold value to the gate electrode 17. .. Since the majority carriers flowing between the source electrode 19 and the drain electrode 20 in the conductive state are electrons, the semiconductor device 10 is a first conductive type (n type) MOSFET.

According to the semiconductor device of the present embodiment described above, dislocations of the basal plane in the silicon carbide layer can be reduced.

Next, the above-mentioned modified examples 1 to 4 of the semiconductor device of the present embodiment will be described below with reference to FIGS. 4 to 7.

FIG. 4 is a cross-sectional view showing a modified example 1 of the semiconductor device of the first embodiment. In the semiconductor device 10 of this modified example, the n ⁺⁺ type recombination promoting layer 21 is arranged between the n ⁺ type dislocation conversion layer 11 and the n-type region 12a.

Since the n ⁺ type dislocation conversion layer 11 may have a small number of basal dislocations, a minority carrier recombines in the vicinity of the basal dislocation in the n ⁺ type dislocation conversion layer 11 to form a semiconductor. Stacking defects may occur in the device 10.

The n ⁺⁺ type recombination promoting layer 21 has a defect level that recombines with holes, which are minority carriers that move from the source electrode 19 side to the drain electrode 20 side, and the holes are n ⁺ type dislocation conversion layers. Suppress moving to 11.

The n ⁺⁺ type recombination promoting layer 21 is formed by adding an impurity giving the polarity of the first conductive type, for example, nitrogen, to the silicon carbide epitaxial layer at an impurity concentration higher than that of the n ⁺ type dislocation conversion layer 11.

The impurity concentration of the n ⁺⁺ type recombination promoting layer 21 can be in the range of 1 × 10 ¹⁷ cm ^-3 or more and 2 × 10 ¹⁹ cm ^-3 or less.

FIG. 5 is a cross-sectional view showing a modified example 2 of the semiconductor device of the first embodiment. The semiconductor device 10 of this modified example is a vertical IGBT (Insulated Gate Bipolar Transistor) having a trench-type gate electrode.

The n ⁺ type dislocation conversion layer 11 has a first conductive type n ⁺ type layer 11a arranged on the n-type region 12a side and a second conductive type p-type layer 11b arranged on the collector electrode 20a side.

The n ⁺ type dislocation conversion layer 11 is different from the first embodiment described above in that it has layers having two polarities in the thickness direction, but the C / Si ratio in the raw material gas and the basal plane dislocation The description of the density is appropriately applied to each of the n ⁺ type layer 11a and the p type layer 11b.

Further, the semiconductor device 10 has an emitter electrode 19a. The other configuration of the semiconductor device 10 is the same as that of the first embodiment described above.

FIG. 6 is a cross-sectional view showing a modified example 3 of the semiconductor device of the first embodiment. The semiconductor device 10 of this modified example is a vertical RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) having a trench-type gate electrode.

A plurality of second conductive type p-type regions 22 are selectively arranged on the portion of the n ⁺ type dislocation conversion layer 11 on the collector electrode 20a side. The p-type region 22 forms a freewheel diode between the emitter electrode 19a and the collector electrode 20a together with the n-type region such as the n-type region 12a. The other configuration of the semiconductor device 10 is the same as that of the first embodiment described above.

FIG. 7 is a cross-sectional view showing a modified example 4 of the semiconductor device of the first embodiment. The semiconductor device 10 of this modified example is a vertical IGBT (Insulated Gate Bipolar Transistor) having a trench-type gate electrode.

The p ⁺ type dislocation conversion layer 11c is a p-type silicon carbide epitaxial layer to which impurities giving the polarity of the second conductive type, for example, aluminum, are added, and the polarity is different from that of the n-type region 12a. The other configuration of the semiconductor device 10 is the same as that of the first embodiment described above.

Next, a second embodiment of the above-mentioned semiconductor device will be described below with reference to FIG. The detailed description of the first embodiment described above is appropriately applied to the points not particularly described with respect to the other embodiments. Further, the same components are designated by the same reference numerals.

FIG. 8 is a cross-sectional view showing a second embodiment of the semiconductor device disclosed in the present specification. The semiconductor device 30 of the present embodiment is a semiconductor device having a silicon carbide layer. Specifically, the semiconductor device 30 is a vertical Schottky barrier type diode.

The semiconductor device 30 includes a first conductive type n ⁺ type rearrangement conversion layer 31, a first conductive type silicon carbide epitaxial layer 32, a second conductive type p-type region 33, and a second conductive type p ^- type. A region 34, a second conductive type p ⁺ type region 35, an anode electrode 36, an interlayer insulating film 37, and a cathode electrode 38 are provided.

The n ⁺ type dislocation conversion layer 31 is a single crystal silicon carbide epitaxial layer doped with impurities that give the polarity of the first conductive type, for example, nitrogen. The above description for the dislocation conversion layer of the first embodiment is appropriately applied to the n ⁺ type dislocation conversion layer 31.

The silicon carbide epitaxial layer 32 is arranged on the n ⁺ type silicon carbide layer 31. The silicon carbide epitaxial layer 32 is an n-type drift layer in which impurities that give the polarity of the first conductive type, for example, nitrogen, are doped into the silicon carbide epitaxial layer at a lower impurity concentration than the dislocation conversion layer 31.

The p-type region 33 and the p ^- type region 34 are selectively arranged on the upper part of the silicon carbide epitaxial layer 32.

The p-type region 33 and the p ^- type region 34 have a ring-shaped shape in a plan view. The p ^- type region 34 is arranged outside the p-type region 33 adjacent to the p-type region 33.

The p-type region 33 is formed by doping the silicon carbide epitaxial layer with impurities that give the polarity of the second conductive type, such as aluminum.

The p ^- type region 34 is formed by doping the silicon carbide epitaxial layer with impurities that give the polarity of the second conductive type, for example, aluminum, at an impurity concentration lower than that of the p-type region 33.

The p ⁺ type region 35 is arranged inside the p-type region 33 at a distance from the p-type region 33. The p ⁺ type region 35 is formed by doping the silicon carbide epitaxial layer with impurities that give the polarity of the second conductive type, for example, aluminum, at a higher impurity concentration than the p-type region 33. The p ⁺ type region 35 and the silicon carbide epitaxial layer 32 form an internal PN diode. Although a Schottky barrier diode having an internal PN diode is a unipolar device, it may perform a bipolar operation in which a small number of carriers are generated.

The anode electrode 36 is arranged on the silicon carbide epitaxial layer 32 so as to cover a part of the p ⁺ type region 35 and the p type region 33.

An active region 30a having a Schottky barrier is formed at the joint portion between the anode electrode 36 and the silicon carbide epitaxial layer 32.

A plurality of p ⁺ type regions 35 are arranged at predetermined intervals in the active region 30a to form a JBS (Junction Barrier Schottky) structure. The junction between the plurality of p ⁺ type regions 35 and the anode electrode 36 may be an ohmic junction or a Schottky junction.

A terminal region 30b is formed around the active region 30a. In the terminal region 30b, a ring-shaped p ^- shaped region 34 is arranged so as to surround the anode electrode 36 in a plan view. Further, the p-type region 33 is arranged so as to extend from the end portion of the active region 30a to the terminal region 30b.

The p-type region 33 and the p ^- type region 34 form a pressure-resistant structure in the terminal region 30b that relaxes the electric field and prevents deterioration of the withstand voltage of the semiconductor device 30. Specifically, the p-type region 33 has a function of avoiding concentration of an electric field at the junction end portion between the silicon carbide epitaxial layer 32 and the anode electrode 36. Further, the p-type region 34 has a function of further dispersing the electric field in the peripheral portion of the active region 30a.

The interlayer insulating film 37 is arranged on the silicon carbide epitaxial layer 32 so as to cover the p-type region 33 and the p ^- type region 34 in the terminal region 30b.

The anode electrode 36 covers the surface of the silicon carbide epitaxial layer 32 exposed in the active region 30a and is in contact with the p-type region 33 in the peripheral portion of the active region 30a. The anode electrode 36 extends from the active region 30a to the middle of the terminal region 30b, and the end of the terminal region 30b of the anode electrode 36 extends over the p-type region 33. Further, the anode electrode 36 covers the p-type region 33 via the interlayer insulating film 37.

The anode electrode 36 is preferably formed by using, for example, a group IVa metal, a group Va metal, a group VIa metal, aluminum or silicon. Further, the anode electrode 36 is preferably formed by using a material containing two or three elements in IVa group metal, Va group metal, VIa group metal, aluminum and silicon.

The Schottky barrier height between the anode electrode 36 and the silicon carbide epitaxial layer 32 is preferably 1 eV or more, for example, when the semiconductor device 30 is used as a high withstand voltage type semiconductor device. Further, the Schottky barrier height of the anode electrode 36 is preferably, for example, 0.5 eV or more and less than 1 eV when the semiconductor device 30 is used as a power supply device.

A cathode electrode 38 is arranged under the n ⁺ type dislocation conversion layer 31. When a positive forward voltage is applied to the anode electrode 36 and a negative forward voltage is applied to the cathode electrode 38, the semiconductor device 30 is in a forward conduction state in which electrons flow from the cathode electrode 38 side to the anode electrode 36 side. On the contrary, when a negative voltage is applied to the anode electrode 36 and a positive reverse voltage is applied to the cathode electrode 38, the semiconductor device 30 is in the reverse direction blocking state. Since the majority carriers flowing between the anode electrode 36 and the cathode electrode 38 in the forward conduction state are electrons, the semiconductor device 10 is a first conductive type (n type) diode.

According to the semiconductor device of the present embodiment described above, the same effect as that of the first embodiment is obtained.

Next, a preferred embodiment of the method for manufacturing a semiconductor device disclosed in the present specification will be described below with reference to FIGS. 9 to 14. The method for manufacturing a semiconductor device of this embodiment is for manufacturing the first embodiment of the semiconductor device described above.

First, as shown in FIG. 9, an n ⁺ type silicon carbide substrate 40 is prepared. The n ⁺ type silicon carbide substrate 40 is a single crystal 4H type silicon carbide substrate to which impurities giving the polarity of the first conductive type, for example, nitrogen are added. The n ⁺ type silicon carbide substrate 40 has a first surface 40a and a second surface 40b. The first surface 40a and the second surface 40b of the n ⁺ type silicon carbide substrate 40 are (0001) surfaces (Si surfaces). The first surface 40a and the second surface 40b may be the (000-1) surface (C surface).

It is preferable that the first surface 40a has an off angle in the range of about 0.05 degrees to 8 degrees from the viewpoint of growing an epitaxial layer having a (0001) surface (Si surface) on the first surface 40a. On the other hand, since the first surface 40a has an off angle, when the first surface 40a has a basal plane dislocation, the basal plane dislocation may propagate to the epitaxial layer growing on the first surface 40a.

Therefore, as shown in FIG. 9, the n ⁺ type dislocation conversion layer 11 is formed on the first surface 40a of the n ⁺ type silicon carbide substrate 40 by epitaxial growth to obtain the substrate structure 50. The n ⁺ type dislocation conversion layer 11 is formed, for example, by using a CVD method. The thickness of the n ⁺ type dislocation conversion layer 11 can be, for example, 0.5 μm to 20 μm.

As the raw material gas for forming the n ⁺ type dislocation conversion layer 11, for example, a gas containing silicon and a gas containing carbon can be used. As the gas containing silicon, for example, silane (SiH ₄ ) can be used. For example, propane (C ₃ H ₈ ) can be used as the gas containing carbon. Further, as the impurity gas, a gas containing nitrogen or a gas containing aluminum can be used. As the gas containing nitrogen, for example, nitrogen (N ₂ ) can be used. As the gas containing aluminum, for example, trimethylaluminum (Al (CH ₃ ) ₃ ) can be used. By adjusting the flow rate ratio of the gas containing silicon and the gas containing carbon, the C / Si ratio in the raw material gas is within the range of 0.7 or more and 1.1 or less, especially 0.8 or more and 1.0 or less. Is preferable. Further, it is preferable that the impurity concentration of the n ⁺ type dislocation conversion layer 11 is in the range of 1 × 10 ¹⁷ cm ^-3 or more and 2 × 10 ¹⁹ cm ^-3 or less by adjusting the flow rate of the impurity gas.

Here, in the early stages of growth of the n ⁺ -type dislocation conversion layer 11, the impurity concentration of the n ⁺ -type dislocation conversion layer 11 may adjust the flow rate of the impurity gas to be lower than 1 × 10 ¹⁸ cm ^-3 .. Here, the initial stage of growth is a stage until the growth of 1 μm. Further, in the initial stage of growth of the ^{n +} -type dislocation conversion layer 11, the concentration of boron in ^{n +} -type dislocation conversion layer 11, 1 × 10 ¹⁴ cm ^-3 or higher, in the range of 1 × ¹⁰ 17 ^{cm -3} or less As such, for example, boron trifluoride (BF ₃ ) gas may be added.

Next, as shown in FIG. 10, the silicon carbide epitaxial layer 12 is formed on the n ⁺ type dislocation conversion layer 11 of the substrate structure 50. The silicon carbide epitaxial layer 12 is formed by, for example, a CVD method. The silicon carbide epitaxial layer 12 is formed so as to have the same composition as the n-type region 12a of the first embodiment of the semiconductor device 10 described above.

As the raw material gas for forming the silicon carbide epitaxial layer 12, for example, a gas containing silicon and a gas containing carbon can be used. As the gas containing silicon, for example, silane (SiH ₄ ) can be used. For example, propane (C ₃ H ₈ ) can be used as the gas containing carbon. Further, as the impurity gas, a gas containing nitrogen or a gas containing aluminum can be used. As the gas containing nitrogen, for example, nitrogen (N ₂ ) can be used. As the gas containing aluminum, for example, trimethylaluminum (Al (CH ₃ ) ₃ ) can be used. It is preferable that the C / Si ratio in the raw material gas is within the range of 1.1 or more and 1.5 or less by adjusting the flow rate ratio of the gas containing silicon and the gas containing carbon. Further, it is preferable that the impurity concentration of the silicon carbide epitaxial layer 12 is set in the range of 3 × 10 ¹⁵ cm ^-3 or less by adjusting the flow rate of the impurity gas.

Next, as shown in FIG. 11, an n-type region 12a, an n ⁺ type region 12b, a first p ⁺ base region 12c, and a second p ⁺ base region 12d are formed in the silicon carbide epitaxial layer 12 of the substrate structure 50. It is formed. Further, on the silicon carbide epitaxial layer 12, a p-type silicon carbide epitaxial layer 13, a source region 14, a contact region 15, a gate insulating film 16, a gate electrode 17, an interlayer insulating film 18, and a source electrode 19 are formed. It is formed.

Here, the n-type region 12a has the same composition as the silicon carbide epitaxial layer 12. Silicon in the raw material gas used to form the n ⁺ type rearrangement conversion layer 11 with respect to the ratio R2 (C / Si ratio) of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the n-type region 12a. The ratio R1 (C / Si ratio) of the number of carbon atoms to the number of atoms of R1 / R2 is preferably in the range of 0.46 to 0.99.

Next, as shown in FIG. 12, the n ⁺ type silicon carbide substrate 40 of the substrate structure 50 is removed to expose the n ⁺ type dislocation conversion layer 11. In the n ⁺ type silicon carbide substrate 40, for example, the back surface side of the substrate structure 50 is removed by using a grinding technique such as diamond lapping. The surface of the n ⁺ type dislocation conversion layer 11 exposed by removing the n ⁺ type silicon carbide substrate 40 by grinding is in an amorphous state.

Further, the n ⁺ type silicon carbide substrate 40 may be ground to a depth in the middle, and then the remaining portion may be removed by using a dry etching technique such as plasma etching. In this case, the end point of the dry etching may be detected by changing the emission color of the plasma.

Next, as shown in FIG. 13, the region where the crystal structure on the surface of the n ⁺ type dislocation conversion layer 11 in the substrate structure 50 is damaged may be removed by polishing using a polishing technique such as chemical mechanical polishing. .. Further, the region where the crystal structure on the surface of the n ⁺ type dislocation conversion layer 11 in the substrate structure 50 is damaged may be removed by using wet etching or dry etching technology.

Further, by heating the substrate structure 50, by rearranging the surface of the n ⁺ -type dislocation conversion layer 11 may reduce the number of defects on the surface of the n ⁺ -type dislocation conversion layer 11. Since step bunching is formed on the surface of the n ⁺ type dislocation conversion layer 11 after heating, the arithmetic mean roughness of the surface can be, for example, 10 nm or more. The upper limit of the arithmetic mean roughness of the surface is usually about 100 nm. The temperature for heating the substrate structure 50 can be in the range of 1500 ° C to 1800 ° C. The step shown in FIG. 13 may be omitted.

Next, as shown in FIG. 14, the drain electrode 20 is formed on the exposed surface of the n ⁺ type dislocation conversion layer 11 of the substrate structure 50, and the semiconductor device 10 is obtained. The drain electrode 20 may be formed directly on the surface of the n ⁺ type dislocation conversion layer 11 having an amorphous state.

In the present invention, the semiconductor device of the above-described embodiment and the method for manufacturing the semiconductor device can be appropriately changed as long as the gist of the present invention is not deviated. Further, the constituent requirements of one embodiment can be appropriately applied to other embodiments.

For example, the semiconductor device of the first embodiment described above was a vertical MOSFET having a trench type gate electrode, but the semiconductor device may be a vertical MOSFET having a planar type gate electrode.

Further, although the semiconductor device of the second embodiment described above is a Schottky barrier type diode, the semiconductor device may be a PN type or a PIN type diode.

Further, in the semiconductor device of the above-described embodiment, the majority carrier is an electron, but a semiconductor device having a large number of carriers may be a hole. In this case, the dislocation conversion layer is a p-type silicon carbide epitaxial layer.

10 Semiconductor device 11 n ⁺ type dislocation conversion layer (first silicon carbide layer)
11an ⁺ type layer 11bp type layer 12 Silicon carbide epitaxial layer 12an type region (second silicon carbide layer)
12b n ⁺ -type region 12c third 1p ⁺ base region 12d first 2p ⁺ base region 13 p-type silicon carbide epitaxial layer (third silicon carbide region)
14 Source region 15 Contact region 16 Gate insulating film 17 Gate electrode 18 Interlayer insulating film 19 Source electrode 19a Emitter electrode 20 Drain electrode 20a Collector electrode 21 n ⁺⁺ type recombination promoting layer 22 p type region 30 Semiconductor device 31 n ⁺ type rearrangement conversion Layer (first silicon carbide layer)
32 Silicon Carbide epitaxial layer (second silicon carbide layer)
33 p-type region 34 p ^- type region 35 p ⁺ type region (third silicon carbide region)
36 Anodic electrode 37 Interlayer insulating film 38 Cathode electrode 40 n ⁺ type silicon carbide substrate 40a 1st surface 40b 2nd surface 50 Substrate structure

Claims (12)

With the electrode layer
A first conductive type first silicon carbide layer which is directly arranged on the electrode layer and has a basal plane dislocation density of 1 piece / cm ² or less.
The first conductive type second silicon carbide layer, which has a lower impurity concentration than the first silicon carbide layer and is arranged on the first silicon carbide layer,
A second conductive type silicon carbide region arranged on the second silicon carbide layer or in the second silicon carbide layer, and
A semiconductor device equipped with. With the electrode layer
After growing on a silicon carbide substrate using a raw material gas containing silicon and carbon in which the ratio of the number of carbon atoms to the number of silicon atoms is in the range of 0.7 or more and 1.1 or less. A first conductive type first silicon carbide layer, which is formed by removing the silicon carbide substrate and is arranged directly on the electrode layer,
The first conductive type second silicon carbide layer, which has a lower impurity concentration than the first silicon carbide layer and is arranged on the first silicon carbide layer,
A second conductive type third silicon carbide region arranged on the second silicon carbide layer or in the second silicon carbide layer, and
A semiconductor device equipped with. The semiconductor device according to claim 1 or 2, wherein the impurity concentration of the first silicon carbide layer is in the range of 1 × 10 ¹⁷ cm ^-3 or more and 2 × 10 ¹⁹ cm ^-3 or less. The semiconductor device according to any one of claims 1 to 3, wherein the interface on the electrode layer side of the first silicon carbide layer is amorphous. The semiconductor device according to any one of claims 1 to 4, wherein the region on the electrode layer side of the first silicon carbide layer contains the first conductive type impurities and the second conductive type impurities. The total thickness of the first silicon carbide layer and the second silicon carbide layer is 50 μm or more, and the impurity concentration of the second silicon carbide layer is 3 × 10 ¹⁵ cm ^-3 or less. The semiconductor device according to any one of the items to 4. The semiconductor device according to any one of claims 1 to 5, wherein the dislocation density of the basal plane of the second silicon carbide layer is lower than that of the first silicon carbide layer. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is a MOSFET or an IGBT. A raw material gas containing silicon and carbon, wherein the ratio of the atomic number of carbon to the atomic number of silicon is in the range of 0.7 or more and 1.1 or less, is used on the first silicon carbide substrate. The first step of forming the conductive first silicon carbide layer and
A second step of forming the first conductive type second silicon carbide layer on the first silicon carbide layer, which has a lower impurity concentration than the first silicon carbide layer.
A third step of forming the second conductive type silicon carbide region on the first silicon carbide layer or in the first silicon carbide layer.
The fourth step of removing the silicon carbide substrate to expose the first silicon carbide layer, and
The fifth step of forming the electrode layer on the exposed surface of the first silicon carbide layer, and
A method for manufacturing a semiconductor device including. In the first step, the ratio R1 of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the first silicon carbide layer is R1.
In the second step, the second silicon carbide layer is formed by using a raw material gas containing silicon and carbon and having a ratio R2 of the number of carbon atoms to the number of silicon atoms.
The method for manufacturing a semiconductor device according to claim 9, wherein the ratio R1 / R2 of the ratio R1 to the ratio R2 is in the range of 0.46 to 0.99. The 9 or 10 according to claim 9 or 10, wherein in the first step, a gas containing an impurity giving conductivity of the first conductive type and a gas containing an impurity giving conductivity of the second conductive type are added as a raw material gas. Manufacturing method of semiconductor equipment. The method for manufacturing a semiconductor device according to any one of claims 9 to 11, which uses dry etching or chemical mechanical polishing in the fourth step.

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