JP4835117B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and more particularly to a vertical semiconductor device for controlling a current flowing between electrodes disposed on the front and back surfaces of a silicon carbide semiconductor substrate and a method for manufacturing the vertical semiconductor device.

  A silicon carbide semiconductor (hereinafter abbreviated as SiC) can form a pn junction and has a wider band gap than other semiconductors such as silicon (Si) and gallium arsenide (GaAs). For example, it is 2.93 eV for 6H-SiC and 3.26 eV for 4H-SiC.

  In principle, there is a trade-off relationship between the on-resistance of the power device and the reverse withstand voltage, which is defined by the forbidden bandwidth. Therefore, it is difficult for current Si power devices to obtain high performance beyond the physical property limit determined by the forbidden bandwidth. However, if a power device is composed of SiC with a wide forbidden bandwidth, the conventional trade-off relationship will be relaxed, and a device that has significantly improved the on-resistance or reverse withstand voltage, or a device that has improved both to a considerable extent. Can be achieved. In other words, the chip size can be extremely reduced while maintaining the on-resistance and the reverse breakdown voltage.

  From the viewpoint of device design, the easiest and most effective method for reducing the on-resistance of the SiC power device and at the same time reducing the chip size is as follows. In the same way as in the case of the Si power device, the large current flow path to be driven is perpendicular to the substrate to minimize the area occupied by the flow path, and the large current inlet (electrode) and outlet (electrode) ) On the front and back of the substrate, that is, a vertical device structure. Today, in order to realize a high-performance and low on-resistance SiC power device, it is an urgent task to develop a practical manufacturing process for forming this vertical device structure.

As is well known, in order to reduce the on-resistance of a SiC vertical power device, it is necessary to minimize all resistance components existing in series in the flow path of a large current. The contact resistance ρ _BC of the ohmic contact on the back surface of the SiC substrate focused on in the present invention is one such resistance component. Here, the “back surface” means another main surface (second surface) opposite to the first main surface (hereinafter referred to as “front surface”) of the SiC substrate on which the main part of the vertical power device is formed. Main surface = “Back”).

  A widely used method for forming a low-resistance ohmic contact is to form a high-concentration conductive impurity region (donor region or acceptor region) on the surface portion of the SiC substrate, and then to form a predetermined region on this region. The contact metal is deposited, and heat treatment (contact annealing) is performed at a temperature of about 900 ° C. to 1000 ° C. in an inert gas atmosphere.

  A contact formation process, which is a kind of metallization, must be incorporated in the final stage of the semiconductor device manufacturing process. However, if high-temperature and rapid contact annealing as described above is applied at the final stage of the manufacturing process, the electrical shock of the semiconductor device may be significantly degraded or unstable due to the thermal shock. For this reason, ohmic contact formation technology that does not require high-temperature contact annealing is awaited, and development has been promoted in various fields. Hereinafter, such an ohmic contact (electrode) is simply referred to as “low temperature contact (electrode)”, and in the description of the present invention, it is defined as a contact that can exhibit ohmic properties without requiring a heat treatment at 450 ° C. or higher.

  With the progress of low-temperature contact formation technology, the technology for forming a low-resistance low-temperature contact on the “surface” of a SiC device substrate has now been almost established. As an example of development of a surface low-temperature contact, Non-Patent Document 1 discloses a low-resistance low-temperature contact in which, for example, Ti is brought into contact with a high-concentration P ion-implanted impurity layer formed on the surface of a SiC substrate.

  However, the technology for producing a low-resistance low-temperature contact on the “back surface” of the vertical SiC device is still in a state where development is still untouched, and development has been far behind that of the “surface”.

Under such circumstances, Patent Document 1 discloses a low-temperature contact formation technique for the second main surface (back surface) of a vertical SiC device. Briefly, after P (phosphorus) is ion-implanted and activated on the back surface of the n-type SiC substrate to form a high concentration impurity layer on the back surface, at least an epi layer serving as a device element is formed on the opposite surface. One layer is grown, and a metal film is deposited on the high-concentration impurity layer on the back surface to complete the back surface low-temperature contact.
Satoshi Tanimoto, Junju Sakizaki, Yasuaki Hayami, Hideyo Ogushi: “Low-resistance contact formed at room temperature on 4H-SiC n + ion-implanted layer” The 47th Joint Conference on Applied Physics (Seigakuin Univ.), Lecture number 30p-YF- 11, Lecture Proceedings, 418 pages US Pat. No. 6,803,243 B2

  However, the technique of Patent Document 1 has a configuration in which the prior art such as Non-Patent Document 1, that is, the surface low-temperature contact technique is simply applied to the back surface without any particular change. For this reason, there may be an ohmic contact, but there is a problem that a sufficiently low resistance cannot be obtained.

For example, according to a verification experiment conducted by the inventors of the present invention using the back surface of a 4H—SiC substrate, the back surface low-temperature contact formed by the technique of Patent Document 1 has a large variation in contact resistance ρ _BC for each manufacture, and the current − In many cases, the voltage characteristics did not show a straight line. Even when the ohmic property is exhibited, even if the contact resistance is small, it is ρ _BC = 10 ⁻⁴ Ωcm ² units, which is 1 to 2 digits higher than the value required for the power device.

  Another problem is that the added back contact-related process adversely affects the surface-side device elements and the surface-side process for forming the element, and the device defect rate increases. For example, when P is ion-implanted on the back surface, the surface of the substrate placed on the platen of the ion implanter is seriously contaminated with metal or contact damaged. These cause device failures. As described above, the technique of Patent Document 1 is almost inconsequential with respect to the risk that the back surface contact process gives to the surface side device element and the surface side process, and it is difficult to say that the technique can be used in the manufacture of an actual vertical power device. .

  In the technique of Patent Document 1, in order to avoid the thermal influence of the activation of the back surface impurity layer on the surface epilayer, a time for forming the surface epilayer is set after the activation step. "Consideration". However, there is no other thing that can be called consideration. Further, when the surface epi layer is a homoepi layer (= SiC), it is an unrealistic manufacturing method to perform the step of forming the surface epi layer after the step of activating the back surface impurities. . This is because, in the process of forming a homoepi layer, it is widely known that the back surface is etched or that the epi film is parasitically attached to the back surface, and the back surface impurity layer disappears or conversely is covered with the parasitic epi film. It is.

  An object of the present invention is to provide a vertical SiC semiconductor device having an extremely low-resistance ohmic contact on the back surface and a method for manufacturing the same.

The present invention is characterized in that an epitaxial layer to which an impurity having the same conductivity type as that of a silicon carbide substrate is added is formed on one main surface of the silicon carbide substrate, and that a silicon carbide substrate is formed on the other main surface of the silicon carbide substrate. A step of forming an impurity layer having the same conductivity type as the substrate, a step of forming an ohmic electrode having hetero - epi properties in the impurity layer by non-heat treatment after forming the first protective film on the epi layer, and an ohmic electrode And forming a second protective film on the ohmic electrode and removing the first protective film to form a main electrode element group on the epi layer. It is a method, and an ohmic electrode having heteroepi property is formed without being subjected to a heat treatment exceeding 450 ° C. until a silicon carbide semiconductor device is completed.

  ADVANTAGE OF THE INVENTION According to this invention, the silicon carbide semiconductor device which has an ohmic contact with a very low resistance on the back surface, and its manufacturing method can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. It should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  In the embodiment of the present invention, an example applied to a high-power vertical Schottky diode having a high breakdown voltage structure formed by ion implantation on the surface side will be described. The present invention is not limited to this type of diode, and can be applied to all vertical SiC semiconductor devices that require a low-resistance low-temperature contact on the back surface.

In addition, the present invention includes all crystal systems such as 4H, 6H, 3C, and 15R (H is hexagonal, C is cubic, and R is rhombohedral), and all crystal planes of each crystal substrate. In the embodiment, for example, the substrate is a 4H-SiC substrate, the front surface (first main surface) is (0001) _Si surface, and the back surface (second main surface) is (000-1). ) It will be explained as _C- plane. This is because this substrate having the (0001) _Si surface as the surface is the substrate most promising and used today as a substrate that gives excellent device characteristics among various SiC substrates.

  In the following description, unless otherwise specified, an SiC substrate on which an epitaxial layer or other film or electrode is formed is called a “substrate”.

<First Embodiment>
In the first embodiment, an example in which the present invention is applied to a Schottky diode, one of two-terminal vertical devices, will be described.

FIG. 1 is a cross-sectional view showing a principal part of a Schottky diode according to a first embodiment of the present invention. The Schottky diode according to the first embodiment includes an n ⁺ type low-resistance single crystal 4H− having a first main surface (front surface) and a second main surface (back surface) opposite to the first main surface. SiC substrate (n ⁺ type single crystal SiC substrate) 1 and main electrode element groups (2, 3 _{a1 to} 3 _an , 5, 7, 8) arranged on the surface side of n ⁺ type single crystal SiC substrate 1; Non-heat-treatment type ohmic electrode (ohmic electrode) 9 in contact with the back surface of n ⁺ type single crystal SiC substrate 1 and back surface wiring 10 in contact with ohmic electrode 9 are provided.

N ⁺ -type single crystal SiC substrate 1 is a silicon carbide substrate having a high n-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more. The n ⁺ type single crystal SiC surface of the substrate 1 is exposed _{(0001) Si} plane, the back surface to expose the ₍₀₀₀₁₎ than _Si surface properties to have an order of magnitude higher oxidation rate _{(0001) C} plane Yes.

The ohmic electrode 9 is provided in contact with the back surface of the n ⁺ -type single crystal SiC substrate 1 having a high-quality, high n-type impurity concentration and high cleanness attribute. In other words, the back surface with which the ohmic electrode 9 is in contact does not include the resistance increasing layer that is formed in the Schottky diode manufacturing process and causes the contact resistance to increase.

The ohmic electrode 9 is a heteroepipolar ohmic electrode (metal) formed without being subjected to heat treatment exceeding 450 ° C. until the completion of the Schottky diode. As the electrode material, aluminum (Al) or titanium (Ti) is most suitable in the sense that extremely low resistance contacts (ρ _BC = 10 ⁻⁶ Ωcm ² units) can be obtained, but it is not limited to this. Absent. Any conductive material having a work function of 4.5 eV or less may be used. Furthermore, a ρ _{BC which} is lower by one digit or more than that of the prior art can be obtained if the conductive material can be formed at room temperature. Examples of the single element material include zirconium (Zr), niobium (Nb), zinc (Zn), tantalum (Ta), magnesium (Mg), vanadium (V), and the like. A single layer film made of any one of these elements, or an alloy film or a composite film made of two or more elements can be used.

“Heteroepi” means that the electrode film is grown on the n ⁺ type single crystal SiC substrate 1 in a completely single crystal state or almost in a single crystal state so as to inherit the crystal periodicity of SiC. ing. The interface between the back surface of n ⁺ -type single crystal SiC substrate 1 and ohmic electrode 9 is extremely steep, and there is no transition layer or reaction layer generated by the reaction between n ⁺ -type single crystal SiC substrate 1 and ohmic electrode 9. Or, if any, its thickness is less than 50 mm.

The n-type impurity concentration on the back surface of the n ⁺ -type single crystal SiC substrate 1, that is, the contact surface with the ohmic electrode 9 is preferably 1 × 10 ¹⁹ / cm ³ or more and less than 1 × 10 ²¹ / cm ^3, more preferably. It is 2 × 10 ¹⁹ / cm ³ or more and 5 × 10 ²⁰ / cm ³ or less.

The main electrode element group preferably includes at least one Schottky electrode or ohmic co-electrode connected to the n ⁺ -type single crystal SiC substrate 1. The Schottky electrode or the ohmic electrode is preferably a non-heat treated electrode formed without being subjected to a heat treatment exceeding 450 ° C. until the completion of the Schottky diode.

In the first embodiment, as an example, the main electrode element group (2, 3 _{a1 to} 3 _an , 5, 7, 8) has a thickness of 10 μm in contact with the surface of the n ⁺ -type single crystal SiC substrate 1 and nitrogen. High-quality n ⁻ type epi layer 2 to which 5 × 10 ¹⁵ / cm ^{3 is} added, and a ring-shaped p-type electric field relaxation region having a width of 2 μm formed in a predetermined region of the surface layer portion of n ⁻ type epi layer 2 at intervals of 2 μm _{3 a1, 3 a2, 3 a3} ‥‥, and 3 _an,, n ^- a field insulating film 5 having an opening 6 formed on the type epi layer 2, n in the bottom of the opening 6 ^- -type epitaxial layer 2 And a surface wiring 8 disposed so as to mechanically and electrically contact the Schottky electrode 7 and close the field opening 6.

The n ⁻ type epi layer 2 is homoepitaxially grown from the (0001) _Si surface exposed on the surface of the n ⁺ type single crystal SiC substrate 1. Note that the back surface of the n ⁺ type single crystal SiC substrate 1 is completely free of parasitic epi films attached by homothepi growth on the front surface side and irregular layers such as crystal distortion and lattice damage, and has the same crystallinity as the inside of the substrate. A crystal plane having a high impurity concentration is exposed, and the ohmic electrode 9 is in contact with the crystal plane.

The p-type field relaxation regions 3 _a1 , 3 _a2 , 3 _a3 ... 3 _an are formed by ion implantation and activation annealing. p-type electric field relaxation region _{3 a1, 3 a2, 3 a3} ‥‥, 3 an the number of (n) depends breakdown voltage of the diode. For example, in the case of a withstand voltage of 1000 V, it is sufficient that there are about five.

Field insulating film 5 is formed by laminating a thermal oxide film of silicon carbide and an insulating film formed thereon by means other than thermal oxidation. The field insulating film 5 covers the entire surface of the SiC substrate including the n ⁻ type epi layer 2, but has an opening 6 for making contact with the electrode on the surface side.

The Schottky electrode 7 forms a Schottky connection with the n ⁻ type epi layer 2 on the bottom surface of the opening 6. The material of the Schottky electrode 7 can be selected from various conductive materials in consideration of the on-voltage and blocking voltage. The outer edge of the Schottky electrode 7 is placed above the p-type electric field relaxation region 3 _a1 (= the innermost p-type annular region).

The outer edge of the surface wiring 8 is designed to be outside the outer edge of the Schottky electrode 7 and inside the outer edge of the p-type electric field relaxation region 3 _a1 when viewed in plan view.

  The back surface wiring 10 is a wiring that uses die bonding.

  Next, a method of manufacturing the vertical Schottky diode shown in FIG. 1 will be described with reference to the sectional process diagrams of FIGS.

(A) First, the prepared (purchased) n ⁺ -type 4H—SiC substrate 1 is sufficiently cleaned, and as shown in FIG. 2A, an n ⁻ -type epi layer 2 having a desired thickness, for example, about 10 μm, is formed on the surface side. Grow homoepitaxially. As the epi layer growth method, a chemical vapor deposition method (CVD) widely used commercially, a proximity sublimation method or a liquid phase growth method in the development stage may be used.

In homoepitaxial growth on the substrate surface, a SiC film adheres to the back surface of the substrate parasitically. Since this SiC film is of low quality and has a very low impurity concentration compared to the substrate, even if it appears to be not attached at first glance, even if it remains slightly (even if the thickness is less than 0.1 μm), ρ of the low temperature contact Increase or vary _BC dramatically. Therefore, in the first embodiment of the present invention, a process for completely removing this is provided after the homoepi growth and before the field insulating film forming process, which will be described later, to reduce ρ _BC compared to the conventional technique. I am trying. Here, an example of performing the process immediately after the homoepi growth process will be described. However, even if the process is performed a little later, the method and the obtained result are almost the same.

Explaining the method in detail, an approximately 2μm SiO ₂ film or PSG film (phosphorus-doped silicate glass) is formed on the surface of the homoepitaxially grown substrate to protect the substrate surface on which the main part of the device is manufactured. After that, the back surface of the substrate is ground or polished by a known cutting means. At this time, care should be taken so that high parallelism is obtained between the front surface and the back surface of the substrate. The protective film formed on the surface is necessary for preventing cutting traces from entering the surface and intrusion of metal contaminants during cutting. Cutting marks and intruding metal contaminants are one of the causes of device failure.

Next, using the well-known photolithography (= photoresist patterning) and dry and wet etching methods, the protective film is patterned to form a hard ion implantation mask for SiC etching for forming an alignment mark for exposure. To do. The dry and wet etching techniques prevent the substrate surface from being damaged by plasma when removing the SiO ₂ film by anisotropic dry etching such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP). Therefore, this is a composite etching technique in which dry etching is stopped immediately before the SiO ₂ film is completely removed, and the remaining portion is removed by wet etching using a buffered hydrofluoric acid solution (BHF) or the like.

  When the etching hard mask is completed, SiC etching is performed using means such as RIE or ICP. When the etching is completed, the hard mask is completely removed using a diluted hydrofluoric acid solution (DHF), and alignment is performed on the substrate. A mark (not shown) is formed.

(B) Subsequently, as shown in FIG. 2B, an ion implantation mask 11 for selectively forming p-type field relaxation regions 3 _a1 , 3 _a2 , 3 _a3 ... On the surface of the n ⁻ -type epilayer 2 is formed. It is formed as follows.

First, an SiO ₂ film having a thickness of about 1.5μm is deposited on the entire surface of the substrate by a CVD method, p-type electric field relaxation region _{3 a1, 3 a2, 3 a3} ‥‥, above the 3 _an, the formation region The SiO ₂ film is selectively removed by photolithography and dry and wet etching techniques.

After removing the photoresist from the n ⁺ type single crystal SiC substrate 1 and sufficiently washing it, a thin SiO ₂ film having a thickness of 10 to 30 nm is formed on the surface of the n ⁻ type epi layer 2 by low pressure chemical vapor deposition (LPCVD). This is deposited and used as a through SiO ₂ film (not shown) for suppressing the ion implantation range. At this time, a thin through SiO ₂ film is similarly formed on the back surface of the n ⁺ -type single crystal SiC substrate 1.

When the ion implantation mask 11 is completed, as shown in FIG. 2 (b), n ^- the Al ⁺ ions on the type epitaxial layer 2 surface by injecting multistage ion, p-type electric field relaxation region _{3 a1, 3 a2, 3 a3} ‥ ... 3 _an precursor regions 11 _a1 , 11 _a2 , 11 _a3 ... 11 _an are formed. An example of ion implantation conditions for the p-type field relaxation regions 3 _a1 , 3 _a2 , 3 _a3, ..., 3 _an is as follows.

Substrate temperature 700 ° C
Acceleration energy / Dose
First stage 300 keV / 8.3 × 10 ¹⁵ / cm ²
Second stage 190 keV / 3.2 × 10 ¹⁵ / cm ²
Third stage 150 keV / 2.1 × 10 ¹⁵ / cm ²
4th stage 100 keV / 1.9 × 10 ¹⁵ / cm ²
5th stage 60 keV / 1.7 × 10 ¹⁵ / cm ²
6th stage 30 keV / 9.4 × 10 ¹⁴ / cm ²
When the above ion implantation is performed at 700 ° C., a through SiO ₂ film is also formed on the back surface of the n ⁺ -type single crystal SiC substrate 1. This film serves as a protective film to prevent the metal present on the heated platen (or susceptor) surface from directly contacting the n ⁺ -type single crystal SiC substrate 1 and contaminating it or causing a solid-phase reaction. Can do. Even when the platen itself is not a metal, the metal adhering to the platen as a contaminant causes contamination and a solid-phase reaction. In the prior art, due to such contamination and solid-phase reaction, the contact resistance of the backside low-temperature contact formed later is increased. However, in the first embodiment, a through SiO ₂ film as a protective film is formed on the back surface, and then high temperature ion implantation is performed on the surface of the n ⁻ -type epi layer 2 to remove this factor, and contact induced therefrom. It solves the problem of high resistance.

In this example, a through-SiO ₂ film automatically formed on the back surface of the substrate is used as a protective film for suppressing the solid-phase reaction, but after forming a dedicated protective film on the back surface in a separate process, Ion implantation may be performed. In this case, it is not necessary to be a SiO ₂ film, and a film made of another material such as Si ₃ N ₄ or polycrystalline silicon may be used.

(C) p-type electric field relaxation regions 3 _a1 , 3 _a2 , 3 _a3 ... When 3 _an ion implantation is completed, the substrate is immersed in a BHF solution (buffered hydrofluoric acid solution) and all SiO _{The two} films, that is, the mask film and the through SiO ₂ film are removed. Subsequently, after the substrate is sufficiently cleaned and dried, activation annealing is performed to activate the precursor regions 11 _a1 , 11 _a2 , 11 _a3 ... 11 _an as shown in FIG. The p-type electric field relaxation regions 3 _a1 , 3 _a2 , 3 _a3 ... 3 _an are formed.

This activation annealing is placed on a high-purity carbon susceptor with the substrate surface facing up, that is, the back surface of the n ⁺ -type single crystal SiC substrate 1 is in contact with the susceptor, and high purity such as argon (Ar), for example. It is carried out by performing a rapid heat treatment at a temperature of 1600 ° C. or higher in an inert gas atmosphere or a high purity inert gas atmosphere containing a slight amount of silane.

(D) After the activation of the p-type electric field relaxation regions 3 _a1 , 3 _a2 , 3 _a3 ..., 3 _an , the substrate is thoroughly cleaned and dried, and then is exposed to 1160 ° C. on both sides of the substrate in an oxygen atmosphere. Then, the thermal oxide film (SiO ₂ ) is immediately removed with a BHF solution. This thermal oxidation is preferably performed so that a 10 to ₂₀ nm SiO ₂ film grows on the substrate surface. By this thermal oxidation, a SiO ₂ film that is about an order of magnitude thicker than the front surface grows on the back surface. This is because, as described above, the back surface that is the (0001) _C plane has an oxidation rate that is one order of magnitude higher than the (0001) _Si surface of the front surface.

The purpose of the growth / removal of the thermal oxide film is to remove the crystal irregular layer and the contaminated layer present on the surface layers on the front and back surfaces of the substrate by thermal oxidation. In particular, a crystal irregular layer is formed on the back surface of the n ⁺ -type single crystal SiC substrate 1 by the cutting process in the step (a), and a part of the crystal irregularity is broken and even amorphous. The first thermal oxidation has an effect of removing a portion where these crystal structures are lost from the base and exposing a crystal plane with high conductivity and high quality, thereby promoting low resistance of the low temperature contact.

  Subsequently, the substrate is sufficiently cleaned again, and then thermally oxidized (second thermal oxidation) at 1160 ° C. in a dry oxygen atmosphere, as shown in FIG. An oxide film 12 is grown, and a thick CVD oxide film 13 having a thickness of, for example, 600 nm, for example, is deposited thereon by means of CVD or the like, thereby forming a two-layer structure comprising the thermal oxide film 12 and the CVD oxide film 13. A field insulating film 5 is formed.

This second thermal oxidation has the effect of removing the irregular layer on the back surface of the substrate in the same manner as the first thermal oxidation, and the back surface ohmic electrode formation described later is applied to the back surface of the high conductivity and high quality exposed by the first thermal oxidation. In the meantime, by covering with the thermal oxide film 14, it plays the role of storing without deteriorating. As a result, the present invention can further reduce the ρ _{BC of the} back surface low-temperature contact as compared with the prior art.

  (E) Next, the opening 6 is opened in the field insulating film 5 by using the photolithography and dry and wet etching methods used in the manufacturing process of the ion implantation mask 11 described above. At this time, the thermal oxide film 14 on the back surface of the substrate is not lost.

  The procedure will be described. A photoresist mask having an opening pattern is formed on the substrate surface by photolithography, and dry etching is performed by RIE or the like using the photoresist mask. Shortly before the field insulating film 5 penetrates, dry etching is finished on the field insulating film 5, and a resist material is applied to the back surface of the substrate to protect the thermal oxide film 14 on the back surface. A substrate whose back surface is protected by a resist material is immersed in a BHF solution, and the opening 6 is penetrated by wet etching.

  When the opening 6 has penetrated through wet etching, the substrate is sufficiently rinsed and dried, and then the substrate is mounted on a vacuum deposition apparatus or a sputtering apparatus, and a desired Schottky electrode material is formed on the entire surface of the substrate. If the Schottky electrode material is a material that is easily oxidized or dissolved with pure water or a photoresist stripping solution such as Ti or Al, a conductive film for preventing reaction, for example, , Pt may be continuously formed in a thickness range of 50 nm to 150 nm. When the substrate after film formation is taken out from the film formation apparatus, the substrate is immersed in a photoresist stripping solution while applying ultrasonic vibrations, the front and back photoresists are removed cleanly, rinsed thoroughly with ultrapure water, and dried. As a result, the Schottky electrode 7 can be disposed in a self-aligned manner at the bottom of the opening 6 as shown in FIG.

  (F) Subsequently, a thick surface wiring material is deposited on the entire surface of the substrate using means such as DC magnetron sputtering, and then the wiring material is patterned using a well-known photolithography and dry etching method such as RIE. Thus, the surface wiring 8 as shown in FIG. As the surface wiring material, for example, a laminated film in which 50 nm thick Ti and 2 μm thick Al are continuously deposited can be used.

  (G) Next, after applying a protective photoresist on the surface of the substrate, the thermal oxide film 14 covering the back surface of the substrate is removed with a BHF solution. Here, it should be emphasized that the exposed back surface of the substrate is a crystal plane of high quality, high impurity concentration, and high cleanliness formed in the above-described step (d).

Then, after rinsing the substrate with the high-quality, high impurity concentration, high-cleanness exposed back surface with ultrapure water and drying it immediately, use film forming means such as electron beam evaporation and DC sputtering on the entire back surface of the substrate. The materials for the predetermined ohmic electrode 9 and the back surface wiring 10 described above are deposited in a desired thickness. In this way, the ohmic electrode 9 formed without placing a gap on the high-quality SiC back surface becomes a single-crystal electrode film that inherits the crystal periodicity of SiC from the substrate. The interface between the back surface of the n ⁺ -type single crystal SiC substrate 1 and the ohmic electrode 9 is extremely steep.

  When the deposition is completed, the substrate is immersed in a dedicated photoresist stripper solution, and the protective photoresist applied to the substrate surface is completely removed. When the substrate is sufficiently cleaned, rinsed thoroughly with ultrapure water and then dried, the final structure of the high power Schottky diode shown in FIG. 1 is obtained.

Based on the first embodiment of the present invention and the prior art, a large number of vertical Schottky diodes having a Schottky electrode area of about 1 × 1 mm ² are manufactured, the contact resistance value ρ _BC on the back surface, and the defect rate of the semiconductor device Was measured. As a result, the contact resistance value ρ _BC of the prior art was 5.4 × 10 ⁻⁴ Ωcm ² on average. In contrast, all the contact resistance values ρ _BC of the first embodiment were 10 ⁻⁶ Ωcm ² , and the average value was 4.3 × 10 ⁻⁶ Ωcm ² . The first embodiment has succeeded in obtaining a contact resistance value ρ _BC of about 1/100 of the prior art. As is apparent from this result, the vertical semiconductor device according to the first embodiment can solve the problem that the sufficiently low-resistance low-temperature contact of the prior art cannot be obtained.

  On the other hand, the defect rate is 30% or less in the first embodiment and 60% or more in the conventional technique. From this result, it can be seen that the defect rate of the first embodiment is greatly improved as compared with the prior art. In other words, it can be said that the first embodiment solves the problem that the process related to the back surface low temperature contact of the prior art increases the device defect rate in the front side device element. When failure analysis of defective products was performed, many of the defects were caused by imperfections inherent to the crystal substrate used, such as micropipes. Excluding this, it became clear that the actual defect rate of the vertical Schottky diode fabricated based on the first embodiment was remarkably low, 10% or less.

  As described above, according to the first embodiment, the following effects can be obtained.

  The Schottky diode has a non-heat-treatable ohmic electrode 9 in contact with the back surface of the substrate, which is formed without being subjected to a heat treatment exceeding 450 ° C. until the Schottky diode is completed. The substrate is in contact with the back surface of the substrate that does not include a resistance increasing layer that causes a contact resistance increase, which is formed in the manufacturing process of the diode. Thereby, the contact resistance on the back surface of the substrate can be reduced.

When the n-type impurity concentration on the back surface of the substrate is 1 × 10 ¹⁹ / cm ³ or more and less than 1 × 10 ²¹ / cm ³ , the contact resistance can be further reduced.

  The non-heat-treatable ohmic electrode 9 is a hetero-epi electrode film that inherits the crystal periodicity of the SiC substrate on the back surface, so that the contact resistance between the ohmic electrode 9 and the SiC substrate can be reduced.

  The interface between the non-heat-treatable ohmic electrode 9 and the silicon carbide substrate 1 is substantially free of a reaction layer produced by the reaction between the non-heat-treatable ohmic electrode and the silicon carbide substrate, or the thickness is less than 5 nm. Exists only in This eliminates the reaction layer that causes an increase in resistance, thereby reducing the contact resistance.

  The non-heat treatment type ohmic electrode 9 is made of a conductive material having a work function of 4.5 eV or less, so that the back contact resistance can be further reduced.

  The non-heat-treatable ohmic electrode is made of a single layer film of any one of Al, Ti, Zr, Nb, Ta, Mg, and V, or a conductive material that can be formed at room temperature by using two or more alloy films or composite films. Can be provided.

  The main electrode element group includes at least one of a Schottky electrode and an ohmic electrode through which current flows between the silicon carbide substrate 1 and the non-heat-treatable ohmic electrode 9. Thereby, the current flowing between the Schottky electrode and the ohmic electrode and the non-heat-treatment type ohmic electrode 9 can be controlled with a low resistance.

  Since the Schottky electrode and the ohmic electrode are non-heat treated electrodes formed without being subjected to heat treatment exceeding 450 ° C. until the completion of the Schottky diode, metal contamination of the electrode accompanying heat treatment can be avoided.

  The back surface of the silicon carbide substrate is covered with a first protective film, and in this state, a main electrode element group constituting the silicon carbide semiconductor device is formed on the surface. The front surface is covered with a second protective film, and in this state, the non-heat treatment type ohmic electrode 9 is formed on the back surface. The non-heat-treatable ohmic electrode 9 is formed without being subjected to a heat treatment exceeding 450 ° C. until the Schottky diode is completed, and the non-heat-treatable ohmic electrode 9 is formed in the manufacturing process and has an increased resistance that increases the contact resistance. It is formed on the back surface not including the layer. Thereby, a low-resistance ohmic contact can be manufactured at a low temperature.

  The step of forming the main electrode element group includes an act of epitaxially growing the epi layer 2 having the surface doped with the first conductivity type impurity. The step of covering the surface with the second protective film is a step of protecting the epi layer 2 with the grinding protective film, and after forming the grinding protective film and before forming the non-heat treatment type ohmic electrode 9 on the back surface. When the epitaxial layer 2 is epitaxially grown, the parasitic epi film adhering to the back surface is removed. Thereby, the non-heat-treatment type ohmic electrode 9 can be formed in a state where the parasitic epi layer on the back surface that causes the increase in resistance is removed.

  The step of covering the back surface of the substrate with the first protective film and the step of covering the surface of the substrate with the second protective film are steps of covering the cleaned and high-quality substrate surface and back surface with the thermal oxide film, respectively. In the step of forming the main electrode element group and the step of forming the non-heat treatment type ohmic electrode 9, the coated thermal oxide film is removed to expose the front and back surfaces of the cleaned and high-quality substrate. And an act of immediately forming an ohmic electrode or a Schottky electrode on the exposed front and back surfaces. As a result, electrodes can be formed on the front and back surfaces of the substrate in a state where there is no crystal irregular layer, contamination layer, or solid phase reaction layer that causes an increase in resistance.

<Second Embodiment>
Depending on the device, it may be difficult to use an extremely low resistance SiC substrate having an impurity concentration of 10 ¹⁹ / cm ³ or more as in the first embodiment. Also, today's ultra-low resistance SiC substrates have many crystal defects such as micropipes, which causes a high device defect rate. For this reason, there is a case where it is desired to use a low resistance substrate having an impurity concentration of 10 ¹⁸ / cm ³ which has been successfully reduced in crystal defects. In the second embodiment, a technology for forming a back surface low-temperature contact for a vertical device suitable for such a case will be described. Here, a description is given using a Schottky diode as an example of a typical vertical device, but this embodiment is not limited to this and can be applied to a vertical device that requires all backside low-temperature contacts.

FIG. 4 is a cross-sectional view showing a principal part of a Schottky diode according to the second embodiment of the present invention. The Schottky diode according to the second embodiment includes an n ⁺ type low-resistance single crystal 4H—SiC substrate (n ⁺ type single crystal) having a first main surface (front surface) and a second main surface (back surface). SiC substrate) 1 ′, a main electrode element group (2, 3 _{a1 to} 3 _an , 5, 7, 8) arranged on the surface side of the n ⁺ type single crystal SiC substrate 1, and an n ⁺ type single crystal SiC substrate 1 has a non-heat-treatment type ohmic electrode (ohmic electrode) 9 in contact with the back surface and a back surface wiring 10 in contact with the ohmic electrode 9.

The n ⁺ -type single crystal SiC substrate 1 ′ is a single crystal SiC substrate having an impurity concentration of less than 1 × 10 ¹⁹ / cm ³ . An n-type single crystal 4H—SiC substrate having this impurity concentration is already commercially available as a high-quality substrate with few crystal defects. Surface of n ⁺ -type single crystal SiC substrate 1 ′ = (0001) An n ⁻ -type epi layer 2 having a thickness of 10 μm and nitrogen added at 5 × 10 ¹⁵ / cm ³ is homoepitaxially grown on the _Si surface.

The difference between the Schottky diode of Figure 1, n ⁺ -type 'at the bottom containing the back surface of, n ⁺ type single crystal SiC substrate 1' single crystal SiC substrate 1 than high concentration n-type impurity is added n ⁺ The type high concentration impurity layer 4 is formed. The impurity concentration of the n ⁺ -type high concentration impurity layer 4 is desirably 2 × 10 ¹⁹ / cm ³ or more and less than 1 × 10 ²¹ / cm ^{3 on the} outermost surface, and more preferably 1 × 10 ²⁰ / cm ³ or more. 5 × 10 ²⁰ / cm ³ or less.

On the back surface of the n ⁺ -type high-concentration impurity layer 4, the resistance increasing layer including the parasitic epi film deposited by the above-described homo-epi growth on the front surface and an irregular layer such as crystal distortion or lattice damage is completely removed. The crystal plane having the same crystallinity as the inside of the substrate is exposed.

The main electrode element group (2, 3 _{a1 to} 3 _an , 5, 7, 8) on the front surface side of the n ⁺ -type single crystal SiC substrate 1 ′, the ohmic electrode 9 on the back surface side, and the back surface wiring 10 are formed in the first embodiment. The description is omitted because it is exactly the same as the form.

  Next, a method for manufacturing the vertical Schottky diode shown in FIG. 4 will be described with reference to cross-sectional process diagrams of FIGS.

(A) First, an n ⁻ type epi layer 2 having a desired thickness (here, about 10 μm) is grown on the surface side of the substrate 1 ′ in the same manner as in the step (a), and a parasitic epi film on the back surface. Then, an alignment mark (not shown) is formed. Of course, the same effects as those described in the process (A) can be obtained in this process.

Next, after sufficiently washing and drying the substrate, both the front and back surfaces of the substrate were thermally oxidized (first thermal oxidation) at 1160 ° C. in an oxygen atmosphere, and immediately after oxidation, the thermal oxide film (SiO ₂ ) was immediately washed with a BHF solution. Remove. This first thermal oxidation is preferably performed so that a 10 to ₂₀ nm SiO ₂ film grows on the substrate surface. By this first thermal oxidation, a SiO ₂ film that is about an order of magnitude thick grows on the back surface, and the crystal irregular layer and the contaminated layer generated on the back surface layer by removing (grinding) the back surface parasitic epi film are removed together with the thermal oxidation. This further promotes lowering the resistance of the back surface low-temperature contact.

(B) Subsequently, p-type field relaxation regions 3 _{a1 to} 3 _an are selectively formed on the surface of the n ⁻ -type epilayer 2 as shown in FIG. For this purpose, an ion implantation mask 11 is formed. Then, the precursor regions 11 _{a1 to} 11 _an of the p-type electric field relaxation regions 3 _{a1 to} 3 _an are formed by ion implantation. Even in this step, the same effect as described in the step (b) can be obtained.

(C) Next, after sufficiently cleaning the front surface and the back surface of the substrate, multi-stage high-temperature ion implantation of P ⁺ (phosphorus) ions is performed through a through SiO ₂ film (not shown) on the back surface of the substrate, and FIG. As described above, the precursor region 12 of the n ⁺ -type high concentration impurity layer 4 is formed on the entire back surface of the substrate. An example of this ion implantation condition is as follows.

Substrate temperature 500 ° C
Acceleration energy / Dose
First stage 250 keV / 3.6 × 10 ¹⁵ / cm ²
Second stage 200 keV / 8.0 × 10 ¹⁴ / cm ²
Third stage 150 keV / 1.5 × 10 ¹⁵ / cm ²
4th stage 100 keV / 8.0 × 10 ¹⁴ / cm ²
5th stage 70 keV / 8.0 × 10 ¹⁴ / cm ²
6th stage 40 keV / 5.3 × 10 ¹⁴ / cm ²
The high temperature ion implantation is performed by bringing the “surface” of the substrate into contact with the heated platen (or susceptor) surface. At this time, since the ion implantation mask 11 with the through SiO ₂ film described in the step (b) remains on the surface of the substrate, this acts as a protective film and the platen (or susceptor) heated on the surface of the substrate 1. It prevents the metal present on the surface from coming into contact with the substrate surface and contaminating it, and preventing the formation of metal silicides and metal carbides by solid phase reaction. In the prior art, these contaminants and reactants adversely affect the device elements on the surface side, which is one of the causes of device characteristic defects. However, in the second embodiment, the cause is eliminated by forming an oxide film as a protective film on the surface of the substrate and then implanting ions into the back surface of the substrate.

In the second embodiment, the ion implantation mask 11 formed on the front surface side is reused as a protective film for suppressing the solid-phase reaction. However, after another dedicated protective film is formed on the surface, ions are formed on the back surface. You may make it inject | pour. In this case, the precursor region 12 of the n ⁺ -type high concentration impurity layer 4 on the back surface is first ion-implanted, and then the precursor regions 11 _{a1 to} 11 _an of the p-type electric field relaxation region are formed. Thus, the process may be changed.

  Of course, as described above, it is needless to say that the reuse of the ion implantation mask 11 is desirable in terms of production technology because the number of manufacturing steps does not increase.

(D) When all the ion implantations on the front and back surfaces are completed, the substrate is immersed in a BHF solution to remove all the SiO ₂ films (mask film and through film) on the front and back surfaces. Subsequently, the substrate is sufficiently cleaned and dried, and then activation annealing is performed, and the precursor regions 11 _{a1 to} 11 _an and 12 are simultaneously activated as shown in FIG. _a1 to _3an and n ⁺ type high concentration impurity layer 4 are formed.

This activation is carried out on a high-purity carbon susceptor so that the surface of the substrate faces upward, that is, the back surface of the substrate is in contact with the susceptor, and a high-purity inert gas atmosphere such as Ar or slightly silane is added. It is carried out by performing a rapid heat treatment at a temperature of 1600 ° C. or higher in a high purity inert gas atmosphere. However, the reached temperature is high and should not exceed 1750 ° C., preferably 1700 ° C. Further, the elapsed time of 1600 ° C. or higher should not exceed 3 minutes, preferably 2 minutes at the maximum. When the temperature and elapsed time exceeding these conditions are taken, SiC sublimation first occurs from the back surface of the substrate, and the n ⁺ type high concentration impurity layer 4 is thinned or roughened (altered), resulting in low resistance. It becomes difficult to obtain a low temperature contact on the back surface. In the second embodiment, a low-temperature contact with low resistance is realized by performing activation in the above-described appropriate temperature and time range.

(E) After the activation of the p-type field relaxation regions 3 _{a1 to} 3 _an and the n ⁺ -type high-concentration impurity layer 4, the substrate is sufficiently cleaned and dried, and then the substrate is raised vertically to the diffusion furnace, 950 Thermal oxidation film 23 of 20 to 100 nm is grown on the back surface of the substrate (n ⁺ type high concentration impurity layer 4) as shown in FIG. At this time, an oxide film slightly grows on the substrate surface = (0001) _Si surface (not shown), but the thickness is extremely thin, about 1/10 of the back surface = (0001) _C surface.

Subsequently, after sequentially depositing a SiO ₂ film 24 having a thickness of ₂₀ to 50 nm and a thermal antioxidant film 25 having a predetermined thickness on both surfaces of the substrate by LPCVD, immediately, the thermal antioxidant film 25 and SiO 2 on the surface side of the substrate are deposited. _{When the two} films 24 are removed by dry etching (RIE, etc.) and wet etching (BHF solution etching, etc.), and the n ^- epi layer 2 is exposed on the surface side of the substrate 1, the structure shown in FIG. Become. It should be noted that the thermal oxidation preventive film 25 on the back surface is preserved even at this point.

The thermal oxidation-preventing film 25 prevents the SiC substrate underneath from being oxidized by thermal oxidation, and has a role of withstanding an etching solution of SiO ₂ such as BHF. A 400 nm thick Si ₃ N ₄ film can be mentioned, but the present invention is not limited to this. For convenience, in the following description, it is assumed that the thermal oxidation-preventing film 25 is a Si ₃ N ₄ film.

The Si ₃ N ₄ film 25 generates a very strong tensile stresses but, SiO ₂ film 24 has a role of this _{the Si} 3 _{N 4} film 25 is to suppress the damage to the surface and the back surface of the substrate, _Si 3 _{N 4} When the film 25 is removed by dry etching (RIE or the like), it has a dual role of protecting the SiC surface from plasma damage.

On the other hand, the thermal oxide film 23 on the back surface is removed by sacrificing oxidation of the low impurity concentration layer and the irregular layer on the extreme surface on the back surface of the substrate generated in the activation process together with the stress relaxation effect of the Si ₃ N ₄ film 25. Plays a function. The irregular layer or the low impurity concentration layer causes the ohmic contact resistance on the back surface to increase. Thus, it can be said that the thermal oxide film 23 greatly contributes to solving the problem of the prior art that the contact resistance on the back surface is not sufficiently lowered.

(F) When the n ⁻ type epi layer 2 is exposed on the surface side of the substrate, the substrate is sufficiently washed and dried, and then thermally oxidized in a dry oxygen atmosphere at 1160 ° C. to grow a thermal oxide film on the substrate surface Let Thereafter, the substrate is immersed in a BHF solution to remove the thermal oxide film on the substrate surface. The thickness of the thermal oxide film is less than 50 nm, preferably 5 to 20 nm.

By this sacrificial oxidation, the surface of the thermal antioxidant film (Si ₃ N ₄ film) 25 on the back surface of the substrate is also slightly oxidized and removed, but most of it remains. This is because the n ⁺ -type high-concentration impurity layer 4 on the back surface of the substrate under the oxidation-resistant Si ₃ N ₄ film 25 is oxidized without being thinned or lost by this sacrificial oxidation. It means that it remains as it is. That is, the thermal oxidation-resistant film (Si ₃ N ₄ film) 25 is formed by forming an n ⁺ -type high concentration impurity layer 4 on the rear surface of the substrate, without causing the loss of the n ⁺ -type high concentration impurity layer 4, the substrate surface It enables sacrificial oxidation. As a result, the contamination and irregular layers that cause device defects are appropriately removed from the substrate surface, which are generated in activation and subsequent processes, without increasing the contact resistance on the back surface, and the defect rate of vertical devices. Can be reduced. This effect is an effect of the embodiment of the present invention that does not exist in the prior art.

After the sacrificial oxidation of the substrate surface is completed, the substrate is sufficiently cleaned. Then, a thermal oxide film having a thickness of about 5 to 20 nm is grown on the entire surface of the substrate 1 by thermal oxidation at 1160 ° C. in a dry oxygen atmosphere, and further, an atmospheric pressure chemical vapor deposition method (APCVD) or the like is formed thereon. A SiO ₂ film thicker (600 nm thick) than the thermal oxide film is deposited by means. Thereby, a field insulating film 5 having a two-layer structure composed of a thermal oxide film and an APCVD-SiO ₂ film is formed as shown in FIG. By this thermal oxidation, the surface of the thermal oxidation preventive film (Si ₃ N ₄ film) 25 on the back surface is also slightly oxidized (not shown), but its thickness is insignificant.

The thermal oxide film under the field insulating film 5 has _an effect of stabilizing the interface between the field insulating film and the SiC surface, increasing the withstand voltage of the p-type electric field relaxation regions 3 _{a1 to} 3 _an and suppressing the variation. . Insufficient withstand voltage or excessive variation is one of device defects, so in the second embodiment of the present invention, the defect rate of the vertical device of the prior art is also high. Can be solved.

(G) Next, a protective photoresist 28 is applied on the field insulating film 5. The thin thermal oxide film (not shown) on the upper surface of the back surface thermal oxidation preventive film (Si ₃ N ₄ film) 25 is removed with a BHF solution, and then the back surface Si ₃ N ₄ film 25 is removed by dry etching, Finally, the SiO ₂ film 24 and the thermal oxide film 23 are removed with a BHF solution. As a result, the n ⁺ -type high concentration impurity layer 4 is exposed on the back surface. Here, the exposed surface of the exposed n ⁺ -type high-concentration impurity layer 4 achieves high quality, high impurity concentration, and high cleanliness by the sacrificial oxidation effect by removing the thermal oxide film 23.

Next, the substrate on which the back surface of the n ⁺ -type high-concentration impurity layer 4 is exposed is thoroughly rinsed with ultrapure water and dried, and then, as shown in FIG. The predetermined ohmic electrode 9 and the back surface wiring 10 described above are deposited by a desired thickness using the film forming means. In this way, the ohmic electrode 9 is formed without placing a gap on the high-quality SiC back surface. The ohmic electrode 9 becomes a single crystalline electrode film that inherits the crystal periodicity of wisdom SiC on the back surface. The interface between the back surface of the substrate and the ohmic electrode 9 is extremely steep.

  (H) When the deposition of the ohmic electrode 9 and the backside wiring 10 is completed, the substrate is immersed in a dedicated photoresist stripper solution, and the protective photoresist 28 on the substrate surface is completely peeled off. Then, the substrate 1 'is sufficiently cleaned, rinsed with ultrapure water, and then dried.

Subsequently, photolithography is performed, and a photoresist pattern 29 for hollowing out the opening 6 on the surface of the field insulating film 5 is formed at a predetermined position. Next, a photoresist 30 is applied to the back surface of the substrate to completely cover and protect the back surface wiring 10. After post-baking the photoresist on the front and back surfaces, wet etching using a BHF solution or the dry etching and wet etching described above are performed to form an opening 6 in the field insulating film 5 and at the bottom of the opening 6 The n ⁻ type epi layer 2 is exposed. This is called “opening etching”.

  When the opening 6 is exposed by opening etching, the substrate is sufficiently rinsed and dried, and then the substrate is mounted on a vacuum deposition apparatus or sputtering apparatus, and a desired Schottky electrode material is formed on the entire surface of the substrate. The structure (a) is obtained. If the Schottky electrode material 21 is a material that is easily oxidized or dissolved with pure water or a photoresist stripping solution, such as Ti or Al, a conductive film for reaction prevention is further formed on this film. For example, Pt may be continuously formed in a thickness range of 50 nm to 150 nm.

  (I) Next, when the substrate is taken out from the film forming apparatus, the substrate is immersed in a photoresist stripping solution while applying ultrasonic vibration, the photoresist on the front and back surfaces is removed cleanly, rinsed thoroughly with ultrapure water, and dried. . As a result, the structure shown in FIG. 7B is obtained in which the Schottky electrode 7 is disposed on the bottom of the opening 6 in a self-aligning manner.

  In the prior art, once the ohmic electrode 9 and the back surface wiring 10 are formed once on the back surface of the substrate, it is practically difficult to sufficiently clean the substrate surface in the subsequent steps. This is because careless cleaning may cause the electrode material to elute into the cleaning solution and contaminate the substrate surface. Therefore, in the prior art, after forming the ohmic electrode 9 on the back surface, members such as an electrode (Schottky electrode or the like) have to be formed on the front surface side without sufficient substrate cleaning. This has been a major cause of the high defect rate of the prior art.

However, in the second embodiment of the present invention, the surface of the n ⁻ -type epitaxial layer 2 exposed by the opening etching is processed substantially equivalent to sacrificial oxidation in the thermal oxidation process of the field insulating film 5 described above. Yes. For this reason, a very homogeneous and clean surface has already been realized at this point in which the irregular layers and contaminants have been completely removed. Moreover, since the back surface is covered with the protective resist during the opening etching, there is no possibility that the ohmic electrode 9 is dissolved into the opening etching solution. The SiC surface exposed to the opening 6 does not suffer from metal contamination. Therefore, in the second embodiment, it is possible to form an extremely clean and high-quality SiC surface Schottky electrode or the like. In this way, the second embodiment removes one factor causing the device failure that the prior art has, and reduces the failure rate.

  (J) Subsequently, a thick surface wiring material is vapor-deposited on the entire surface of the substrate using means such as DC magnetron sputtering, and then the wiring material is patterned using a well-known photolithography and a dry etching method such as RIE. When the surface wiring 8 is formed and the photoresist is peeled off, the final structure shown in FIG. 4 is obtained. As the surface wiring material, for example, a laminated film in which 50 nm thick Ti and 2 μm thick Al are continuously deposited can be used.

A large number of vertical Schottky diodes having a Schottky electrode area of about 1 × 1 mm ² were manufactured based on the second embodiment, and the contact resistance value ρ _BC on the back surface and the defect rate of the semiconductor device were measured. The values ρ _BC were all lower than the first half of 10 ⁻⁶ Ωcm ² and averaged 1.8 × 10 ⁻⁶ Ωcm ² . Compared to the ρ _BC value of the prior art introduced as a comparison in the description of the first embodiment, the second embodiment succeeds in obtaining a ρ _BC of about 1/400. As is apparent from this result, the second embodiment solves the problem of the prior art that a sufficiently low-resistance back surface low-temperature contact cannot be obtained.

In addition, the defect rate of the 1 × 1 mm ² vertical Schottky diode is 10% or less, and it can be seen that the defect rate is drastically improved as compared with the defect rate of 60% of the prior art. In other words, it can be said that the second embodiment solves the problem that the backside low temperature contact related process of the prior art increases the device defect rate in the front side device element.

The defect rate in the second embodiment is improved by 20 points or more compared to 30% in the first embodiment. This is due to the effect that an n-type single crystal 4H—SiC substrate having an impurity concentration of less than 1 × 10 ¹⁹ / cm ³ with few crystal defects can be used.

  As described above, according to the second embodiment of the present invention, the following effects can be obtained.

  A substrate with a relatively high resistance by coating the surface of the substrate with a heat-resistant protective film made of a non-metallic material, and ion-implanting conductive impurities of the same conductivity type as the silicon carbide substrate on the back of the substrate to activate the conductive impurities. Even if is used, a low resistance layer can be formed on the back surface thereof, and the contact resistance can be reduced.

  Using the ion implantation mask formed on the surface of the epi layer 2 as a heat-resistant protective film, ion implantation of conductive impurities of the same conductivity type as the silicon carbide substrate is performed on the back surface. Thereby, processes can be reduced by effectively using the ion implantation mask.

<Third Embodiment>
In the first and second embodiments, in order to fabricate the vertical semiconductor device shown in FIGS. 1 and 4, in both cases, a low-temperature ohmic electrode (low-temperature contact) on the back surface is formed first, and then the surface of the surface is formed. Although the Schottky electrode is formed, the manufacturing method of the present invention is not limited to this order. A vertical semiconductor device having exactly the same structure can be manufactured by forming the Schottky electrode on the front surface side first and the low-temperature ohmic electrode on the back surface side later. In the third embodiment, as an example to prove this, a method of forming a vertical Schottky diode having the configuration of FIG. 4 in an order different from that of the second embodiment is shown in FIG. 8 to FIG. This will be described with reference to the drawings.

(1) Steps (A) to (F) are performed to obtain the structure shown in FIG. 6B, and then photolithography is performed. As shown in FIG. 5 A photoresist pattern 29 for hollowing out the opening 6 is formed at a predetermined position on the surface. Wet etching using a BHF solution or the dry etching and wet etching described above is performed to form an opening 6 in the field insulating film 5 and to expose the n ⁻ type epi layer 2 at the bottom of the opening 6 (opening etching). . At this point, the back Si ₃ N ₄ film 25 is still preserved because it is resistant to the BHF solution.

When the n ⁻ -type epi layer 2 is exposed, the substrate is sufficiently rinsed and dried, and then the substrate is mounted on a vacuum deposition apparatus or a sputtering apparatus, and a desired Schottky electrode material is formed on the entire surface of the substrate. Thereby, the structure of FIG. 8A is obtained. If the Schottky electrode material 21 is a material that is easily oxidized or dissolved with pure water or a photoresist stripping solution, such as Ti or Al, a conductive film for preventing reaction is further formed on this film. For example, Pt may be continuously formed in a thickness range of 50 nm to 150 nm.

  Next, the substrate is taken out from the film formation apparatus, immersed in a photoresist stripping solution while applying ultrasonic vibration, the photoresist on the front and back is removed cleanly, rinsed thoroughly with ultrapure water, and dried. A structure is obtained in which the Schottky electrode 7 is disposed on the bottom in a self-aligning manner.

  (2) Subsequently, a thick surface wiring material is deposited on the entire surface of the substrate using means such as DC magnetron sputtering. Thereafter, the surface wiring 8 is formed by patterning the wiring material using a known etching method such as photolithography and RIE. When the photoresist is peeled off, the structure shown in FIG. As the surface wiring material, for example, a laminated film in which 50 nm thick Ti and 2 μm thick Al are continuously deposited can be used.

(3) When the surface wiring 8 is formed, a photoresist 28 is applied to the substrate surface to protect the surface wiring 8 and the field insulating film 5. Thereafter, the Si ₃ N ₄ film 25 on the back side is removed by dry etching, and finally the SiO ₂ film 24 and the thermal oxide film 23 under the Si ₃ N ₄ film 25 are removed with a BHF solution. As a result, the n ⁺ -type high concentration impurity layer 4 is exposed on the back surface side. Here, the exposed surface of the n ⁺ -type high-concentration impurity layer 4 is a surface that has achieved high quality, high impurity concentration, and high cleanliness by the sacrificial oxidation effect by removing the thermal oxide film 23.

Next, the substrate on which the n ⁺ -type high-concentration impurity layer 4 is exposed is sufficiently rinsed with ultrapure water and dried. Then, as shown in FIG. The predetermined ohmic electrode 9 and the back surface wiring 10 described above are vapor-deposited to a desired thickness. The ohmic electrode 9 becomes a single crystalline electrode film that inherits the crystal periodicity of SiC. The interface between the back surface of the S substrate and the ohmic electrode is extremely steep.

  In the prior art, once the Schottky electrode 7 and the surface wiring 8 are once formed on the back surface of the substrate, it is practically difficult to sufficiently clean the back surface of the substrate in the subsequent steps. This is because careless cleaning may cause the electrode material to elute into the cleaning solution and contaminate the backside of the substrate. Therefore, in the prior art, after the Schottky electrode is formed on the surface, the ohmic electrode has to be formed on the back surface side without sufficient substrate cleaning. This is the cause of the high contact resistance of the backside low temperature ohmic electrode of the prior art.

  However, in the third embodiment, the back surface of the substrate exposed by the etching of the thermal oxide film 23 has a high sacrificial oxidation as described in the steps (A) and (E). The surface has achieved quality, high impurity concentration (outermost surface), and high cleanliness, and the low temperature ohmic electrode 9 is formed on such an ideal surface. In addition, in the etching of the thermal oxide film 23 that exposes the back surface, the front surface side is covered with the protective resist 28, so that the back surface of the substrate is not contaminated by the electrode metal ions on the front surface side. Thus, in the third embodiment, the back surface contact resistance is reduced, and the problem of the prior art that the resistance of the back surface low temperature contact is high is solved.

  (4) Finally, the protective photoresist 28 is removed with a special stripping solution, the substrate is sufficiently washed and dried, and the final structure shown in FIG. 4 is completed.

The vertical semiconductor device manufactured in the third embodiment shows the same performance and defect rate as the second embodiment, and the contact resistance of the low-temperature ohmic electrode 9 on the back surface is 10 ⁻⁶ as in the second embodiment. Ωcm was ^two first half below.

  As described above, the present invention has been described according to the first to third embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the first to third embodiments, application examples of the present invention have been described in detail using vertical Schottky diodes, but the present invention is not limited to vertical Schottky diodes. The present invention is universally applicable to all vertical semiconductor devices having a low-temperature contact on the back side and an ion-implanted impurity region, a Schottky electrode, an ohmic electrode, a field insulating film, etc. on the front side.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.

It is principal part sectional drawing which shows the Schottky diode which concerns on the 1st Embodiment of this invention. FIGS. 2A to 2C are process cross-sectional views showing main manufacturing processes of the Schottky diode of FIG. 3A to 3C are process cross-sectional views showing main manufacturing steps subsequent to FIGS. 2A to 2C. It is principal part sectional drawing which shows the Schottky diode which concerns on the 2nd Embodiment of this invention. 5A to 5C are process cross-sectional views showing the main manufacturing processes of the Schottky diode of FIG. 6A to 6C are process cross-sectional views showing main manufacturing steps subsequent to FIGS. 5A to 5C. 7A and 7B are process cross-sectional views showing the main manufacturing processes of the Schottky diode according to the third embodiment. FIGS. 8A and 8B are process cross-sectional views showing main manufacturing steps following FIGS. 7A and 7B. It is process sectional drawing which shows the main manufacturing processes following FIG. 8 (a) and (b).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon carbide substrate 2 ... N-type epi layer 3a1-3an ... p-type electric field relaxation area | region 5 ... Field insulating film 6 ... Opening part 7 ... Schottky electrode 8 ... Surface wiring 9 ... Non-heat-treatment type ohmic electrode 10 ... Back surface wiring 11a1 -11an ... Precursor region 11 ... Ion implantation mask 12 ... Thermal oxide film 13 ... CVD oxide film 14 ... Thermal oxide film 21 ... Schottky electrode material 23 ... Thermal oxide film 25 ... Thermal antioxidant film 28-30 ... Photoresist

Claims (3)

Forming an epitaxial layer to which an impurity of the same conductivity type as that of the silicon carbide substrate is added on one main surface of the silicon carbide substrate;
Forming an impurity layer of the same conductivity type as the silicon carbide substrate on the other main surface of the silicon carbide substrate;
Forming an ohmic electrode having a heteroepi property on the impurity layer by non-heat treatment after forming the first protective film on the epi layer; and
After forming the ohmic electrode , a step of forming a second protective film on the ohmic electrode and removing the first protective film to form a main electrode element group on the epi layer is provided. A method for manufacturing a silicon carbide semiconductor device, comprising:
The method of manufacturing a silicon carbide semiconductor device, wherein the ohmic electrode having a heteroepi property is formed without being subjected to a heat treatment exceeding 450 ° C. until the silicon carbide semiconductor device is completed. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the ohmic electrode is made of a conductive material having a work function of 4.5 eV or less. 3. The silicon carbide semiconductor according to claim 2, wherein the ohmic electrode is made of a single layer film of any one of Al, Ti, Zr, Nb, Ta, Mg, and V, or two or more alloy films or composite films. Device manufacturing method.

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