WO2017175460A1 - Dispositif à semi-conducteur et dispositif de conversion de puissance - Google Patents

Dispositif à semi-conducteur et dispositif de conversion de puissance Download PDF

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Publication number
WO2017175460A1
WO2017175460A1 PCT/JP2017/003434 JP2017003434W WO2017175460A1 WO 2017175460 A1 WO2017175460 A1 WO 2017175460A1 JP 2017003434 W JP2017003434 W JP 2017003434W WO 2017175460 A1 WO2017175460 A1 WO 2017175460A1
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Prior art keywords
stripe
region
diffusion layer
semiconductor device
protective diffusion
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PCT/JP2017/003434
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English (en)
Japanese (ja)
Inventor
勝俊 菅原
梨菜 田中
裕 福井
亘平 足立
和也 小西
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三菱電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a trench gate type semiconductor device.
  • insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as switching elements for controlling power supply to loads such as motors. Yes.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • a trench gate type semiconductor device in which a gate electrode is embedded in a semiconductor layer.
  • an on-resistance representing the electrical resistance between the main electrodes when the semiconductor device is on is known. Since a trench gate type semiconductor device can have a higher channel width density than an ordinary planar type semiconductor device, an on-resistance per unit area can be reduced.
  • next-generation switching elements silicon carbide (SiC), gallium nitride (GaN) -based materials, MOSFETs and IGBTs using wide band gap semiconductors such as diamond, etc. are attracting attention, and hexagonal systems such as SiC.
  • SiC silicon carbide
  • GaN gallium nitride
  • MOSFETs and IGBTs using wide band gap semiconductors such as diamond, etc. are attracting attention, and hexagonal systems such as SiC.
  • the current path of the trench gate type semiconductor device coincides with the a-axis direction having a high carrier mobility, so that a significant reduction in on-resistance is expected.
  • Patent Document 1 discloses a technique for reducing the electric field applied to the insulating film at the bottom of the trench by spreading a depletion layer from the second conductive type protective diffusion layer provided at the bottom of the trench into the drift layer of the first conductivity type. It is shown.
  • Patent Document 2 For each of the nine cells in a matrix shape partitioned by a lattice-like gate electrode, one central cell is used as a protective contact region where the protective diffusion layer and the source electrode are connected.
  • the depletion layer extending from the protective diffusion layer has a certain spread not only when the high voltage is cut off between the drain and source, but also when the drain and source are conductive. Due to this spreading, the on-current path in the drift layer is narrowed, and a resistance component called a JFET (Junction FET) resistance increases. Especially when the protective diffusion layers are adjacent to each other, the on-current path becomes narrow, which can contribute to an increase in on-resistance.
  • JFET Joint FET
  • the present invention reliably connects a protective diffusion layer and a source electrode in a trench gate type semiconductor device in which gate electrodes are arranged in a stripe pattern, and suppresses a decrease in switching speed.
  • An object of the present invention is to provide a semiconductor device that can be used.
  • a semiconductor device includes a first conductivity type semiconductor layer, a second conductivity type base region provided above the semiconductor layer, a source region provided above the base region, and a base in the semiconductor layer.
  • a gate insulating film provided in a stripe trench formed in a plurality of stripes that reach a position deeper than the region, and a gate having a side surface that is provided in the stripe trench and faces the base region through the gate insulating film
  • a plurality of active stripe regions each including an electrode, a protective diffusion layer of a second conductivity type provided at a lower portion of the stripe trench, and a source electrode connected to the source region and the base region;
  • a source electrode is connected to the protective diffusion layer through an opening provided in the semiconductor layer between adjacent stripe trenches.
  • a plurality of active stripe regions, and a plurality of first active stripe regions including a protective diffusion layer ground region and a first active stripe region not including a protective diffusion layer ground region.
  • the second active stripe region not including the protective diffusion layer ground region is provided between the first active stripe region including the protective diffusion layer ground region. It becomes possible to connect the layer and the source electrode more reliably, and a decrease in switching speed can be suppressed.
  • 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
  • 1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • 1 is an enlarged plan view showing a semiconductor device according to a first embodiment of the present invention;
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • It is sectional drawing which shows the manufacturing process of the semiconductor device concerning Embodiment 1 of this invention.
  • FIG. 1 is a plan view showing the semiconductor device 100 according to the first embodiment.
  • FIG. 2 is a partial cross-sectional view of the semiconductor device 100 according to the first embodiment, and is a partial cross-sectional view taken along line AA in FIG. It is.
  • an n-type MOSFET using silicon carbide will be described as an example.
  • a semiconductor device 100 is a trench gate type MOSFET having gate electrodes 304 arranged in a stripe shape, and has an active stripe region 3 and a protective diffusion layer ground region 4.
  • the gate electrode 304 extends in one direction (the left-right direction in FIG. 1), and a plurality of gate electrodes 304 are arranged in parallel at a predetermined interval.
  • the minimum unit of the section where the on-current path is formed is the active stripe cell 30.
  • the active stripe region 3 is each stripe-shaped region partitioned by the gate electrodes 304 arranged in a stripe shape, and indicates each row arranged in the vertical direction in FIG.
  • one active stripe region 3 is a region (one row) sandwiched between adjacent stripe-shaped gate electrodes 304 and includes gate electrodes 304 on both sides. That is, it is assumed that the gate electrode 304 sandwiched between adjacent active stripe regions 3 is shared by each active stripe region 3.
  • the protective diffusion layer ground region 4 is a region for connecting a source electrode 5 and a protective diffusion layer 306 described later.
  • a region (row) including the protective diffusion layer ground region 4 is referred to as a first active stripe region 3a, and a region (row) not including the protective diffusion layer ground region 4 is a second active stripe region 3a. This is referred to as a stripe region 3b.
  • FIG. 2 is a partial cross-sectional view including both the active stripe region 3 and the protective diffusion layer ground region 4.
  • the semiconductor device 100 includes a SiC substrate 1, an epitaxial layer 2, an ohmic electrode 301a, a source region 302, a base region 303, a gate electrode 304, a gate insulating film 305, a protective diffusion layer 306, an ohmic electrode 401a, And a drain electrode 7.
  • SiC substrate 1 semiconductor substrate
  • epitaxial layer 2 semiconductor layer
  • a drain electrode 7 is formed on the back surface of the SiC substrate 1.
  • a p-type base region 303 is formed on the epitaxial layer 2, and a region of the epitaxial layer 2 excluding the base region 303 becomes an n-type drift layer 2a.
  • An n-type source region 302 is formed in part of the upper portion of the base region 303.
  • a stripe trench 307 that penetrates the source region 302 and the base region 303 and reaches the drift layer 2 a is formed on both sides of the active stripe region 3, and a gate electrode 304 and a gate insulating film 305 are provided in the stripe trench 307. Yes.
  • the gate insulating film 305 is provided on the side surface and the bottom surface of the gate electrode 304, and the side surface of the gate electrode 304 faces the base region 303 and the source region 302 with the gate insulating film 305 interposed therebetween.
  • the film thickness of the gate insulating film 305 at the position corresponding to the bottom surface of the gate electrode 304 may be larger than the film thickness at the position corresponding to the side surface of the gate electrode 304.
  • the gate insulating film 305 shown in FIG. 2 has the same thickness at the side and bottom, only the side actually operates as the gate insulating film, and the bottom does not contribute to the operation as the MOSFET.
  • the electric field tends to concentrate on the bottom of the trench, and the insulating film is easily broken. Therefore, by selectively thickening only the gate insulating film 305 on the bottom surface of the gate electrode 304, the electric field applied to the gate insulating film 305 can be further reduced.
  • a p-type protective diffusion layer 306 is formed on the bottom of the gate electrode 304 (below the stripe trench 307) via the gate insulating film 305.
  • An interlayer insulating film 6 having contact holes 301 and 401 is provided on the gate electrode 304.
  • the source electrode 5 is connected (ohmic contact) to the source region 302 and the base region 303 through the contact hole 301 of the interlayer insulating film 6. More specifically, an ohmic electrode 301a is formed in the contact hole 301, and the source electrode 5 forms an ohmic contact with the source region 302 and the base region 303 via the ohmic electrode 301a.
  • the protective diffusion layer grounding region 4 not only the stripe trenches 307 in which the gate electrodes 304 on both sides are disposed, but also the opening between the base region 303 and the source region 302 not only in the gate electrodes 304 on both sides. A portion 402 is formed. That is, in the protective diffusion layer ground region 4, the stripe trench 307 in which the gate electrodes 304 on both sides are disposed and the opening 402 therebetween are integrated and provided as one opening. In the protective diffusion layer ground region 4, the protective diffusion layer 306 is formed from the bottom of one gate electrode 304 to the bottom of the other gate electrode 304 over the entire lower part of the stripe trench 307 and the opening 402.
  • the source electrode 5 extends from above the epitaxial layer 2 to the bottom of the opening 402 in the protective diffusion layer ground region 4, and the source electrode 5 passes through the contact hole 401 of the interlayer insulating film 6 at the bottom of the opening 402. Connected to the protective diffusion layer 306.
  • an interlayer insulating film 6 is provided in the opening 402 of the protective diffusion layer grounding region 4 so as to cover the upper surface and side surfaces of the gate electrode 304, and the protective diffusion layer grounding region 4 is provided on the interlayer insulating film 6.
  • a contact hole 401 is formed in FIG.
  • An ohmic electrode 401a is formed in the contact hole 401, and the source electrode 5 forms an ohmic contact with the protective diffusion layer 306 via the ohmic electrode 401a.
  • the interlayer insulating film 6 that covers the side surface of the gate electrode 304 is formed integrally with the interlayer insulating film 6 that covers the upper surface of the gate electrode 304, but the upper surface of the interlayer insulating film 6 and the gate electrode 304 that covers the side surface of the gate electrode 304 is formed. It is good also as providing separately with the interlayer insulation film 6 to cover.
  • the thickness of the interlayer insulating film 6 covering the side surface of the gate electrode 304 may be set as appropriate, but the thickness is made larger than that of the gate insulating film 305 in order to reduce the gate-source parasitic capacitance. Is desirable.
  • FIG. 1 is a plan view of the surface of the epitaxial layer 2 of the semiconductor device 100 shown in FIG. 2 in order to improve visibility, and the source electrode 5 and the interlayer insulating film 6 on the epitaxial layer 2 are not shown. It is a plan view.
  • a plurality of gate electrodes 304 are provided in a stripe shape in the left-right direction of FIG. 1, and a region partitioned by adjacent gate electrodes 304 is defined as an active stripe region 3.
  • Each of the gate electrodes 304 is provided in parallel and spaced apart in the short direction of the gate electrode 304 (up and down direction in FIG. 1). Further, it is desirable that the interval between the gate electrodes 304 be constant, that is, the length of the short side of each active stripe region 3 is desirably constant. If active stripe regions 3 having different short sides are mixed, current may concentrate on the active stripe regions 3 having long short sides. Therefore, by concentrating the length of the short side of the active stripe region 3, current concentration in a part of the active stripe regions 3 can be suppressed.
  • a part of the active stripe regions 3 in the active stripe region 3 includes the protective diffusion layer ground region 4.
  • the active stripe region 3 including the protective diffusion layer ground region 4 is changed to the first active stripe region 3.
  • One active stripe region 3a is referred to as an active stripe region 3 that does not include the protective diffusion layer ground region 4 and is referred to as a second active stripe region 3b.
  • the first active stripe region 3a has a plurality of protective diffusion layer ground regions 4 that are spaced apart from each other.
  • a section defined by the two gate electrodes 304 adjacent to the protective diffusion layer ground region 4 becomes the active stripe cell 30.
  • the active stripe cell 30 is a rectangular section whose periphery is partitioned by a gate electrode 304 (including the gate electrode 304 in the protective diffusion layer ground region 4), and an active cell in which an on-current flows according to the potential of the gate electrode 304. It is.
  • FIG. 3 is an enlarged plan view of the semiconductor device 100 according to the present embodiment around the boundary between the active stripe cell 30 and the protective diffusion layer grounding region 4.
  • the gate electrode 304 and the gate insulating film 305 are formed along the short side of the active stripe cell 30 in the protective diffusion layer ground region 4.
  • the gate electrodes 304 formed along the short sides of the active stripe cell 30 connect the gate electrodes 304 formed in adjacent stripe trenches. Therefore, the protective diffusion layer ground region 4 includes a gate electrode 304 formed in the stripe trench 307 (a gate electrode 304 extending in the horizontal direction in FIG. 3) and a gate electrode formed along the short side of the active stripe cell 30.
  • the region is divided by 304 (the gate electrode 304 extending in the vertical direction in FIG. 3).
  • the ON current path is narrowed by the depletion layer extending from the protective diffusion layer 306 except for the vicinity of the short side of the active stripe cell 30. There are only two directions. Therefore, an increase in JFET resistance can be suppressed as compared with the case where the gate electrode 304 is a lattice type. On the other hand, in such a stripe-type cell layout, the channel resistance increases because the channel width density decreases.
  • the on-resistance can be reduced as compared with the lattice-type layout. it can. Specifically, it is desirable that the long side of the active stripe cell 30 is 1.5 or more, more preferably 2.0 or more with respect to the short side.
  • the second active stripe region 3b does not include the protective diffusion layer ground region 4, the entire second active stripe region 3b becomes one active stripe cell 30.
  • the first active stripe region 3 a and the second active stripe region 3 b are alternately arranged in the short side direction of the active stripe region 3.
  • the protective diffusion layer grounding regions 4 are arranged at regular intervals.
  • the protective diffusion layer grounding region 4 is roughly square in shape, but may be any shape such as other polygons, and the length of each side is the short side of the active stripe region 3. It is not necessarily equal to the length. However, in order to make the short side of the active stripe region 3 the same in all the active stripe regions 3, it is desirable that one side of the protective diffusion layer ground region 4 is an integral multiple of the short side of the active stripe region 3.
  • the semiconductor device 100 operates by switching between an on state and an off state according to a voltage applied to the gate electrode 304.
  • a voltage equal to or higher than a threshold voltage for example, a voltage of 20 V
  • a threshold voltage for example, a voltage of 20 V
  • a voltage lower than the threshold voltage for example, a voltage of 0 V
  • a voltage lower than the threshold voltage for example, a voltage of 0 V
  • the semiconductor device 100 switches between the above-described on-state and off-state according to the voltage applied to the gate electrode 304, thereby realizing a switching operation.
  • a parasitic capacitance called a depletion capacitance exists between the protective diffusion layer 306 and the drift layer 2a.
  • the protective diffusion layer 306 provided under the stripe trench 307 is connected to the source electrode 5 through at least one of the protective diffusion layer ground regions 4.
  • a charge / discharge current of parasitic capacitance flows between the protective layer 5 and the protective diffusion layer 306.
  • 4 to 10 are cross-sectional views showing the steps of the method for manufacturing the semiconductor device 100.
  • the material, dimensions, and the like of each component are merely examples, and the present invention is not limited thereto.
  • epitaxial layer 2 (semiconductor layer) is formed on SiC substrate 1.
  • an n-type low-resistance SiC substrate 1 having a 4H polytype was prepared, and an n-type epitaxial layer 2 was epitaxially grown thereon by a chemical vapor deposition (CVD) method.
  • the epitaxial layer 2 has an n-type impurity concentration of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 and a thickness of 5 to 200 ⁇ m.
  • the surface of the SiC substrate 1 is an angle of 4 ° (off angle) with respect to the (0001) plane which is the c-plane of the SiC crystal.
  • a base region 303 and a source region 302 are formed by ion-implanting a predetermined dopant into the surface of the epitaxial layer 2.
  • the base region 303 is formed by ion implantation of aluminum (Al) which is a p-type impurity.
  • Al aluminum
  • the depth of Al ion implantation is about 0.5 to 3.0 ⁇ m within a range not exceeding the thickness of the epitaxial layer 2.
  • the impurity concentration of Al to be implanted is set higher than the n-type impurity concentration of the epitaxial layer 2.
  • the p-type impurity concentration of the base region 303 is set to a range of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the region of the epitaxial layer 2 deeper than the Al implantation depth becomes the n-type drift layer 2a.
  • the base region 303 may be formed by p-type epitaxial growth. Even in such a case, the impurity concentration and thickness of the base region 303 are the same as those formed by ion implantation.
  • the source region 302 is formed by ion-implanting nitrogen (N) that is an n-type impurity into part of the surface of the base region 303.
  • the planar pattern of the source region 302 is formed with a pattern corresponding to the layout of the gate electrode 304 formed in a process described later. Specifically, the planar arrangement of the source region 302 is determined so that the source region 302 is disposed on both sides of the gate electrode 304 when the gate electrode 304 is formed.
  • the N ion implantation depth is made shallower than the thickness of the base region 303.
  • the impurity concentration of N to be implanted is not less than the p-type impurity concentration of the base region 303 and not more than 1 ⁇ 10 21 cm ⁇ 3 .
  • a depletion suppression layer (not shown) having an n-type impurity concentration higher than that of the drift layer 2a may be provided below the base region 303.
  • a current path is narrowed by a depletion layer extending from both the base region 303 and the protective diffusion layer 306, and a so-called JFET resistance is generated between them.
  • the depletion suppression layer is provided as described above, since the extension of the depletion layer from the base region 303 can be suppressed when the semiconductor device 100 is turned on, the JFET resistance can be reduced.
  • the depletion suppression layer is formed by ion implantation of nitrogen (N) or phosphorus (P) which are n-type impurities.
  • the depth of the depletion suppressing layer is preferably deeper than the base region 303 and within the range not exceeding the thickness of the epitaxial layer 2, and the thickness is preferably about 0.5 to 3 ⁇ m.
  • the impurity concentration of N to be implanted is preferably higher than the n-type impurity concentration of the epitaxial layer 2 and 1 ⁇ 10 17 cm ⁇ 3 or more.
  • the depletion suppression layer may be formed by n-type epitaxial growth. In such a case, the impurity concentration and thickness of the depletion suppression layer are the same as those formed by ion implantation.
  • the depletion suppression layer may be a planar pattern in which only the central portion of the active stripe cell 30 is removed.
  • a silicon oxide film 8 is deposited on the surface of the epitaxial layer 2 by about 1 to 2 ⁇ m, and an etching mask 9 made of a resist material is formed on the silicon oxide film 8.
  • the etching mask 9 is formed in a pattern opened corresponding to a trench formation region by a photolithography technique. Then, the silicon oxide film 8 is patterned by a reactive ion etching (RIE) process using the etching mask 9 as a mask. Thereby, the pattern of the etching mask 9 is transferred to the silicon oxide film 8.
  • the patterned silicon oxide film 8 becomes an etching mask for the next step.
  • RIE reactive ion etching
  • a stripe trench 307 and an opening 402 that penetrate the source region 302 and the base region 303 are formed in the epitaxial layer 2 by RIE using the patterned silicon oxide film 8 as a mask.
  • the depth of the trench is not less than the depth of the base region 303 and is about 1.0 to 6.0 ⁇ m.
  • the planar pattern of the trench corresponds to the planar pattern in which the gate electrode 304 and the gate insulating film 305 in FIG. 1 are combined. More specifically, a plurality of stripe trenches 307 are provided in a stripe shape so as to define the active stripe region 3, and only the region corresponding to the protective diffusion layer ground region 4 is also formed between adjacent stripe trenches 307.
  • An opening 402 is formed, and the entire protective diffusion layer grounding region 4 is etched.
  • the stripe trench 307 defining the active stripe region 3 and the opening 402 formed in the protective diffusion layer ground region 4 are collectively referred to as a trench.
  • the stripe trench 307 (active stripe region 3) is arranged in parallel to the step flow of the epitaxial layer 2 formed by the off angle of the SiC substrate 1.
  • a portion adjacent to the gate electrode 304 in the active stripe region 3 functions as a MOSFET.
  • an implantation mask 10 having the same pattern as the etching mask 9 is formed by opening a trench portion, and ion implantation using the implantation mask 10 as a mask is performed to form a p-type protective diffusion layer 306 at the bottom of the trench.
  • Al is used as a p-type impurity.
  • the impurity concentration of Al to be implanted is preferably in the range of 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 and the thickness is preferably in the range of 0.1 to 2.0 ⁇ m.
  • the Al impurity concentration of the protective diffusion layer 306 is determined from the electric field applied to the gate insulating film 305 when a working breakdown voltage is applied between the drain and source of the MOSFET.
  • a (patterned) silicon oxide film 8 that is an etching mask for forming a trench may be used instead of the implantation mask 10. Thereby, simplification of the manufacturing process and cost reduction can be achieved.
  • the silicon oxide film 8 is used instead of the implantation mask 10, it is necessary to adjust the thickness and etching conditions of the silicon oxide film 8 so that the silicon oxide film 8 having a sufficient thickness remains after the trench is formed. There is.
  • annealing is performed using a heat treatment apparatus, thereby activating the impurities implanted by the above process.
  • the annealing treatment is performed in an inert gas atmosphere such as argon (Ar) gas or in vacuum under conditions of 1300 to 1900 ° C. and 30 seconds to 1 hour.
  • a polysilicon film 12 is deposited by a low pressure CVD method.
  • the gate insulating film 305 and the gate electrode 304 are formed in the stripe trench 307 by patterning or etching back the silicon oxide film 11 and the polysilicon film 12.
  • the silicon oxide film 11 to be the gate insulating film 305 may be formed by thermally oxidizing the surface of the epitaxial layer 2 or may be formed by being deposited on the epitaxial layer 2.
  • the interlayer insulating film 6 is formed on the entire surface of the epitaxial layer 2 by low pressure CVD, and the gate electrode 304 is covered with the interlayer insulating film 6. Further, by patterning the interlayer insulating film 6, a contact hole 301 reaching the source region 302 and the base region 303 is formed in the active stripe region 3, and a contact hole 401 reaching the protective diffusion layer 306 is formed in the protective diffusion layer ground region 4. Form. Then, ohmic electrodes 301 a and 401 a are formed on the surface of the epitaxial layer 2 exposed at the bottoms of the contact holes 301 and 401.
  • a metal film containing Ni as a main component is formed on the entire surface of the epitaxial layer 2 including the inside of each contact hole, and reacted with silicon carbide by heat treatment at 600 to 1100 ° C.
  • a silicide film to be an ohmic electrode is formed.
  • an electrode material such as an Al alloy is deposited on the epitaxial layer 2 to form the source electrode 5 on the interlayer insulating film 6 and in the contact holes 301 and 401 (not shown).
  • an electrode material such as an Al alloy is deposited on the lower surface of the SiC substrate 1 to form the drain electrode 7 (not shown).
  • FIG. 21 and 22 show a comparative example of the semiconductor device 100 according to the present embodiment.
  • FIG. 21 shows a semiconductor device 200 in which a protective diffusion layer grounding region 4 is provided in a central section of nine sections in a lattice layout in which gate electrodes 304 are arranged in a lattice form as shown in Patent Document 2.
  • FIG. 22 shows a semiconductor device 300 in which the gate electrode 304 is replaced with a stripe layout in the semiconductor device 200 shown in FIG.
  • the active cells divided by the lattice-like gate electrodes 304 are surrounded by the gate electrodes 304 in four directions, they extend from the protective diffusion layer 306 provided at the bottom of each gate electrode 304. Due to the influence of the depletion layer, the on-current path is narrowed from four directions, which may increase the on-resistance. Therefore, when the layout of the gate electrode 304 is changed from the lattice type to the stripe type in order to suppress such an increase in on-resistance, the semiconductor device 300 shown in FIG. 22 is obtained. In the semiconductor device 300, the on-current path is narrowed only in two directions except for the vicinity of the short side of the active stripe cell 30, so that the on-current path can be widened and the on-resistance can be reduced.
  • the semiconductor device 300 shown in FIG. 22 there is a region where the second active stripe regions 3b are arranged without including the protective diffusion layer ground region 4, and the stripe trench 307 between the adjacent second active stripe regions 3b.
  • the stripe trenches 307 in the second, fifth, and eighth rows from the top in FIG. 22 do not contact the protective diffusion layer ground region 4. Therefore, the protective diffusion layer 306 provided below the stripe trenches 307 is not connected to the protective diffusion layer ground region 4.
  • the potential of the protective diffusion layer 306 that is not in contact with the protective diffusion layer ground region 4 becomes floating, and the response speed of the depletion layer is delayed as compared with the other protective diffusion layers 306 during the transient response.
  • the gate insulating film may be destroyed due to an increase in switching loss, characteristic variations in the semiconductor device 300, and eventually current concentration during high-speed operation.
  • the active stripe region 3 includes the first active stripe region 3 a including the protective diffusion layer ground region 4 and the second active stripe region 3 b not including the protective diffusion layer ground region 4. Since the second active stripe regions 3b that do not include the protective diffusion layer ground region 4 are sandwiched between the first active stripe regions 3a that include the protective diffusion layer ground region 4, Thus, all the stripe trenches 307 are connected to the protective diffusion layer ground region 4. As a result, there is no place where the protective diffusion layer 306 provided below the stripe trench 307 is in a floating state, and an increase in switching loss, variation in characteristics within the semiconductor device 300, and further current concentration during high-speed operation, Problems such as destruction can be suppressed.
  • the layout of the gate electrode 304 is striped to widen the on-current path and reduce the on-resistance, and part of the protective diffusion layer 306 is in a floating state. Therefore, problems such as an increase in switching loss, characteristic variations in the semiconductor device 100, and breakdown of the gate insulating film 305 due to current concentration during high-speed operation can be suppressed.
  • the gate electrode 304 has a stripe layout, so that the current path becomes wider compared to the lattice layout, so that the increase in JFET resistance with a rise in temperature becomes moderate.
  • the temperature characteristics of on-resistance can be improved.
  • the source electrode 5 and the protective diffusion layer 306 are connected in the protective diffusion layer ground region 4.
  • an opening may be partially provided between the gate electrodes 304 on both sides in the protective diffusion layer ground region 4, but the protective diffusion layer ground is provided as in the present embodiment.
  • an opening is provided between the gate electrodes 304 on both sides, and the source electrode 5 and the protective diffusion layer 306 are connected within the opening 402, thereby expanding the contact area, and the source electrode 5 and the protective diffusion layer. The contact resistance with 306 can be reduced.
  • the position in the depth direction where the source electrode 5 and the protective diffusion layer 306 are in contact with each other may be appropriately changed, but as in the semiconductor device 100 according to the present embodiment,
  • the source electrode 5 preferably extends to the bottom of the opening 402 deeper than the base region 303 and is connected to the protective diffusion layer 306 at the bottom of the opening 402. .
  • the protective diffusion layer 306 can be formed up to the surface of the epitaxial layer 2 and connected to the source electrode 5.
  • the source electrode 5 having a resistivity lower than that of the diffusion layer 306 is extended to the bottom of the opening 402 and the source electrode 5 and the protective diffusion layer 306 are connected to each other, so that the gap between the protective diffusion layer 306 and the source electrode 5 is reached. Resistance can be reduced and switching loss can be reduced.
  • the interlayer insulating film 6 that covers the side surface of the gate electrode 304 is thicker than the gate insulating film 305 in the opening 402 of the protective diffusion layer ground region 4.
  • the parasitic capacitance between the gate and the source can be reduced, and the switching characteristics (loss, time, etc.) can be improved.
  • FIGS. 11 to 13 are plan views showing modifications of the semiconductor device 100 according to the present embodiment.
  • FIGS. 11 to 13 are plan views showing modifications of the semiconductor device 100 according to the present embodiment.
  • the base region 303 exposed in the contact hole 301 in the active stripe region 3 is divided into a plurality of regions as compared with the semiconductor device 100 according to the present embodiment. The only difference is that it has been changed.
  • the base region 303 exposed in the contact hole 301 has a single rectangular shape corresponding to the shape of the rectangular active stripe cell 30.
  • the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is composed of a plurality of square regions, and has a constant interval. Are provided apart from each other.
  • the reduction in channel width density can be suppressed by reducing the pitch in the short side direction of the active stripe region 3.
  • reducing the distance between the contact hole 301 and the gate electrode 304 may increase the gate-source leakage rate, a certain distance is ensured between the contact hole 301 and the gate electrode 304.
  • reducing the size of the contact hole leads to an increase in contact resistance. Although the channel resistance can be reduced, the contact resistance increases.
  • the contact area between the source region 302 and the source electrode 5 can be increased, and the contact resistance can be reduced.
  • the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is divided into a plurality of regions, and the source region 302 is interposed between the plurality of divided base regions 303. Is exposed. Therefore, compared with the semiconductor device 100 shown in FIG. 1, the area of the source region 302 in the contact hole 301 can be increased, and the contact resistance between the source region 302 and the source electrode 5 can be reduced.
  • the occupied area of the base region 303 in the contact hole 301 is desirably 20% or more.
  • the base region 303 exposed on the surface of the epitaxial layer 2 in the contact hole 301 is composed of a plurality of rectangular regions and is provided at regular intervals. Each of the base regions 303 exposed on the surface extends from one of the adjacent stripe trenches 307 to the other in the short side direction of the active stripe region 3.
  • each of the base regions 303 exposed on the surface is uniformly provided in the short side direction of the active stripe region 3 between the stripe trenches 307. Even when the position of the contact hole 301 is shifted in the side direction, the area of the source region 302 in the contact hole 301 does not change. Therefore, the pitch in the short side direction of the active stripe region 3 can be further reduced, and the on-resistance can be reduced.
  • the composition ratio of the first active stripe region 3a and the second active stripe region 3b is 2: 1. More specifically, in the short side direction of the active stripe region 3, two first active stripe regions 3a and two second active stripe regions 3b are arranged as a minimum unit, and this is repeatedly arranged. It is out. Further, the width of the protective diffusion layer ground region 4 in the short side direction of the active stripe region 3 is twice the short side of the active stripe region 3, and the two adjacent first active stripe regions 3a are adjacent to each other. A common protective diffusion layer ground region 4 is provided.
  • the configuration ratio of the first active stripe region 3a and the second active stripe region 3b is not limited to 2: 1 and can be set as appropriate.
  • the width of the protective diffusion layer ground region 4 in the short side direction of the active stripe region 3 corresponds to the composition ratio of the first active stripe region 3a and the second active stripe region 3b. If the width is an integral multiple of the width of the short side, the short sides of the active stripe region 3 can be arranged equally.
  • the first active stripe region 3a including the protective diffusion layer ground region 4 and the second active stripe region 3b not including the protective diffusion layer ground region 4 are alternately arranged.
  • the arrangement of the first active stripe region 3a and the second active stripe region 3b is not limited to this.
  • one second active stripe region 3b may be provided for each of the plurality of first active stripe regions 3a.
  • the protective diffusion layer 306 provided below the stripe trench 307 between the second active stripe regions 3b is floated. There is a fear. Therefore, as shown in FIG.
  • the first active stripe region 3a is adjacent to both sides of each second active stripe region 3b, and the second active stripe region 3b is sandwiched between the first active stripe regions 3a. Arrange so that. Thereby, it is possible to prevent a part of the protective diffusion layer 306 from floating.
  • the second active stripe region 3b that does not include the protective diffusion layer ground region 4 is disposed so as to be sandwiched between the first active stripe region 3a that includes the protective diffusion layer ground region 4, Some of the protective diffusion layers 306 can be prevented from floating, and deterioration of switching characteristics can be suppressed.
  • FIG. FIG. 14 is a plan view showing the semiconductor device 110 according to the second embodiment of the present invention.
  • the same reference numerals as those in FIG. 1 denote the same or corresponding configurations.
  • the present embodiment is different from the first embodiment in that an intersection trench 308 that intersects with the stripe trench 307 is provided.
  • the first active stripe region 3a including the protective diffusion layer ground region 4 is disposed adjacent to both sides of the second active stripe region 3b not including the protective diffusion layer ground region 4.
  • the second active stripe regions 3b are adjacent to each other, and the protective diffusion layer 306 provided below the stripe trench 307 between the second active stripe regions 3b is prevented from floating.
  • the second active stripe region can be obtained by providing the intersecting trench 308 intersecting the stripe trench 307.
  • a protective diffusion layer 306 provided below the stripe trench 307 between 3 b can be connected to the source electrode 5.
  • an intersection trench 308 that intersects with the stripe trench 307 in a direction perpendicular to the longitudinal direction of the stripe trench 307 is provided.
  • a gate electrode 304 and a gate insulating film 305 are disposed in the intersection trench, and a protective diffusion layer 306 is also provided under the intersection trench.
  • the intersecting trenches are respectively provided between two adjacent protective diffusion layer ground regions 4 and extend in the short side direction of the active stripe region 3. More specifically, the intersecting trench 308 is provided between the adjacent protective diffusion layer ground regions 4 so as to connect the two adjacent protective diffusion layer ground regions 4 in the short side direction of the active stripe region 3. Between the protective diffusion layer ground regions 4 to be crossed, the stripes 307 perpendicularly intersect with the second active stripe regions 3b.
  • the protective diffusion layer 306 provided below the stripe trench 307 sandwiched between the second active stripe regions 3b is floating, but in the semiconductor device 110 according to the present embodiment, The protective diffusion layer 306 below the stripe trench sandwiched between the second active stripe regions 3b is also connected to the protective diffusion layer ground region 4 via the protective diffusion layer 306 provided below the intersecting trench 308. Become. Accordingly, since the protective diffusion layer 306 can be connected to the source electrode 5 more reliably, an increase in switching loss, a variation in characteristics within the semiconductor device 300, and a breakdown of the gate insulating film due to current concentration during high-speed operation can be prevented. Can be suppressed.
  • the semiconductor device 110 by providing the intersecting trench 308 in which the gate electrode 304 is provided, a channel is also formed on the side surface of the intersecting trench 308, so that the channel width density is improved. Thus, the on-resistance can be reduced.
  • the intersection trench 308 by providing the intersection trench 308, the length of the long side of the active stripe cell 30 is narrowed, and the JFET resistance due to the depletion layer extending from the protective diffusion layer 306 may increase.
  • the active stripe cells 30 are set to have at least a stripe shape (rectangular shape), preferably the length of the long side of the active stripe cell 30 is 1.5 times the length of the short side, more preferably 2. It is set to be 0 times or more.
  • the semiconductor device 200 shown in FIG. 21 has a lattice-type gate electrode arrangement, if at least one protective diffusion layer ground region 4 is provided, all the protective diffusion layers 306 provided below the gate electrode 304 are provided. Inevitably is connected to the source electrode 5, but the depletion layer from the protective diffusion layer 306 extends from the four directions in each active cell, increasing the JFET resistance and increasing the on-resistance.
  • the gate electrode 304 is changed to a striped layout as it is in the structure of the semiconductor device 200 of FIG. As described above, becomes floating and causes deterioration of switching characteristics.
  • a part of the protective diffusion layers 306 is formed by connecting the protective diffusion layers 306 provided below the stripe trenches 307 via the protective diffusion layers 306 provided below the intersection trenches 308.
  • intersection trench 308 is not limited to the structure in which the second active stripe regions 3b are adjacent to each other as in the present embodiment.
  • the first active stripe region 3b is provided.
  • the intersection trench 308 may be provided.
  • FIG. 15 shows a semiconductor device 111 according to a modification of the present embodiment.
  • the first active stripe region 3a, the second active stripe region 3b, and the active stripe region 3 are alternately arranged in the short side direction, and the second active stripe region 3b Are provided with intersecting trenches 308 at regular intervals in the long side direction of the active stripe region 3.
  • an intersection trench 308 is provided for each protective diffusion layer ground region 4, and one end of each intersection trench 308 is connected to the protection diffusion layer ground region 4.
  • the channel width density is improved and the on-resistance is increased. Can be reduced.
  • the deterioration of the switching characteristics can be suppressed by connecting the stripe trench 307 that can be floated by the intersection trench 308 and the protective diffusion layer grounding region 4.
  • the cross trench 308 since the cross trench 308 is provided, a channel region can be formed on the side surface of the cross trench 308, so that the channel width density can be improved and the on-resistance can be reduced.
  • FIG. 16 is a plan view showing a semiconductor device 120 according to the third embodiment of the present invention.
  • the same reference numerals as those in FIG. 1 denote the same or corresponding components.
  • the present embodiment is different from the first embodiment in that the protective diffusion layer ground region 4 is provided in all the active stripe regions 3.
  • each of the plurality of active stripe regions 3 is provided with a protective diffusion layer ground region 4, that is, only the first active stripe region 3 a including the protective diffusion layer ground region 4.
  • the protective diffusion layer ground region 4 of each active stripe region 3 is continuously formed in the short side direction of the active stripe region 3.
  • the protective diffusion layer ground region 4 in the present embodiment is formed by one stripe-shaped opening extending in the short side direction (vertical direction in FIG. 16) of the active stripe region 3.
  • a plurality of stripe-shaped protective diffusion layer ground regions 4 are provided at regular intervals in the longitudinal direction of the active stripe region 3.
  • a gate electrode 304 is provided on both side surfaces of a striped opening (protective diffusion layer grounding region 4) extending in the vertical direction in FIG. 16 (not shown). Therefore, the plurality of gate electrodes 304 provided in the stripe trenches 307 extending in the left-right direction in FIG. 16 and defining the active stripe cell 30 are connected to each other by the gate electrodes 304 provided in the protective diffusion layer ground region 4. Will be. Accordingly, the protective diffusion layer 306 provided below the stripe trench 307 (gate electrode 304) is connected to each other by the protective diffusion layer 306 provided below the opening 402 in the protective diffusion layer ground region 4, and The protective diffusion layer ground region 4 is connected to the source electrode 5.
  • the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, it is prevented that a part of the protective diffusion layer 306 is floated and the switching characteristics are deteriorated. be able to.
  • the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, but the ratio of the protective diffusion layer ground region 4 is relatively increased as compared with the first embodiment. There is a risk. Since the on-current path is not formed in the protective diffusion layer ground region 4, if the protective diffusion layer ground region 4 is made dense, the on-current path may be narrowed and the on-resistance may be increased. Therefore, it is desirable that the interval between the protective diffusion layer grounding regions 4 is larger than that in the first embodiment, and the exclusive area of the protective diffusion layer grounding region 4 is set to a ratio that does not hinder the on-resistance. It is desirable to do.
  • FIG. 17 shows a plan view of a semiconductor device 121 according to a modification of the present embodiment.
  • the protective diffusion layer ground region 4 is provided in each active stripe region 3, and the protective diffusion layer ground region 4 included in each active stripe region 3 is provided in order to reduce the gate resistance. They are provided at regular intervals.
  • a gate electrode 304 is disposed along each side of the square-shaped protective diffusion layer grounding region 4. Thereby, since the gate electrode 304 is not divided by the protective diffusion layer grounding region 4, an increase in gate resistance can be suppressed.
  • the protective diffusion layer ground region 4 of each adjacent active stripe region 3 is formed continuously and formed by one stripe-shaped opening, but the protective diffusion layer ground region 4 is formed. May be divided into a plurality of sections.
  • FIG. 18 shows a modification in which the protective diffusion layer ground region 4 is divided into a plurality of sections in the semiconductor device 120 according to the present embodiment.
  • the protective diffusion layer grounding region 4 is composed of a plurality of spaced square sections, and a plurality of columns in which the protective diffusion layer grounding regions 4 are arranged in a plurality of spaced apart are provided. .
  • Active stripe cells 30 are formed between columns of the protective diffusion layer ground region 4.
  • square active cells 31 are provided between a plurality of sections constituting the protective diffusion layer grounding region 4.
  • the side in the short side direction of the active stripe region 3 in the active cell 31 is composed of two intersecting trenches 308 intersecting with the stripe trench 307, and a gate electrode 304 and a gate insulating film 305 are arranged inside the intersecting trench 308.
  • a protective diffusion layer 306 is provided below the intersection trench 308.
  • a trench extending in the longitudinal direction of the active stripe region 3 is provided at the boundary between the active cell 31 and the protective diffusion layer ground region 4, and a gate electrode 304 is provided inside the trench.
  • the on-current path is increased and the channel width density is also increased. As a result, the on-resistance can be reduced.
  • the active stripe cell 30 is also referred to as a first active cell, and the active cell 31 is also referred to as a second active cell. If an attempt is made to configure only a single-shaped active cell and a protective diffusion layer ground region, it may be difficult to sufficiently adjust the exclusive ratio of active cells in the entire semiconductor device. Therefore, in the semiconductor device 122 shown in FIG. 18, the stripe-shaped first active cell (30) and the square-shaped second active cell (31) having a different planar shape from the first active cell are provided. Since the space in the planar direction can be fully utilized and the area that can be utilized as the on-current path can be increased, the on-resistance can be reduced.
  • the boundary between the protective diffusion layer ground region 4 and the active cell 31 is a half cycle of the pitch in the short side direction of the active stripe cell 30 with respect to the boundary between the active stripe cells 30.
  • the protective diffusion layer grounding region 4 is provided so as to be shifted by the amount.
  • Each active stripe region 3 includes a part (half) of the protective diffusion layer ground region 4.
  • the “active stripe region 3 includes the protective diffusion layer ground region 4.
  • the configuration of “included” includes the active stripe region 3 including a part of the protective diffusion layer ground region 4 as described above.
  • the gate electrode 304 since the gate electrode 304 is integrally formed without being divided, an increase in gate resistance can be suppressed.
  • the protective diffusion layer grounding region 4 has a square shape, but is not limited thereto.
  • FIG. 19 shows a semiconductor device 123 in which the planar shape of the protective diffusion layer ground region 4 is rectangular in the semiconductor device 122 shown in FIG. As shown in FIG. 19, the protective diffusion layer grounding region 4 may have a rectangular shape.
  • the protective diffusion layer ground region 4 has the same shape as that of the active stripe cell 30, and accordingly, the active cell 31 provided between the protective diffusion layer ground regions 4 also has the same rectangular shape as that of the active stripe cell 30. It becomes a shape.
  • the protective diffusion layer grounding region 4 and the active stripe cell 30 are not limited to a rectangular shape, and may be configured in a polygonal shape such as a hexagon.
  • 20 shows a semiconductor device 124 in which the planar shape of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 in the semiconductor device 122 shown in FIG. 18 is hexagonal.
  • the protective diffusion layer ground region 4 and the active cell 31 are formed in a regular hexagonal shape, and the active stripe cell 30 has a shape in which the regular hexagonal shape is extended in one direction along the stripe trench 307. Further, as shown in FIG.
  • the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 are separated by an intersection trench 308 that intersects with the stripe trench 307. Further, in FIG. 20, the plane orientation of the side wall of the epitaxial layer 2 formed by the intersecting trench 308 having an obtuse angle with respect to the stripe trench 307 is constituted by a plane equivalent to the (10-10) plane. As a result, the influence of the off-angle can be reduced and the reduction in gate breakdown voltage can be suppressed.
  • the ratio of the long side to the short side of the active stripe cell 30 is the distance between the long sides of the active stripe cell 30. It can be considered and calculated as a short side. Even if the shape of the active stripe cell 30 changes, the ratio of the long side to the short side is preferably 1.5 or more, more preferably 2.0 or more.
  • the cross trench 308 provided in the second embodiment is not necessarily orthogonal to the stripe trench 307, and the planar shape of the protective diffusion layer ground region 4, the active stripe cell 30, and the active cell 31 is the same. Accordingly, it may be provided.
  • the protective diffusion layer ground region 4 is provided in each of the active stripe regions 3, it is possible to suppress a part of the protective diffusion layer 306 from floating and to suppress deterioration of switching characteristics and the like. be able to.
  • FIG. 23 is a plan view showing a semiconductor device 130 according to the fourth embodiment of the present invention.
  • the same reference numerals as those in FIG. 1 denote the same or corresponding configurations.
  • the present embodiment is different from the first embodiment in that the apex portion of the active cell in plan view has a curvature.
  • the first active cell (active stripe cell 30) and the second active cell (active cell 31) are collectively referred to as an active cell.
  • the trench surrounds the apex portion of the active stripe cell 30 from two directions.
  • the apex portion of the active stripe cell 30 transitions to the on state with a lower gate voltage than the side wall portion.
  • the threshold voltage of the apex portion is lower than that of the side wall portion. Lowering the threshold voltage at the apex is not preferable because it causes phenomena such as lowering the threshold voltage of the entire MOSFET and increasing switching loss.
  • trenches and gate electrodes 304 corresponding to the apex portions of the active stripe cells 30 are formed in an arc shape, and the outline of the active stripe cells 30 is expressed as apexes.
  • the concentration of the gate electric field in the channel region at the apex portion can be relaxed and the applied gate electric field can be weakened. Thereby, the fall of the threshold voltage in a vertex part can be suppressed.
  • the radius of curvature of the apex portion is desirably 10% or more and 50% or less of the length Lm on the short side of the active stripe cell 30. This is because when the curvature is small, a sufficient double gate electric field reduction effect cannot be obtained, and when the curvature is large, the tip of the active stripe cell 30 is sharp, and the gate electric field is applied to this portion twice. It is.
  • Embodiments 2 and 3 can be used in combination with Embodiments 2 and 3 as well as Embodiment 1.
  • An example in combination with Embodiment Mode 2 is shown in FIG. In this case, it is necessary to change the shape of the both sides of the intersection trench 308 to have a similar curvature.
  • the active stripe cell 30 but also the active cell 31 may be provided with a curvature at the apex portion.
  • not only a rounded rectangle but a rounded polygon may be used.
  • the gate electric field applied to the apex portion is reduced, and the phenomenon that the apex portion becomes smaller in threshold than the side wall portion is reduced. can do.
  • FIG. FIG. 25 is a plan view showing a semiconductor device 140 according to the fifth embodiment of the present invention.
  • parts different from those of the first embodiment will be described, and description of the same or corresponding parts will be omitted.
  • 25 the same reference numerals as those in FIG. 1 denote the same or corresponding configurations.
  • the present embodiment is different from the first embodiment in that a part of the stripe trench 307 is replaced with a dummy trench 309.
  • some stripe trenches 307 are replaced with dummy trenches 309.
  • the dummy trench 309 is separated from the other stripe trenches 307, and the gate electrode (second gate electrode) formed in the dummy trench 309 via the gate insulating film is a gate electrode in the other stripe trench 307.
  • the channel region that is not connected to 304 and adjacent to the second gate electrode does not operate.
  • the dummy trench 309 has the same depth as the stripe trench 307. This is because if the depth is the same, the stripe trench 307 and the dummy trench 309 can be formed simultaneously by changing the mask pattern when forming the trench.
  • the second gate electrode formed in the dummy trench 309 does not operate at all, and the channel region adjacent to the second gate electrode also does not operate. As a result, even when the threshold voltage is small, it is impossible to control the charge in the channel region by applying a negative voltage to the second gate electrode. -There is a concern that the leakage current between the sources will increase. For this, a method in which the source region 302 is not formed only in the region adjacent to the dummy trench 309 can be employed. In addition, when the threshold voltage is sufficiently high, it is not necessary to apply a negative voltage to the gate electrode 304. Therefore, a method of not forming the source region 302 only in the region adjacent to the dummy trench 309 is not necessarily required.
  • the protective diffusion layer 306 at the bottom of each is separated, so that the response speed of the protective diffusion layer 306 provided in the dummy trench 309 is the same as that of the stripe trench 307.
  • the dummy trench 309 is also preferably connected to the protective diffusion layer ground region 4. When the protective diffusion layer ground region 4 is not provided, it is necessary to consider that the protective diffusion layer 306 of the stripe trench 307 and the protective diffusion layer 306 of the dummy trench 309 are connected.
  • the parasitic capacitance of the MOSFET can be reduced and the switching loss can be improved.
  • the MOSFET having a structure in which the drift layer 2 and the SiC substrate 1 (buffer layer) have the same conductivity type has been described.
  • the drift layer 2 and the substrate 1 have different conductivity types.
  • the present invention is also applicable to an IGBT having a structure.
  • the SiC substrate 1 is a p-type substrate with respect to the semiconductor device 100 shown in FIG. 2, an IGBT configuration is obtained.
  • the source region 302 and source electrode 5 of the MOSFET correspond to the emitter region and emitter electrode of the IGBT, respectively
  • the drain electrode 7 of the MOSFET corresponds to the collector electrode of the IGBT.
  • the source region and the source electrode in this specification include an emitter region and an emitter electrode, and the drain electrode includes a collector electrode.
  • the n-type SiC substrate serving as the substrate may be deleted, and a p-type region formed by ion implantation in the epitaxial layer 2 may be used as the p-type substrate.
  • the semiconductor device formed using SiC which is one of the wide band gap semiconductors
  • other wide band gap semiconductors such as gallium nitride (GaN) -based materials and diamond are used.
  • the present invention can also be applied to a semiconductor device using silicon and a semiconductor device using a silicon semiconductor.
  • the n-type insulated gate semiconductor device has been described as an example in the above-described embodiment, the present invention may be applied to a p-type insulated gate semiconductor device.
  • a wide band gap semiconductor is a semiconductor having a wider band gap than at least a silicon semiconductor.
  • Embodiment 6 the semiconductor device according to the first to third embodiments described above is applied to a power conversion device.
  • the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a sixth embodiment.
  • FIG. 26 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.
  • the power conversion system shown in FIG. 26 includes a power supply 1000, a power conversion device 2000, and a load 3000.
  • the power supply 1000 is a DC power supply and supplies DC power to the power converter 2000.
  • the power source 1000 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good.
  • the power supply 1000 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 2000 is a three-phase inverter connected between the power source 1000 and the load 3000, converts the power supplied from the power source 1000 into AC power, and supplies AC power to the load 3000. As shown in FIG. 26, the power conversion device 2000 converts a DC power into an AC power and outputs the main conversion circuit 2001, and a drive circuit 2002 that outputs a drive signal that drives each switching element of the main conversion circuit 2001. And a control circuit 2003 that outputs a control signal for controlling the main conversion circuit 2001 to the drive circuit 2002.
  • the load 3000 is a three-phase motor driven by AC power supplied from the power converter 2000.
  • the load 3000 is not limited to a specific application, and is an electric motor mounted on various electric devices.
  • the load 3000 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.
  • the main conversion circuit 2001 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 2001 converts DC power supplied from the power source 1000 into AC power and supplies the AC power to the load 3000.
  • the main conversion circuit 2001 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes.
  • the semiconductor device according to any of the first to third embodiments described above is applied to each switching element of the main conversion circuit 2001.
  • the six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of the upper and lower arms that is, the three output terminals of the main conversion circuit 2001 are connected to the load 3000.
  • the drive circuit 2002 generates a drive signal for driving the switching element of the main conversion circuit 2001 and supplies it to the control electrode of the switching element of the main conversion circuit 2001. Specifically, in accordance with a control signal from a control circuit 2003 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element.
  • the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).
  • the control circuit 2003 controls the switching element of the main conversion circuit 2001 so that desired power is supplied to the load 3000. Specifically, based on the power to be supplied to the load 3000, the time (ON time) during which each switching element of the main converter circuit 2001 is to be turned on is calculated. For example, the main conversion circuit 2001 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 2002 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. In accordance with this control signal, the drive circuit 2002 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.
  • the semiconductor device according to any one of the first to third embodiments is applied to the switching element of the main conversion circuit 2001, the switching loss of the switching element is reduced and high-speed switching is performed. High frequency and reduction of switching loss can be realized, and a highly efficient power conversion device can be provided.
  • the present invention is not limited to this, and can be applied to various power conversion devices.
  • a two-level power converter is used.
  • a three-level or multi-level power converter may be used.
  • the present invention is applied to a single-phase inverter. You may apply.
  • the present invention can be applied to a DC / DC converter or an AC / DC converter.
  • the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor.
  • the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.
  • each embodiment can be appropriately modified and omitted.
  • a configuration in which a plurality of base regions 303 are exposed in a single contact hole 301 shown in FIG. 11 as a modification of the first embodiment can be applied to any configuration of the second to fifth embodiments. It is possible, and the modification in each embodiment can be applied as appropriate to other embodiments.

Abstract

Dispositif à semi-conducteur comprenant : une pluralité de régions de bandes actives (3) qui sont séparées les unes des autres par une pluralité de tranchées de bandes (307) ; et des régions de mise à la terre de couche de diffusion de protection (4) dans chacune desquelles une électrode de source (5) est connectée à une couche de diffusion de protection (306) par l'intermédiaire d'une ouverture (402) disposée, dans une couche semi-conductrice (2), entre des tranchées de bandes adjacentes (307). La pluralité de régions de bandes actives (3) comprend : une pluralité de premières régions de bandes actives (3a) comprenant les régions de mise à la terre de couche de diffusion de protection (4) ; et des secondes régions de bandes actives (3b) qui ne comprennent pas la région de mise à la terre de couche de diffusion de protection (4) et qui sont disposées entre les premières régions de bandes actives (3a). La couche de diffusion de protection (306) et l'électrode de source (5) sont connectées de manière fiable l'une à l'autre de telle sorte qu'une diminution d'une vitesse de commutation peut être supprimée.
PCT/JP2017/003434 2016-04-07 2017-01-31 Dispositif à semi-conducteur et dispositif de conversion de puissance WO2017175460A1 (fr)

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Cited By (9)

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CN111370485A (zh) * 2018-12-25 2020-07-03 无锡华润上华科技有限公司 沟槽型垂直双扩散金属氧化物半导体场效应晶体管
WO2020145109A1 (fr) * 2019-01-08 2020-07-16 三菱電機株式会社 Dispositif à semi-conducteur et dispositif de conversion de puissance
WO2023223590A1 (fr) * 2022-05-19 2023-11-23 住友電気工業株式会社 Puce semi-conductrice
WO2023223588A1 (fr) * 2022-05-19 2023-11-23 住友電気工業株式会社 Puce semi-conductrice
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JP2019110160A (ja) * 2017-12-15 2019-07-04 株式会社東芝 半導体装置
CN107942615A (zh) * 2017-12-22 2018-04-20 江苏宏微科技股份有限公司 一种电动汽车用igbt或mosfet版图结构
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JP2019197792A (ja) * 2018-05-09 2019-11-14 三菱電機株式会社 炭化珪素半導体装置、電力変換装置、および炭化珪素半導体装置の製造方法
US11984492B2 (en) 2018-05-09 2024-05-14 Mitsubishi Electric Corporation Silicon carbide semiconductor device, power converter, and method of manufacturing silicon carbide semiconductor device
CN111370485A (zh) * 2018-12-25 2020-07-03 无锡华润上华科技有限公司 沟槽型垂直双扩散金属氧化物半导体场效应晶体管
CN111370485B (zh) * 2018-12-25 2021-12-21 无锡华润上华科技有限公司 沟槽型垂直双扩散金属氧化物半导体场效应晶体管
JP6991370B2 (ja) 2019-01-08 2022-01-12 三菱電機株式会社 半導体装置及び電力変換装置
JPWO2020145109A1 (ja) * 2019-01-08 2021-09-30 三菱電機株式会社 半導体装置及び電力変換装置
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WO2020145109A1 (fr) * 2019-01-08 2020-07-16 三菱電機株式会社 Dispositif à semi-conducteur et dispositif de conversion de puissance
WO2023223590A1 (fr) * 2022-05-19 2023-11-23 住友電気工業株式会社 Puce semi-conductrice
WO2023223588A1 (fr) * 2022-05-19 2023-11-23 住友電気工業株式会社 Puce semi-conductrice

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