JP2003168799A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make current distribution in a cell uniform, in a semiconductor device having a polygon cell structure and its manufacturing method. <P>SOLUTION: In this semiconductor device, rounds are arranged on the corner parts 11b of cells 11 partitioned by trenches 4, as shown in (a). Since partial electric field concentration generated on the corner parts 11b of the cells 11 can be relieved, decrease of a threshold voltage at the corner parts 11b of the cells 11 can be prevented. As a result, current characteristics at the corner parts 11b of the cells 11 and linear parts 11a of the cells 11 can be made equivalent, and desired current characteristics can be obtained for the whole element. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a trench gate type transistor having a trench gate and a polygonal cell shape, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device of this type has a structure in which a large number of cells each forming a unit transistor are integrated on a semiconductor substrate and connected in parallel. The planar shape of the cell portion is shown in FIG. 6 (a), and a schematic sectional view taken along the line BB in FIG. 6 (a) is shown in FIG. 6 (b).

First, as shown in FIG. 6B, P ⁺
-Type or N ⁺ -type silicon substrate 21 is provided with N-type epitaxial growth layer 22, P-type base layer 23 is formed on this epitaxial growth layer 22, and inside this base layer 23 P-type body layer 32
And a trench 24 is formed so as to penetrate the base layer 23.

A gate electrode 26 is formed inside the trench 24 via a gate oxide film 25, and an N ⁺ type emitter layer 27 is formed on the side surface of the trench 24.
Are formed.

Further, an insulating film 28 is formed so as to cover a part of the emitter layer 27 and the upper portion of the trench 24, and the base layer 23 and the emitter layer 27 are exposed through the contact hole 28a formed in the insulating film 28. An emitter electrode 29 to be connected is formed. Then, the collector electrode 30 is formed on the back surface side of the silicon substrate 21.

As shown in FIG. 6A, the trench 24 has a hexagonal planar pattern, and the base layer 23 partitioned by the trench 24 has a hexagonal columnar shape, that is, a so-called hexagonal shape. The cell 31 is configured.

Using this hexagonal cell 31 as one unit transistor, a plurality of hexagonal cells 31 are integrated, and a common gate electrode 26, emitter electrode 29 and collector electrode 3 are formed.
It is connected in parallel by 0, and functions as one transistor as a whole.

[0008]

In the above-mentioned prior art, as shown in FIG. 6A, the top surface of the cell 31 is hexagonal, that is, polygonal, and when a voltage is applied to the gate electrode 26, Causes the electric field to concentrate on the corners 31b of the cells 31 rather than the straight parts 31a of the cells 31, so that the corners 31b of the cells 31
The electron density of b becomes large.

As a result, it was found that the threshold voltage at the corner 31b of the cell 31 was lowered and the current was concentrated at the corner 31b, so that the desired current characteristics could not be obtained as a whole element.

Therefore, in view of the above problems, it is an object of the present invention to make the current distribution in a cell uniform in a semiconductor device having a polygonal cell structure and a manufacturing method thereof.

[0011]

A semiconductor device according to claim 1 is a trench gate having a trench formed on one surface of a semiconductor substrate and a polygonal cell formed in a region partitioned by the trench. A semiconductor device having a type transistor structure is characterized in that corners of polygonal cells are rounded.

According to the first aspect of the invention, since the local electric field concentration generated at the corners of the cell can be relaxed, the electron density at the corners of the cell and the electron density at portions other than the corners can be reduced. Can be made approximately equal.

As a result, the threshold voltage at the corner of the cell can be prevented from lowering, so that the desired current characteristics can be obtained in the entire device.

The semiconductor device according to a second aspect is characterized in that the radius of curvature of the roundness provided at the corner of the polygonal cell is 0.4 μm or more.

According to the second aspect of the present invention, since the threshold voltage at the corners of the cell and the threshold voltage at the parts other than the corners can be made approximately the same, the radius of curvature of the roundness can be It is preferably 0.4 μm or more.

A method of manufacturing a semiconductor device according to a third aspect of the present invention is a trench gate type transistor structure having a trench formed on one surface of a semiconductor substrate and a polygonal cell formed in a region partitioned by the trench. In the method of manufacturing a semiconductor device including the above, when the trench is formed, a step of forming a roundness at a corner portion of the trench is added.

By applying the semiconductor device manufacturing method according to the third aspect, the semiconductor device according to the first aspect can be manufactured.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1A shows a plan view of a semiconductor device according to an embodiment of the present invention, and FIG.
The schematic sectional drawing which followed the AA line in (a) is shown.
Although FIG. 1 (a) shows a pattern in which three hexagonal cells are arranged, this is a unit cell pattern, and in reality, this unit cell pattern is tens of thousands to hundreds of thousands. , Is repeated many times according to the desired current value.

First, as shown in FIG. 1 (b), P⁺
Type or N⁺On the silicon substrate 1 of type N-type
The epitaxial growth layer 2 is formed and this epitaxial
A P-type base layer 3 is formed on the growth layer 2.
Inside the base layer 3, N ⁺Type emitter layer 7 and
A P-type body layer 16 is formed, and by these,
A semiconductor substrate 15 is formed.

Further, on one surface of the semiconductor substrate 15, a trench 4 penetrating the emitter layer 7 and the base layer 3 and reaching the epitaxial growth layer 2 is formed.

A gate insulating film 5 is formed on the inner wall of the trench 4.
Is formed, and the trench 4 is formed through the gate insulating film 5.
A gate electrode 6 made of doped polycrystalline silicon or the like is embedded and formed in the inside of the.

A BPSG film (insulating film) 8 is formed on one surface of the base layer 3 and the emitter layer 7 (the surface of the semiconductor substrate 15).
Is formed, and the emitter electrode 9 connected to the emitter layer 7 and the base layer 3 is formed through the contact hole 8a formed in the BPSG film 8.

A collector electrode 10 is formed on the entire back surface of the silicon substrate 15.

In such a semiconductor device, when a voltage is applied to the gate electrode 6, a channel is formed in the base layer 3 on the side surface of the trench 4, and a current flows between the emitter electrode 9 and the collector electrode 10 through this channel. Operates to flow.

As shown in FIG. 1A, the trench 4 has a hexagonal planar pattern, and the base layer 3 partitioned by the trench 4 has a hexagonal columnar shape, that is, a so-called hexagonal shape. The cell 11 is configured.

Using this hexagonal cell 11 as one unit transistor, a plurality of hexagonal cells 11 are integrated and connected in parallel by a common gate electrode 6, emitter electrode 9 and collector electrode 10 to form one transistor as a whole. Function as.

Here, in this embodiment, as shown in FIG. 1A, the corner portion 11b of the cell 11 is rounded.

The relationship between the gate voltage applied to the gate electrode 6 and the electron density is shown in FIG. From FIG. 2, there is a large gap between the electron density in the straight portion of the cell and the electron density in the corner portion of the cell unless the corners of the cell are rounded as in the prior art. In cell 11
If the corner portion 11b of the cell 11 is rounded, the straight portion 11 of the cell 11
It can be seen that the electron density at a and the electron density at the corner 11b of the cell 11 can be made substantially equal.

It is presumed that this is because the local electric field concentration generated at the corner 11b of the cell 11 can be relaxed.

Therefore, as in this embodiment, the corner portion 11b of the cell 11 is rounded so that the corner portion 1 of the cell 11 is
The decrease in the threshold voltage in 1b can be prevented, and the cell 11
It is possible to make the current characteristics of the corner portion 11b of the cell 11 and the straight portion 11a of the cell 11 uniform, and to obtain desired current characteristics of the entire device.

Next, the relationship between the radius of curvature of the roundness provided at the corner 11b of the cell 11 and the difference between the threshold voltage at the corner 11b of the cell 11 and the threshold voltage at the straight portion 11a of the cell 11 will be described. As shown in FIG. As shown in FIG. 3, when the radius of curvature of the roundness provided in the corner portion 11b of the cell 11 is 0.4 μm or more, the threshold voltage at the corner portion 11b of the cell 11 and the straight portion 11a of the cell 11 are It can be seen that the threshold voltage can be made approximately the same.

Therefore, it is preferable that the radius of curvature of the corner portion 11b of the cell 11 is 0.4 μm or more.

The characteristic lines of the corners (with roundness) of the cells in FIG. 2 show the results when the radius of curvature of the roundness is 0.4 μm.

Next, a method of manufacturing the above semiconductor device will be described with reference to the process chart shown in FIG.

First, as shown in FIG. 4A, P ⁺
An N ⁻ type epitaxial growth layer 2 is formed on a N type or N ⁺ type silicon substrate 1. Then, the P-type base layer 3, the N ⁺ -type emitter layer 7, and the P-type body layer 1
6 are sequentially formed by ion implantation and thermal diffusion.

Subsequently, as shown in FIG. 4B, an oxide film 12 serving as a trench mask is deposited on the surfaces of the base layer 3 and the emitter layer 7 by the CVD method, and a resist 13 is applied. Next, the resist 13 on the surface of the oxide film 12 is exposed and patterned by photolithography using a mask 14 having an opening corresponding to the region where the trench 4 is formed. Here, as shown in FIG. 5, the mask 14 used in the present embodiment has rounded corners 14b in advance. The shaded portion in FIG. 5 is a light transmitting portion during patterning.

Subsequently, as shown in FIG. 4C, the oxide film 12 formed on the region where the trench 4 is formed is removed by using the patterned resist 13 as a mask. Next, all the resist 13 is removed, and trench etching is performed using the oxide film 12 as a mask. Thereby, the trench 4 which penetrates the base layer 3 and the emitter layer 7 and reaches the epitaxial growth layer 2 is formed. At this time, the corners of the trench 4 are rounded so as to transfer the pattern of the mask 14 described above.

Subsequently, as shown in FIG. 4D, after removing the processing damage layer (not shown) by the above-mentioned trench etching by sacrificial oxidation, wet etching or gas etching, the gate insulating film 5 is formed. It is formed on the inner wall of the trench 4. Next, the gate electrode 6 is formed by depositing doped polycrystalline silicon containing phosphorus (P) inside the trench 4 by a low pressure CVD method or the like. Next, the atmospheric pressure CVD (APCVD) method or L
The BPSG film 8 is formed on the surfaces of the base layer 3 and the emitter layer 7 by the PCVD method or the like. Next, the BPSG film 8, that is, the base layer 3 is formed by using a photolithography technique.
And a contact hole 8a in a portion common to the emitter layer 7
To open a hole.

Subsequently, a metal is deposited on the entire surface of the front and back surfaces of the semiconductor substrate 15 by vapor deposition, sputtering, CVD, etc., and then a pattern of the metal electrode is formed by using the photolithography technique, and the emitter electrode 9 and The collector electrode 10 is formed. As a result, as shown in FIG. 1, the semiconductor device in which the corner 11b of the cell 11 is rounded is completed.

Here, in the present embodiment, the roundness provided in the corner 11b of the cell 11 is formed by previously providing the roundness in the corner 14b of the mask 14 used for forming the trench 4. However, the present invention is not limited to this, and a dry etching method using CF4 or O gas after forming a cell having no rounded corners,
The corners of the cells may be rounded by a wet etching method using hydrofluoric acid, nitric acid, or the like, or a thermal oxidation method, or a combination thereof may be used.

Further, when the roundness is formed at the corners of the cell by various methods as described above, it is preferable that the radius of curvature of the roundness is 0.4 μm or more as described above. If the radius of curvature of the roundness is 0.4 μm or more, the threshold voltage at the corner of the cell and the threshold voltage at the straight part of the cell can be made to be approximately the same, so that the corner of the cell and the straight line of the cell The current characteristics of the parts can be made uniform.

The present invention is not limited to the above embodiment, but can be applied to various aspects.

For example, the semiconductor device having the hexagonal cell structure has been described in the above embodiment, but the present invention is not limited to this, and any polygonal cell having a trench gate structure such as a quadrangular cell or an octagonal cell can be used. The effect of can be obtained.

It is also possible to employ a lateral type or up-drain type semiconductor device in which the collector electrode is provided on the front surface side of the semiconductor substrate.

The conductivity types of the epitaxial growth layer 2, the base layer 3, the emitter layer 7 and the body layer 16 are not limited to those shown in FIG. 1 (b), and may be reversed. Good.

[Brief description of drawings]

1A is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view taken along the line AA in FIG.

FIG. 2 is a graph showing the relationship between gate voltage and electron density.

FIG. 3 is a graph showing a relationship between a radius of curvature and a threshold voltage.

4A to 4D are process diagrams showing a method of manufacturing the semiconductor device shown in FIG.

FIG. 5 is a diagram showing a planar shape of a mask used for forming a trench and a cell.

6A is a plan view of a conventional semiconductor device, and FIG. 6B is a schematic sectional view taken along line BB in FIG.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... Epitaxial growth layer, 3 ... Base layer, 4 ... trench, 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... Emitter layer, 8 ... BPSG film (insulating film), 9 ... Emitter electrode, 10 ... collector electrode, 11 ... cell, 11a ... Straight part of cell, 11b ... corner of cell, 12 ... resist, 13 ... Silicon oxide film, 14 ... Mask, 14b ... corner of mask 15 ... Silicon substrate, 16 ... Body layer.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takashi Arakawa             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO

Claims (3)

[Claims] 1. A semiconductor device having a trench gate type transistor structure having a trench formed on one surface of a semiconductor substrate and a polygonal cell formed in a region partitioned by the trench, wherein the polygonal cell is provided. A semiconductor device having rounded corners. 2. The semiconductor device according to claim 1, wherein a radius of curvature of a roundness provided at a corner portion of the polygonal cell is 0.4 μm or more. 3. A method of manufacturing a semiconductor device having a trench gate type transistor structure having a trench formed on one surface of a semiconductor substrate and a polygonal cell formed in a region partitioned by the trench, A method of manufacturing a semiconductor device, wherein a step of forming a roundness at a corner portion of the trench is added when the trench is formed.