JPH06120347A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a guard ring type transistor which is high in breakdown strength against surges by making an opening to form a guard ring larger than an opening to form a diffused region. CONSTITUTION:A p-type base region 3 is formed within a layer 2 of n-type epitaxial growth in the surface of an n<+>-type silicon substrate 1, and further a region 4 of p-type body of a diameter (b) which passes through the layer 2 of epitaxial growth and the bottom of which reaches the substrate 1. A guard ring 4g, the diameter (a) of which becomes twice the depth of it within the layer 2 of epitaxial growth and the bottom of which reaches the substrate 1, is formed. For a guard ring 4f connected with a source electrode 9, it is unnecessary to make larger an opening in it than an opening in the region 4 of body since impurities are not aspirated into an LOCOS oxide film 8S. Since an amount by which impurity concentration decreases can be compensated for, the withstand voltage of the region 4 of p-type body accords with that of the guard ring 4g under the LOCOS oxide film, a surge current uniformly flows, so that the breakdown strength against surges may be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improvement of surge withstand voltage of a power transistor having a guard ring structure.

[0002]

2. Description of the Related Art In recent years, in power MOS devices, there is a tendency to reduce the on-resistance by miniaturizing the elements to improve the degree of integration.

By the way, as a semiconductor integrated circuit including a power transistor, as shown in FIG.
A p-type base region 3 is formed in the n-type epitaxial growth layer 2 formed on the surface of the + -type silicon substrate 1, and a deep p-type body region 4 is further formed in the p-type base region 3. Reference numeral 4 is formed so as to penetrate the epitaxial growth layer 2 and reach the bottom of the n + type silicon substrate 1. 5 is an n + diffusion layer as a source region, 6
Is a gate insulating film, 7 is a gate electrode, and 8 is an interlayer insulating film.

Further, in the same diffusion step as the diffusion for forming the p-type body region 4, a p-type diffusion layer as a peripheral guard ring 4g is formed around this.

At this time, the breakdown voltage of the Zener diode formed by the p type body region and the n + substrate is lower than the breakdown voltage of the base. Due to the presence of the peripheral guard ring 4g, when a surge voltage is applied, a current flows through the Zener diode, so that the parasitic npn bipolar transistor formed by the source region 5, the base region 3 and the n-type epitaxial layer 2 is turned on. Can be prevented. By the way, in an intelligent power device in which a power device and an IC for control are formed on the same chip, a LOCOS oxidation process is used in order to mitigate the step under the aluminum wiring in order to prevent disconnection of the aluminum wiring. That is, the peripheral guard ring 4g is covered with the LOCOS oxide film 8s. Therefore, p of guard ring 4g under the LOCOS oxide film
The type impurities diffuse into the LOCOS oxide film 8s to reduce the surface concentration. Therefore, the breakdown voltage of the p-type guard ring region under the LOCOS oxide film becomes higher than the breakdown voltage of the p-type body region. The breakdown voltage of the p-type guard ring region may be higher than that of the p-type body region by about 5V. As a result, a surge current flows mainly in the cell portion, the Zener diode in the guard ring portion does not work effectively, and there is a problem that the surge resistance of the entire chip decreases. This problem has become particularly prominent with the miniaturization of the diffusion window accompanying the miniaturization of the device.

[0006]

As described above, in the conventional guard ring type transistor, when it is used as an integrated circuit, the guard ring is covered with the LOCOS oxide film, and the impurities diffuse into the LOCOS oxide film. Due to this, there is a problem that the Zener diode in the guard ring portion does not work effectively and the surge resistance of the entire chip decreases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a guard ring type transistor capable of effectively operating the Zener diode of the guard ring section and having a high surge withstand voltage.

[0008]

Therefore, in the present invention, in a guard ring type transistor in which a guard ring is covered with an insulating film such as a LOCOS oxide film, an opening for forming a guard ring under the insulating film is formed. The size is made larger than the opening for forming the diffusion region.

[0009]

When the diameter of the diffusion window, that is, the guard ring is large, the substantial amount of impurities increases, which cancels out the effect of increasing the breakdown voltage of the guard ring portion due to the diffusion of impurities into the insulating film. Therefore, according to the above configuration, a decrease in breakdown voltage due to an increase in the substantial amount of impurities by increasing the diameter of the guard ring and an increase in breakdown voltage of the guard ring portion due to the diffusion of impurities into the insulating film compensate for each other. The withstand voltage of the p-type body region and the withstand voltage of the guard ring portion can be made equal to each other, and the surge voltage flows through the entire chip, so that the surge withstand capability can be improved.

That is, when the diffusion window becomes smaller and the diameter of the diffusion window becomes less than twice the diffusion depth due to the miniaturization of the element, the LOCOS oxide film is formed under the LOCOS oxide film even at the same impurity implantation amount and the same diffusion time. However, since the substantial amount of impurities differs due to the inflow of impurities into the LOCOS oxide film, the breakdown voltage differs depending on the diameter of the diffusion window.

Therefore, in the present invention, in the guard ring portion whose upper portion is covered with an insulating film such as a LOCOS oxide film, the size of the opening is made larger than the opening for forming the diffusion region, and the inside of the insulating film is filled. The decrease of the impurity concentration due to the inflow of impurities is compensated by the increase of the substantial impurity concentration due to the increase of the opening to prevent the impurity concentration of the guard ring region from becoming lower than the impurity concentration of the diffusion region, which greatly affects the breakdown voltage reduction. Is not to give.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In this semiconductor device, as shown in FIGS. 1 and 2 (FIG. 2 is a plan view), the diameter of the second guard ring region 4g formed under the LOCOS oxide film 8S is
It is characterized in that it is made larger than the diameter of the P-type body region 4 and at least twice as large as the depth, and the other parts are formed in the same manner as in the conventional example. . Here, it is connected to the source electrode 9 and the LO
In the first guard ring region 4f whose surface is not covered with the COS oxide film, impurities are not sucked into the LOCOS oxide film 8S, so that it is not necessary to make the opening larger than the opening of the p-type body region. Absent.

That is, as shown in FIGS. 1 and 2, this guard ring type transistor has an n type epitaxial growth layer 2 formed on the surface of an n + type silicon substrate 1,
A p-type base region 3 is formed, and a deep p-type body region 4 is further formed in the p-type base region 3. The p-type body region 4 penetrates the epitaxial growth layer 2 and the bottom is n +.
It is formed so as to reach the mold silicon substrate 1. Further, while the p-type body region 4 has a diameter b,
In the epitaxial growth layer 2 around the type body region 4, a second guard ring 4g is formed so that the diameter a is twice the depth and the bottom reaches the n + type silicon substrate 1. Also, it is connected to the source electrode 9 and
In the first guard ring region 4f not covered with the OS oxide film, impurities are not sucked out to the LOCOS oxide film 8S, so that the opening portion thereof has a p-type structure like the second guard ring 4g. It is formed to the same extent as the opening of the body region 4 without being made larger.

Reference numeral 5 is an n + diffusion layer as a source region, 6 is a gate insulating film, 7 is a gate electrode made of a polycrystalline silicon layer, 8 is an interlayer insulating film, 9 is a source electrode, and 10 is a drain electrode.

Here, the second guard ring 4g is formed so that the diameter a is larger than the diameter b of the p-type body region 4, double the depth, and the bottom reaches the n + -type silicon substrate 1. Therefore, a sufficient amount of substantial impurities can be secured,
Even if the surface concentration is reduced by diffusing into the LOCOS oxide film 8S, this reduction can be compensated by securing a substantial amount of impurities, and the breakdown voltage of the p-type body region and the second underlayer of the LOCOS oxide film can be compensated.
The withstand voltage of the guard ring region 4g is the same, the surge current flows uniformly, and the surge withstand capability can be improved. This is because when the diffusion window becomes smaller and the diameter of the diffusion window becomes less than twice the diffusion depth due to the miniaturization of the element, the actual impurity amount differs even with the same impurity implantation amount and the same diffusion time. The withstand voltage varies depending on the diameter of the diffusion window. By utilizing this, the increase in breakdown voltage due to the inflow of impurities into the LOCOS oxide film is compensated by increasing the diameter of the opening.

Although the guard ring has a circular shape in the above embodiment, it may have a polygonal shape such as a regular hexagon or a square. However, when the cell has a polygonal shape, the electric field tends to be concentrated at the corners of the cell and the breakdown voltage tends to be low. Therefore, the breakdown voltage can be increased when the number of corners is large and the circle is as close as possible.

FIG. 3 shows the relationship between the opening diameter and the pressure resistance.
Here, the horizontal axis represents the ratio (0.3 to 1.2) of the opening diameter of the diffusion layer region to the diffusion depth, and the vertical axis represents the surge withstand voltage. As is clear from this figure, the withstand voltage is set to 1 by changing the ratio of the opening diameter to the diffusion depth from this figure.
It can be seen that it is possible to control about 5V. For example p
The diameter b of the mold body region 4 and the diffusion opening diameter a of the second guard ring 4g have the same value (a / h, b / h = 0.4).
5), if the breakdown voltage of the guard ring transistor is increased by 5V due to the outflow of impurities, it can be seen from this figure that the breakdown voltage of 5V can be reduced by setting b / h = 0.68.

[0019]

As described above, according to the present invention, a semiconductor integrated circuit device including a guard ring type transistor having a high surge withstand voltage can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a guard ring transistor of the present invention.

FIG. 2 is a plan view of the same guard ring transistor.

[Fig. 3] Withstand voltage of the transistor and diameter of guard ring /
Diagram showing the relationship with depth

FIG. 4 is a cross-sectional view showing a conventional guard ring type transistor.

[Explanation of symbols]

 1 silicon substrate 2 n-type epitaxial growth layer 3 p-type base region 4 p-type body region 4f first p-type guard ring region 4g second p-type guard ring region 5 source region 6 gate insulating film 7 gate electrode 8 interlayer Insulating film 8s LOCOS insulating film 9 Source electrode 10 Drain electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location 9170-4M H01L 27/08 102 F

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a diffusion region of a second conductivity type formed in the semiconductor substrate, an insulating film surrounding the diffusion region of the second conductivity type, and the semiconductor. In a semiconductor device including a guard ring formed of a diffusion region of the second conductivity type formed in a substrate, the guard ring region is divided into regular polygonal or circular cell regions, and the guard ring is formed below the insulating film. A semiconductor device, wherein the area of the opening of the region is formed larger than the area of the diffusion region.