JPH04215468A - Static protective device - Google Patents

Abstract

PURPOSE:To realize a built-in IC protective p-n junction diode, capable of easy voltage setting, in an easy and effective manner under ordinary process conditions by using only a patterned mask. CONSTITUTION:A semiconductor substrate includes a p-n junction diode region 14 with one acute end, and a resistor region 15 opposing the acute end of the region 14. The regions 14 and 15 are covered with an insulating film having a contact 17 to the diode region 14. The contact 17 is connected with a wiring 18 that overlaps the insulating film. Since the diode region has a small radius of curvature at the acute end, there appears a concentration of electric field, and thus a local breakdown occurs at a lower voltage than the breakdown voltage of the normal p-n junction. A desired breakdown voltage can be set by arranging the diode region and the resistor region close to each other. If an excessive positive bias is applied to the wiring, a surface inversion occurs at the gate between the diode region and the resistor region, and a leakage current flows to ground to protect the integrated circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in electrostatic protection devices for ICs.

0002

2. Description of the Related Art Numerous inventions and ideas have been disclosed for electrostatic protection of ICs. Due to the dramatic increase in the degree of integration of ICs, the shapes and dimensions of elements included in ICs are becoming smaller year by year, resulting in a decrease in the electrostatic breakdown voltage of the elements themselves. Depending on the handling and usage conditions of the IC, an overvoltage exceeding the maximum rated voltage may be momentarily applied, which may lead to destruction of the IC. As a solution, if an overvoltage above a certain level is applied before reaching the breakdown voltage of the device, a current path different from that of the IC circuit is used to connect the device to GND (
Measures are taken to flow it to the ground potential). Typical methods include those that utilize the breakdown of a PN junction diode, and those that utilize a MOS structure (MOS FE).
There are some methods that utilize T), but the prior art has the following problems. Note that since the present invention also utilizes the breakdown of a PN junction diode, the description of the prior art will be limited to that means. FIG. 4 shows an example of a conventional electrostatic protection diode, and FIG. 5 shows its equivalent circuit. In FIG. 4, 1 is a semiconductor substrate, 2 is a buried layer, 3 is a diode region, 4 is an insulating film, and 5 is a metal wiring, which connects the IC terminal and GN.
By connecting a diode between D and D, if an overvoltage higher than the reverse voltage of this diode is applied, this protection diode breaks down first to protect the IC circuit. However, if the components and manufacturing of the electrostatic protection diode area between the ICs are the same, the PN junction breakdown voltage will be the same, and there is no resistor etc. connected at the end of this protection diode, and it can be directly connected to the transistor or diode of the IC circuit. If it is connected, the effect will be diminished.

In order to improve the above-mentioned protection means, proposals have been made to add a resistor as a protection circuit and to lower the junction breakdown voltage of the protection diode itself. For example, Japanese Patent Publication No. 46-8250 discloses a protection means shown in FIG. 6. In the figure, 1 is a semiconductor substrate, 6 and 7 are regions of a different conductivity type from the substrate, S is a source electrode, D is a drain electrode,
G is a gate electrode, 4 is an insulating film, and 8 is a protective diode region. This makes the protection diode junction shallower and
I'm trying to lower the breakdown voltage. Further, Japanese Patent Publication No. 46-8010 discloses a protection means shown in FIG. 7. This is done by providing a low resistivity region 9 of the same conductivity type as the substrate around the diode region to lower the breakdown voltage.

0004

[Problems to be Solved by the Invention] However, all of the above-mentioned protection means increase and complicate the manufacturing process, require accurate manufacturing of the protection diode itself, and are difficult to manufacture. Therefore, it has the disadvantage that the manufacturing cost increases as a result.

[0005]

OBJECT OF THE INVENTION The present invention has been made to solve the above problems, and provides an IC that can be manufactured relatively easily and at low cost.
The purpose is to provide an electrostatic protection device.

[0006]

[Means for Solving the Problems] An electrostatic protection device according to the present invention includes: a first conductivity type buried region formed in a semiconductor substrate; a second conductivity type region formed above the buried region;
A first conductivity type diode region is formed within the second conductivity type region and has an acute angle at one end when viewed from above, and a first conductivity type diode region is formed within the second conductivity type region and faces the acute angle portion of the diode region. The formed first conductivity type resistance region has a contact at least on the diode region, and an insulating film that covers the diode region and the resistance region, and the contact is in contact with the insulating film on the resistance region. The gist is that the wiring is formed so as to pass through the wiring.

[0007]

[Function] By providing the planar shape of the diode region and the resistance region facing the acute angle portion thereof, the curvature (radius of curvature) on the plane of the diffusion region, surface inversion, and punch-through breakdown voltage with the resistance region can be combined. According to
Since the breakdown voltage is lowered and the current flows to GND through the resistance region, there is no instantaneous large current that not only protects the IC itself but also protects the external circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic sectional view of the main parts of the electrostatic protection device of the present invention, FIG. 2 is a plan view, and FIG. 3 is an equivalent circuit. In the drawing, 10 is a p-type silicon substrate, 11 is an n-type buried region, 12 is a p-type well region, and 13 is a high concentration p-type isolation region. An n-type diode region 14 having an acute angle, and an n-type resistance region 15 facing the acute angle portion of the diode region 14 are formed. Reference numeral 16 denotes an SiO2 insulating film, which has a contact 17 on the diode region 14 and covers the diode region 14 and the resistance region 15. Reference numeral 18 denotes an Al wiring, which is provided so as to be in contact with the contact 17 and pass through the insulating film 16 on the resistance region 15. The resistance region 15 is a resistance whose one end is grounded to GND. In the electrostatic protection circuit of the above embodiment, some of the corners of the diode region 14 are made into acute angles by the mask pattern. The angle θ is determined depending on the required pressure resistance. The diffusion layer that will become the diode region 14 is formed at the same time as the collector wall, which is performed to reduce the collector resistance of the NPN transistor. As mentioned above, by making a part of the diode region at an acute angle, the radius of curvature there becomes small, and electric field concentration occurs there.
Local breakdown occurs at a voltage lower than the original PN junction breakdown voltage.

[0009] With conventional protection means, the above-mentioned FIG.
This effect is aimed at by shallowly diffusing the diffusion layer itself, which becomes the diode, to reduce the radius of curvature of the corners in the depth direction, and the present invention embodies this effect on a planar pattern. Furthermore, the diode region 14 and the resistance region 1
5 is by providing adjacent diffusion regions of the same type,
Can be set to any desired pressure resistance. This is because the diode region 14 is always used in a reverse bias state, and in normal use, a certain depletion layer (a depletion region where no charge exists) spreads to the low concentration p side due to the voltage, but when an overvoltage is applied, , this depletion layer spreads throughout the vertical and horizontal directions. At this time, by providing 15 resistance diffusion regions at positions in contact with the depletion layer, punch-through occurs and the breakdown voltage is determined. In order to make this punch-through voltage even more effective, the present invention adds another structure. As a third configuration of the present invention, an electrode wiring 18 is arranged on an oxide insulating film 16 covering the diode region 14 and the resistance region 15, and the MOS
It has an FET structure. When an excessively positive bias is applied to the wiring, the surface of the gate between the diode region 14 and the resistance region 15 is reversed (or the carrier concentration is reduced to a state where the depletion layer is likely to extend), and a leakage current is generated between the gate and the GND.
Flows into the air and works to protect the IC circuit. As described above, the present invention combines the planar structure of the diode region using the radius of curvature, the provision of the same diffusion layer to utilize the punch-through breakdown voltage, and the use of the MOSFET effect. The breakdown voltage is determined by the structure. Further, there is no need to set new manufacturing conditions to form these, and they can be formed at low cost using only a mask pattern under the same manufacturing conditions.

0010

[Effects of the Invention] As described above, according to the present invention,
Since the breakdown voltage of the electrostatic protection diode can be determined by the mask pattern, a simple and effective electrostatic protection circuit can be realized. Additionally, there is no need for manufacturing changes or additions.
Voltage can be easily set and voltage changes can be easily accommodated.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an electrostatic protection device showing one embodiment of the present invention.

FIG. 2 is a plan view.

FIG. 3 is an equivalent circuit diagram.

FIG. 4 is a schematic cross-sectional view of a conventional electrostatic protection device.

FIG. 5 is an equivalent circuit diagram.

FIG. 6 is a schematic cross-sectional view of a conventional improved electrostatic protection device.

FIG. 7 is a schematic cross-sectional view of a conventional improved electrostatic protection device.

[Explanation of symbols]

11 N-type buried region 12 Low concentration p-type well region 13 High concentration p-type isolation region 14 Diode area 15 Resistance area 18 Wiring

Claims (1)

[Claims] Claims: 1. A buried region of a first conductivity type formed in a semiconductor substrate, a region of a second conductivity type formed above the buried region, and a region of a second conductivity type formed in the second conductivity type region and having one end formed in a plan view. a first conductivity type diode region having an acute angle; a first conductivity type resistance region formed within the second conductivity type region and facing the acute angle portion of the diode region;
a contact on at least the diode region;
an insulating film covering the diode region and the resistance region;
An electrostatic protection device comprising: a wiring formed to contact the contact and pass over an insulating film on the resistance region.