KR102187903B1 - Power semiconductor device - Google Patents

Abstract

According to an aspect of the present invention, a power semiconductor device includes: a semiconductor layer including a main cell region, a sensor region, and an insulating region between the main cell region and the sensor region; a plurality of power semiconductor transistors formed in the main cell region; a plurality of current sensor transistors formed in the sensor region; and a protection resistor which is formed in the insulating region to connect the emitter electrodes of the plurality of power semiconductor transistors and the emitter electrodes connected to the plurality of current sensor transistors to each other in an abnormal operation situation. At least one additional floating region is formed in the semiconductor layer between the protection resistor and a floating region in the semiconductor layer adjacent to the outermost current sensor transistor among the plurality of current sensor transistors, thereby improving the operating characteristics of the sensor region.

Description

Power semiconductor device

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission.

Power semiconductor devices are semiconductor devices that operate in high voltage and high current environments. Such power semiconductor devices are used in fields requiring high power switching, for example, inverter devices. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a power MOSFET, and the like. These power semiconductor devices are basically required to withstand voltage characteristics for a high voltage, and recently, additionally, a high-speed switching operation is required.

In order to monitor the operating current, the power semiconductor device monitors the current of the main operating cell by forming a current sensor cell in the sensor region at a predetermined mirroring ratio compared to the main operating cell. However, since the area of the current sensor cell is very small compared to the main operation cell, it is difficult to secure an appropriate scale ESD capacitance in the sensor area.

Further, as shown in FIG. 1, due to the gate delay effect, there is a problem that the operation of the current sensor cell is delayed compared to the main operation cell. After the gate voltage V _G is applied, the current I _CE of the main operation cell increases linearly, but it can be seen that the voltage V _s of the current sensor cell increases after a predetermined time delay.

Republic of Korea Publication No. 20140057630 (released on May 13, 2014)

The present invention has been made to solve the above-described problems, and an object thereof is to provide a power semiconductor device capable of improving the operating characteristics of a sensor region. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A power semiconductor device according to an aspect of the present invention for solving the above problem includes a semiconductor layer including a main cell region, a sensor region, and an insulating region between the main cell region and the sensor region, and the main cell region In an abnormal operation situation, a plurality of power semiconductor transistors formed, a plurality of current sensor transistors formed in the sensor region, an emitter electrode of the plurality of power semiconductor transistors, and an emitter electrode connected to the plurality of current sensor transistors At least one additional floating on the semiconductor layer between the protective resistor and the floating region in the semiconductor layer adjacent to the outermost current sensor transistor among the plurality of current sensor transistors including a protection resistor formed in the insulating region to be connected to each other A region is formed.

In the power semiconductor device, the at least one additional floating area may include a plurality of floating areas spaced apart from each other in the insulating area.

In the power semiconductor device, the semiconductor layer includes a drift region doped with impurities of a first conductivity type over the main cell region, the sensor region, and the insulating region, and the floating region and the at least one additional floating region A region is formed by doping with an impurity of a second conductivity type opposite to the first conductivity type, and the drift region and the additional floating region may form a PN diode structure.

In the power semiconductor device, the protection resistor includes a protection junction region formed by doping an impurity of a second conductivity type in the semiconductor layer, and the at least one additional floating region comprises the protection junction region and the protection junction region in the semiconductor layer. It may be spaced apart between the floating areas.

In the power semiconductor device, a part of the drift region may be interposed between the protection junction region and the at least one additional floating region, and between the floating region and the at least one additional floating region.

A power semiconductor device according to another aspect of the present invention for solving the above problem includes a plurality of power semiconductor transistors formed in a main cell region of a semiconductor layer, and an emitter connected to the emitter electrode of the plurality of power semiconductor transistors. A terminal, a plurality of current sensor transistors formed in a sensor region of the semiconductor layer, and a current sensor terminal connected to an emitter electrode of the plurality of current sensor transistors to monitor current of the power semiconductor transistors, and the power Between the main cell region and the sensor region so as to connect the gate electrode of semiconductor transistors and the gate electrode of the plurality of current sensor transistors and the emitter terminal and the current sensor terminal to each other in an abnormal operation situation. A floating region in the semiconductor layer adjacent to an outermost current sensor transistor among the plurality of current sensor transistors and at least one additional floating region is formed in the semiconductor layer between the protection resistor. .

In the power semiconductor device, the at least one additional floating area may include a plurality of floating areas spaced apart from each other in the insulating area.

In the power semiconductor device, the semiconductor layer includes a drift region doped with impurities of a first conductivity type over the main cell region, the sensor region, and the insulating region, and the floating region and the at least one additional floating region A region is formed by doping with an impurity of a second conductivity type opposite to the first conductivity type, and the drift region and the additional floating region may form a PN diode structure.

In the power semiconductor device, the protection resistor includes a protection junction region formed by doping an impurity of a second conductivity type in the semiconductor layer, and the at least one additional floating region comprises the protection junction region and the protection junction region in the semiconductor layer. It may be spaced apart between the floating areas.

According to the power semiconductor device according to an embodiment of the present invention made as described above, it is possible to alleviate a phenomenon in which the current sensor transistors are driven with a delay compared to the power semiconductor transistors. Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a timing graph showing driving of a conventional power semiconductor device.
2 is a schematic plan view showing a power semiconductor device according to an embodiment of the present invention.
3 is a circuit diagram showing a power semiconductor device according to an embodiment of the present invention.
4 is a circuit diagram showing a part of the power semiconductor device of FIG. 3.
5 is an equivalent circuit diagram illustrating driving of a power semiconductor device according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present invention.
7 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the following embodiments make the disclosure of the present invention complete, and the scope of the invention to those of ordinary skill in the art. It is provided to fully inform you. In addition, in the drawings for convenience of description, at least some of the constituent elements may be exaggerated or reduced in size. In the drawings, the same reference numerals refer to the same elements.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions have been exaggerated for the sake of explanation, and thus are provided to explain general structures of the present invention. The same reference numerals indicate the same elements. When referring to a configuration such as a layer, region, or substrate as being on another configuration, it will be understood that it is directly on top of the other configuration or that there may also be other intervening configurations in between. On the other hand, when it is referred to as being "directly on" of another configuration, it is understood that there are no intervening configurations.

2 is a schematic plan view showing a power semiconductor device according to an embodiment of the present invention, FIG. 3 is a circuit diagram showing a power semiconductor device according to an embodiment of the present invention, and FIG. 4 is a schematic plan view of the power semiconductor device of FIG. It is a schematic diagram showing a part.

Referring to FIG. 2, the power semiconductor device 100 may be implemented using a semiconductor layer 105 including a main cell area MC and a sensor area SA. The power semiconductor device 100 may include a wafer, chip, or die structure.

A plurality of power semiconductor transistors (PT of FIG. 3) may be formed in the main cell area MC. A plurality of current sensor transistors (ST in FIG. 3) may be formed in the sensor area SA to monitor currents of the power semiconductor transistors PT.

For example, the two power semiconductor transistors PT and the current sensor transistors ST may include an insulated gate bipolar transistor (IGBT) or a power MOSFET structure. The IGBT may include a gate electrode, an emitter electrode, and a collector electrode. In FIGS. 3 to 4, an IGBT is described as an example as the power semiconductor device 100.

2 to 4 together, the power semiconductor device 100 may include a plurality of terminals for connection to the outside. For example, the power semiconductor device 100 includes an emitter terminal 69 connected to the emitter electrodes of the power semiconductor transistors PT, and a Kelvin emitter connected to the Kelvin emitter electrodes of the power semiconductor transistors PT. The terminal 66, the current sensor terminal 64 connected to the emitter electrode of the current sensor transistors ST for monitoring current, the gate electrode of the power semiconductor transistors PT, and the current sensor transistors ST. The gate terminal 62 connected to the gate electrode, the temperature sensor terminals 67 and 68 connected to the temperature sensor TC for monitoring the temperature, and/or the power semiconductor transistors PT and the current sensor transistors ST ) May include a collector terminal 61 connected to the collector electrode. In FIG. 3, the collector terminal 61 is on the rear surface of the power semiconductor device 100 in FIG. 2.

The temperature sensor TC may include a junction diode connected to the temperature sensor terminals 67 and 68. The junction diode may include a junction structure between at least one n-type impurity region and at least one p-type impurity region, such as a P-N junction structure, a P-N-P junction structure, an N-P-N junction structure, and the like. This structure exemplarily describes a structure in which the temperature sensor TC is embedded in the power semiconductor device 100, but the temperature sensor TC may be omitted in a modified example of this embodiment.

The power semiconductor transistor PT is connected between the emitter terminal 69 and the collector terminal 61, and the current sensor transistor ST is the power semiconductor transistor PT between the current sensor terminal 64 and the collector terminal 61. ) And partially connected in parallel. The gate electrode of the current sensor transistor ST and the gate electrode of the power semiconductor transistor PT are sharedly connected to the gate terminal 62 through a predetermined resistance.

The current sensor transistor ST is formed to have substantially the same structure as the power semiconductor transistor PT, but may be reduced to a predetermined ratio. Accordingly, by monitoring the output current of the current sensor transistor ST, it is possible to indirectly monitor the output current of the power semiconductor transistor PT.

In this embodiment, the emitter terminal 69 and the current sensor terminal 64 may be connected through a predetermined protection resistor Re. The protection resistance Re may be a sufficiently large insulation resistance so as to insulate between the emitter terminal 69 and the current sensor terminal 64 during normal operation of the power semiconductor device 100 so as not to substantially allow the flow of current. . However, the meaning that the emitter terminal 69 and the current sensor terminal 64 are connected through the protection resistor (Re) means that in the case of an abnormal operation situation, for example, an electro static discharge (ESD) situation, the electric current is allowed to flow. It can mean connected by.

Accordingly, in a normal operation situation, a current or electron flow through the emitter terminal 69 of the power semiconductor transistor PT and a current or electron flow through the current sensor terminal 64 of the current sensor transistor ST are divided. However, in an abnormal operation situation, such as an ESD situation, a very large voltage is applied or a very large current is introduced, so that the current or electron flow of the current sensor transistor ST is transferred to the power semiconductor transistor PT through the protection resistor Re. Can be distributed. Accordingly, even in the sensor area SA having a relatively small size compared to the main cell area MC, it is possible to increase the capacitance and improve the electrostatic characteristics. That is, by using the current distribution through the protection resistor Re, the sensor area SA may be protected from an ESD impact.

5 is an equivalent circuit diagram illustrating driving of a power semiconductor device according to example embodiments.

3 to 5, the emitter terminal 69 functions as a ground terminal of the power semiconductor transistors PT, and the Kelvin emitter terminal 66 is a ground terminal for the driver portion of the gate terminal 62. Can function as The potential of the sensing resistor Rs connected to the current sensor terminal 64 at the sensing voltage node CS may be measured. Through this, the direction of the current flowing through the current sensor terminal 64 can be calculated.

In FIG. 5, a capacitor C _GF and a capacitor C _GE represent a gate-emitter capacitor, a capacitor C _GJ represents a gate-collector capacitor, and a resistance Rp represents a gate resistance.

6 is a cross-sectional view illustrating a power semiconductor device according to another embodiment of the present invention.

2 and 6, the semiconductor layer 105 includes a main cell area MC, a sensor area SA, and an insulating area IA between the main cell area MC and the sensor area SA. can do. Furthermore, the semiconductor layer 105 may further include a terminal region for forming other terminals that function as external output terminals.

In this embodiment, the power semiconductor transistors PT may be formed in the main cell region MC, and the current sensor transistor ST may be formed in the sensor region SA, respectively. For example, the sensor area SA is not under the current sensor terminal 64 and may be formed on the semiconductor layer 105 outside the sensor area SA. Accordingly, the current sensor terminal 64 functioning as an output terminal of the current sensor transistors ST is a separate terminal area, for example, a semiconductor layer outside the main cell area MC and the sensor area SA. 105) can be formed. In this case, the size of the current sensor terminal 64 can be adjusted regardless of the size of the sensor area SA.

In some embodiments, the sensor area SA may be formed by remodeling a partial area of the main cell area MC. In this case, the insulating area IA is the main cell area MC and the sensor area SA. It may be disposed between the main cell area MC and the sensor area SA to be electrically insulated during operation. Accordingly, the insulating area IA may be disposed to surround at least a portion of the sensor area SA. As described above, a protection resistor Re may be formed in the insulating region IA.

Referring to FIG. 6, the semiconductor layer 105 may refer to one or more layers of semiconductor material, and, for example, may refer to a part of a semiconductor substrate and/or one or multiple epitaxial layers. May be. For example, the semiconductor layer 105 may include a drift region 107 and a well region 110.

In the main cell region MC, the semiconductor layer 105 may further include a source region 112 in the well region 110. Here, the source region 112 may also be referred to as an emitter region. Hereinafter, the source region 112 may refer to a source region or an emitter region.

Furthermore, the semiconductor layer 105 may further include a floating region 125 in a portion between the gate electrodes 120 and connected to the lower portion of the gate electrode 120. The floating region 125 may be formed deeper than the bottom of the gate electrode 120 and may be formed to connect two adjacent gate electrodes 120. The floating region 125 is formed in the semiconductor layer 105 opposite the well region 110 between two adjacent power semiconductor transistors PT, and further adjacent to the outermost power semiconductor transistor PT, It may be formed on the semiconductor layer 105 opposite the well region 110.

The drift region 107 and the source region 112 may have a first conductivity type, and the well region 110 and the floating region 125 may have a second conductivity type. The first conductivity type and the second conductivity type have opposite conductivity types, but may be any one of n-type and p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

The drift region 107 may be provided as an epitaxial layer of a first conductivity type, and the well region 110 may be doped with impurities of a second conductivity type to the epitaxial layer or formed as an epitaxial layer of a second conductivity type. Can be formed. The source region 112 may be formed by doping an impurity of the first conductivity type in the well region 110 or by additionally forming an epitaxial layer of the first conductivity type.

The collector region 128 may be provided under the drift region 107, and the collector electrode 155 may be provided under the collector region 128 to be connected to the collector region 128. For example, the drift region 107 may be provided on a semiconductor substrate (not shown), the semiconductor substrate defines at least a part or all of the collector region 128 having the second conductivity type, and the collector electrode 155 ) May be provided on the lower surface of the semiconductor substrate. As another example, the collector region 128 may be provided as an epitaxial layer having a second conductivity type under the drift region 107.

The gate electrode 120 may be formed by being recessed into the semiconductor layer 105 to fill at least one trench formed in the semiconductor layer 105. The trench may be formed to a predetermined depth from the surface of the semiconductor layer 105, for example, may be formed to penetrate the source region 112 and the well region 110 and extend to a part of the drift region 107. The trench may be rounded at its edge, such as a lower edge, to suppress the concentration of the electric field.

The gate insulating layer 118 may be interposed between the gate electrode 120 and the semiconductor layer 105 in the trench. An insulating layer 130 may be formed on the gate electrode 120. The number of gate electrodes 120 may be appropriately selected according to an operation specification required by one or more, and does not limit the scope of this embodiment.

The emitter electrode 145 may be formed on the emitter region or the source region 112. An insulating layer 133 may be interposed between the semiconductor layer 105 and the emitter electrode 145.

The structure of one sensor current transistor ST in the sensor area SA may be substantially the same as the structure of one power semiconductor transistor PT in the main cell area MC. For example, in the sensor area SA and the main cell area MC, the drift area 107, the floating area 125, and the gate electrode 120 may be formed continuously without being divided.

In the sensor region SA, the floating region 125 is formed in the semiconductor layer 105 opposite the well region 110 between two adjacent current sensor transistors ST, and further, the outermost current sensor transistor ST ) May be formed on the semiconductor layer 105 opposite to the well region 110.

In the sensor area SA and the main cell area MC, the well area 110 may be formed to be separated from each other. Further, the emitter region or the source region 112 in the sensor region SA is formed in the well region 110 in the sensor region SA to be separated from the emitter region or the source region 112 in the main cell region MC. Can be. Further, the emitter electrode 145a in the sensor area SA is formed on the emitter area or the source area 112 in the sensor area SA, and is insulated between the semiconductor layer 105 and the emitter electrode 145a. The layer 133 may be interposed.

In this embodiment, at least a portion of the power semiconductor transistors PT and at least a portion of the current sensor transistors ST may be connected to each other in an abnormal operation situation through the protection resistor Re formed in the insulating region IA. .

For example, the protection resistor Re may include a protection junction region 125a formed by doping impurities in the semiconductor layer 105. More specifically, the emitter electrode 145 of the power semiconductor transistors PT and the emitter electrode 145a of the current sensor transistor ST may be connected to the protection junction region 125a.

The drift region 107 may be doped with impurities of a first conductivity type, and the protection junction region 125a may be doped with impurities of the same second conductivity type as the floating region 125 and the well region 110. Accordingly, the protection junction region 125a and the drift region 107 may form a PN doped structure. Furthermore, the protection junction area 125a may be formed to have the same or similar depth as the floating area 125. Accordingly, in some embodiments, the floating area 125 and the protection junction area 125a may be formed at the same time.

Since the resistance of the protection junction area 125a is very high compared to the source area 112, the flow of current through the protection resistance Re is negligible in a normal operating situation. Accordingly, the protection junction region 125a has a high resistance in the normal operating condition of the power semiconductor device 100 and thus hardly allows the flow of current. Can be adjusted.

The at least one additional floating region 125c is a semiconductor layer between the floating region 125 and the protection resistor Re in the semiconductor layer 105 adjacent to the outermost current sensor transistor ST among the current sensor transistors ST. 105) can be formed. More specifically, the additional floating region 125 is formed by doping with impurities of the second conductivity type, and accordingly, the additional floating region 125 may form the drift region 107 and a PN diode structure.

Furthermore, when the protection resistor (Re) is implemented as the protection junction region 125a, the additional floating region 125c is spaced apart from two between the protection junction region 125a and the floating region 125 in the semiconductor layer 105 It can be arranged as much as possible. Accordingly, a part of the drift region 107 may be interposed between the protection junction region 125a and the additional floating region 125c and between the floating region 125 and the additional floating region 125c.

In the structure without the additional floating region 125c, the drift region 107 between the floating region 125 and the protection junction region 125a adjacent to the outermost side of the current sensor transistor ST when the power semiconductor device 100 is operated. A depletion layer of) may be expanded, so that the floating region 125 may be connected to the protective junction region 125a to which the emitter potential is applied. As described above, when the floating region 125 has an emitter potential, there is a problem in that an abnormal operation such as gate delay occurs in the sensor current transistors ST at the initial stage of operation.

However, as the additional floating area 125c is added between the floating area 125 and the protection junction area 125a, this problem can be greatly alleviated. That is, by adding the additional floating region 125c between the floating region 125 and the protection junction region 125a adjacent to the outermost side of the current sensor transistor ST, the insulation resistance between the two can be increased. According to this structure, even if the additional floating area 125c is connected to the protective junction area 125a, it is possible to prevent the protective junction area 125a from being directly connected to the floating area 125.

This effect is further enhanced by disposing two or more, that is, a plurality of additional floating regions 125c, spaced apart from each other, between the floating region 125 and the protection junction region 125a adjacent to the outermost side, as shown in FIG. 7. I can.

Further, in some embodiments, at least a portion of the power semiconductor transistors PT and at least a portion of the current sensor transistors ST may share a gate capacitance. For example, at least a portion of the power semiconductor transistors PT and at least a portion of the current sensor transistors ST may share the gate electrode 120 with each other.

In more detail, the gate electrode 120 of the power semiconductor transistors PT and the gate electrode 120 of the current sensor transistors ST may be arranged in a stripe type. In this case, the gate electrode 120 of the power semiconductor transistors PT and the gate electrode 120 of the current sensor transistors ST disposed on the same line may be connected to each other across the insulating region IA. In this case, the gate capacitances of the power semiconductor transistors PT of the main cell region MC and the current sensor transistors ST of the sensor region SA may be shared. Accordingly, an effect of substantially increasing the capacitance of the sensor area SA may occur.

In another embodiment, the gate electrode 120 may not be shared in the sensor area SA and the main cell area MC and may be separated from each other. In this case, the gate capacitance is not shared in the sensor area SA and the main cell area MC, but current distribution through the protection resistor Re is still possible in an ESD situation.

According to some embodiments, the structure may be simplified by allocating a partial area of the typical main cell area MC as the sensor area SA. In this case, the well region 110, the drift region 107, the gate electrode 120, and the like can be manufactured through a consistent process in the main cell region MC, the sensor region SA, and the insulating region IA.

The foregoing descriptions have been described on the assumption that the power semiconductor device is an IGBT, but may be applied to a power MOSFET as it is. For example, in the power MOSFET, there is no collector region 128 and a drain electrode may be disposed instead of the collector electrode.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those of ordinary skill in the art will appreciate that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

61: collector terminal
62: gate terminal
64: current sensor terminal
66: Kelvin emitter terminal
67, 68: temperature sensor terminal
69: emitter terminal
100: power semiconductor device
105: semiconductor layer
120: gate electrode
125: floating area
125a: protective junction area
125c: additional floating area
PT: power semiconductor transistor
ST: current sensor transistor

Claims (6)

A semiconductor layer including a main cell region, a sensor region, and an insulating region between the main cell region and the sensor region;
A plurality of power semiconductor transistors formed in the main cell region;
A plurality of current sensor transistors formed in the sensor area; And
A protection resistor formed in the insulating region to connect the emitter electrodes of the plurality of power semiconductor transistors and the emitter electrodes connected to the plurality of current sensor transistors to each other in an abnormal operation situation, and
At least one additional floating region is formed in the semiconductor layer between the floating region in the semiconductor layer adjacent to the outermost current sensor transistor among the plurality of current sensor transistors and the protection resistor,
Power semiconductor device. A plurality of power semiconductor transistors formed in the main cell region of the semiconductor layer;
An emitter terminal connected to the emitter electrodes of the plurality of power semiconductor transistors;
A plurality of current sensor transistors formed in a sensor region of the semiconductor layer to monitor currents of the power semiconductor transistors;
A current sensor terminal connected to the emitter electrodes of the plurality of current sensor transistors;
A gate terminal connected to the gate electrodes of the power semiconductor transistors and the gate electrodes of the plurality of current sensor transistors; And
And a protection resistor formed in an insulating region between the main cell region and the sensor region to connect the emitter terminal and the current sensor terminal to each other in an abnormal operation situation, and
At least one additional floating region is formed in the semiconductor layer between the floating region in the semiconductor layer adjacent to the outermost current sensor transistor among the plurality of current sensor transistors and the protection resistor,
Power semiconductor device. The method according to claim 1 or 2,
The at least one additional floating region includes a plurality of additional floating regions spaced apart from each other in the insulating region. The method according to claim 1 or 2,
The semiconductor layer includes a drift region doped with an impurity of a first conductivity type over the main cell region, the sensor region, and the insulating region,
The floating region and the at least one additional floating region are formed by doping with an impurity of a second conductivity type opposite to the first conductivity type,
The drift region and the additional floating region form a PN diode structure,
Power semiconductor device. The method of claim 4,
The protection resistor includes a protection junction region formed by doping an impurity of a second conductivity type in the semiconductor layer,
The at least one additional floating region is spaced apart between the protection junction region and the floating region in the semiconductor layer.
Power semiconductor device. The method of claim 5,
A part of the drift region is interposed between the protection junction region and the at least one additional floating region and between the floating region and the at least one additional floating region,
Power semiconductor device.

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