KR102321272B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device according to an aspect of the present invention includes a semiconductor layer, at least one trench formed by recessing a predetermined depth into the semiconductor layer from a surface of the semiconductor layer, and the semiconductor at one side of the at least one trench A well region defined in a layer, a floating region defined in the semiconductor layer on the other side of the at least one trench, and a portion formed on a sidewall of the at least one trench, the portion adjacent to the floating region having a thickness adjacent to the well region and a gate insulating layer including a sidewall portion thicker than a thickness of , and a gate electrode layer formed on the gate insulating layer to fill the at least one trench.

Description

Power semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method for manufacturing the same.

A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Such a power semiconductor device is used in a field requiring high power switching, for example, an inverter device. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a power MOSFET, and the like. Such a power semiconductor device is fundamentally required to withstand high voltage, and recently, a high-speed switching operation is additionally required.

Such a semiconductor device operates while electrons injected from a channel and holes injected from a collector flow. However, in the trench gate type power semiconductor device, as the parasitic capacitance between the gate and the collector increases, holes are excessively accumulated in the trench gate, and negative gate charging (NGC) occurs in the gate direction. A displacement current is generated.

In this case, as shown in FIG. 10 , the gate-emitter potential (Vge) momentarily rises during the switching operation and the collector-emitter current (Ice) rises, causing oscillation and/or overshooting of these values. This may lead to operational instability of the door element.

1. Republic of Korea Publication No. 20140057630 (published on May 13, 2014)

An object of the present invention is to provide a power semiconductor device capable of suppressing a negative gate charging phenomenon in order to solve the above problems.

However, these problems are exemplary, and the scope of the present invention is not limited thereto.

A power semiconductor device according to an aspect of the present invention for solving the above problems is formed by recessing a semiconductor layer by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer, and forming a closed loop. a trench; a well region formed in the semiconductor layer inside the at least one trench; a floating region formed in the semiconductor layer outside the at least one trench; and a gate insulation formed on at least a sidewall of the at least one trench. layer, at least one gate electrode layer formed on the gate insulating layer inside the at least one trench and formed to be biased toward the well region, and on the gate insulating layer inside the at least one trench. and at least one source electrode layer spaced apart from the gate electrode layer and formed to be biased toward the floating region.

The power semiconductor device may further include an emitter region in the well region and an emitter electrode layer connected to the well region and the emitter region, and the at least one source electrode layer may be connected to the emitter electrode layer.

According to the power semiconductor device, the gate electrode layer and the source electrode layer may extend in parallel in a depth direction in the at least one trench.

According to the power semiconductor device, the gate insulating layer includes a first portion between the well region and the gate electrode layer and a second portion between the gate electrode layer and the source electrode layer, and the thickness of the second portion is the second portion. It can be thicker than the thickness of 1 part.

According to the power semiconductor device, the gate insulating layer includes a third portion between the bottom of the at least one trench and the gate electrode layer and between the bottom of the at least one trench and the source electrode layer, The thickness may be greater than the thickness of the first portion.

According to the power semiconductor device, the semiconductor layer and the emitter region are doped with an impurity of a first conductivity type, and the well region and the floating region are doped with an impurity of a second conductivity type opposite to the first conductivity type. can be

According to the power semiconductor device, the gate electrode layer and the source electrode layer may be respectively formed in a closed loop along the at least one trench.

In a method of manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems, at least one trench is formed by being recessed by a predetermined depth into the semiconductor layer from the surface of the semiconductor layer, and forming a closed loop. forming a well region in the semiconductor layer inside the at least one trench; forming a floating region in the semiconductor layer outside the at least one trench; forming a gate insulating layer on at least a sidewall of and forming at least one source electrode layer spaced apart from the gate electrode layer and biased toward the floating region on the gate insulating layer inside the trench.

According to the manufacturing method of the power semiconductor device, the forming of the gate insulating layer includes: forming a gate insulating layer filling the inside of the at least one trench; The method may include forming a trench and a second trench biased toward the floating region.

According to the method of manufacturing the power semiconductor device, the forming of the gate electrode layer includes filling the inside of the first trench with the gate electrode layer, and the forming of the source electrode layer includes: the inside of the second trench may include filling in the source electrode layer.

According to the manufacturing method of the power semiconductor device, the gate insulating layer includes a first portion between the well region and the gate electrode layer, a second portion between the gate electrode layer and the source electrode layer, and a bottom of the at least one trench and a third portion between the gate electrode layer and between the bottom of the at least one trench and the source electrode layer; It can be thicker than the thickness of 1 part.

The method of manufacturing the power semiconductor device further includes: forming an emitter region in the well region; and forming an emitter electrode layer connected to the well region and the emitter region; and the at least one source electrode layer. may be connected to the emitter electrode layer.

According to the method of manufacturing the power semiconductor device, the gate electrode layer and the source electrode layer may extend in parallel in a depth direction in the at least one trench.

According to the power semiconductor device and the manufacturing method thereof according to the embodiment of the present invention made as described above, it is possible to suppress the operation instability due to the parasitic capacitance between the gate-collector and increase the reliability of the device.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic plan view showing a power semiconductor device according to an embodiment of the present invention.
2 is a circuit diagram showing a power semiconductor device according to an embodiment of the present invention.
3 is a circuit diagram illustrating a part of the power semiconductor device of FIG. 2 .
4 is a cross-sectional view showing a power semiconductor device according to an embodiment of the present invention.
FIG. 5 is a plan view taken from the VV plane of the power semiconductor device of FIG. 4 .
6 to 9 are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
10 is a graph showing an operating wave form due to a negative gate charging (NGC) phenomenon of a conventional power semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform In addition, in the drawings for convenience of description, the size of at least some of the components may be exaggerated or reduced. In the drawings, like reference numerals refer to like elements.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the sake of illustration, and are therefore provided to illustrate the general structures of the present invention.

Like reference signs indicate like elements. It will be understood that when referring to one configuration as being on another configuration, such as a layer, region, or substrate, it may also be in a trench immediately above the other configuration or other intervening configurations in between. On the other hand, when referring to one configuration as being “directly on” of another, it is understood that intervening configurations do not exist.

1 is a schematic plan view showing a power semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a power semiconductor device according to an embodiment of the present invention, and FIG. 3 is a power semiconductor device of FIG. A circuit diagram showing some of it.

Referring to FIG. 1 , the power semiconductor device 100 may be implemented using a semiconductor layer 105 including a main cell region MC and a sensor region SA. The power semiconductor device 100 may include a wafer, chip, or die structure.

A plurality of power semiconductor transistors (PT of FIG. 3 ) may be formed in the main cell region MC. A plurality of current sensor transistors (ST of FIG. 3 ) may be formed in the sensor area SA to monitor currents of the power semiconductor transistors PT.

For example, the two power semiconductor transistors PT and the current sensor transistors ST may include an insulated gate bipolar transistor (IGBT) structure or a power MOSFET structure. The IGBT may include a gate electrode, an emitter electrode, and a collector electrode. 2 to 3 , an IGBT will be described as an example of the power semiconductor device 100 .

1 to 3 , the power semiconductor device 100 may include a plurality of terminals for connection to the outside.

For example, the power semiconductor device 100 includes an emitter terminal 69 connected to the emitter electrode of the power semiconductor transistors PT, and a Kelvin emitter connected to the Kelvin emitter electrode of the power semiconductor transistors PT. terminal 66, a current sensor terminal 64 connected with an emitter electrode of the current sensor transistors ST for monitoring a current, a gate electrode of the power semiconductor transistors PT, and the current sensor transistors ST. The gate terminal 62 connected to the gate electrode, the temperature sensor terminals 67 and 68 connected to the temperature sensor TC for monitoring the temperature and/or the power semiconductor transistors PT and the current sensor transistors ST ) may include a collector terminal 61 connected to the collector electrode.

In FIG. 2 , the collector terminal 61 may be formed on the rear surface of the semiconductor layer 105 in FIG. 1 .

The temperature sensor TC may include a junction diode connected to the temperature sensor terminals 67 and 68 . The junction diode may include a junction structure of at least one n-type impurity region and at least one p-type impurity region, for example, a P-N junction structure, a P-N-P junction structure, an N-P-N junction structure, or the like.

Although this structure exemplarily describes a structure in which the temperature sensor TC is built in the power semiconductor device 100 , the temperature sensor TC may be omitted in a modified example of this embodiment.

The power semiconductor transistor PT is connected between the emitter terminal 69 and the collector terminal 61 , and the current sensor transistor ST is connected between the current sensor terminal 64 and the collector terminal 61 , the power semiconductor transistor PT ) and some parallel connections. The gate electrode of the current sensor transistor ST and the gate electrode of the power semiconductor transistor PT are commonly connected to the gate terminal 62 via a predetermined resistor.

The current sensor transistor ST has a structure substantially the same as that of the power semiconductor transistor PT, but may be reduced by a predetermined ratio. Accordingly, the output current of the power semiconductor transistor PT may be indirectly monitored by monitoring the output current of the current sensor transistor ST.

4 is a cross-sectional view showing the power semiconductor device 100 according to an embodiment of the present invention, and FIG. 5 is a plan view taken along the V-V plane of the power semiconductor device of FIG. 4 .

4 and 5 , the semiconductor layer 105 may refer to one or more semiconductor material layers, for example, a portion of a semiconductor substrate and/or one or multiple epitaxial layers. may refer to For example, the semiconductor layer 105 may include a drift region 107 and a well region 110 .

Furthermore, the semiconductor layer 105 may further include an emitter region 112 in the well region 110 . Here, the emitter region 112 may be referred to as a source region.

The semiconductor layer 105 may further include a floating region 125 in a portion between the gate electrode layers 120 extending under the gate electrode layer 120 . The floating region 125 may be formed to be deeper than the bottom of the gate electrode layer 120 . The floating region 125 may be formed in the semiconductor layer 105 opposite the well region 110 between adjacent two of the power semiconductor transistors PT. Accordingly, when viewed in cross section, the well region 110 and the floating region 125 may be alternately formed between the gate electrodes 120 .

For example, the drift region 107 and the emitter region 112 may have a first conductivity type, and the well region 110 and the floating region 125 may have a second conductivity type. The first conductivity type and the second conductivity type have opposite conductivity types, but may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

The drift region 107 may be provided as an epitaxial layer of a first conductivity type, and the well region 110 may be formed by doping this epitaxial layer with an impurity of a second conductivity type or as an epitaxial layer of a second conductivity type. can be formed The source region 112 may be formed by doping an impurity of the first conductivity type in the well region 110 or by additionally forming an epitaxial layer of the first conductivity type.

Furthermore, when the power semiconductor device 100 is an IGBT, a collector region (not shown) may be provided under the drift region 107, and a collector electrode layer (not shown) may be provided under the collector region to be connected to the collector region. . For example, the collector region may be provided as an epitaxial layer having the second conductivity type under the drift region 107 .

The at least one trench 116 may be formed by recessing a predetermined depth into the semiconductor layer 105 from the surface of the semiconductor layer 105 . For example, trench 116 may form a closed loop when viewed in plan view. The loop may have various shapes, such as a donut shape and a square shape.

The number of trenches 116 may be appropriately selected according to the performance of the power semiconductor device 100 and does not limit the scope of this embodiment. For example, the plurality of trenches 116 may be disposed in a matrix structure.

Furthermore, the trenches 116 may have their edges, for example, bottom edges, rounded to suppress the concentration of the electric field.

According to this structure, the well region 110 may be formed in the semiconductor layer 105 inside the trench 116 , and the floating region 125 may be formed in the semiconductor layer 105 outside the trench 116 . .

The gate insulating layer 118 may be formed on a sidewall of the at least one trench 116 . For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 .

The gate electrode layer 120 may be formed on the gate insulating layer 118 in at least one trench 116 formed in the semiconductor layer 105 . For example, the gate electrode layer 120 may be formed on the gate insulating layer 118 inside the trench 116 , but may be formed to be biased toward the well region 110 .

Furthermore, the source electrode layer 122 may be formed on the gate insulating layer 118 inside the trench 116 , spaced apart from the gate electrode layer 120 , and inclined toward the floating region 125 .

More specifically, the gate insulating layer 118 includes a first portion 118a between the well region 110 and the gate electrode layer 120 , and a second portion 118b between the gate electrode layer 120 and the source electrode layer 122 . ) may be included. In some embodiments, the first portion 118a may be understood to include a portion formed between the source electrode layer 122 and the floating region 125 .

Furthermore, the gate insulating layer 118 may further include a third portion 118c between the bottom of the trench 116 and the gate electrode layer 120 and between the bottom of the trench 116 and the source electrode layer 122 . In some embodiments, the third portion 118c may be interpreted as including the gate insulating layer 118 between the second portion 118b and the bottom of the trench 116 .

The first portion 118a of the gate insulating layer 118 may have a predetermined thickness according to the operating voltage because it is related to the operating voltage for turning on and off the channel in the well region 110 . On the other hand, the second portion 118b and the third portion 118c of the gate insulating layer 118 need to be relatively thick because they are involved in the withstand voltage of the device and the gate-collector capacitance (Cgc).

Accordingly, the thickness of the second portion 118b and the third portion 118c of the gate insulating layer 118 may be greater than the thickness of the first portion 118a. Since the third portion 118c has little to do with channel formation and has a large degree of freedom in its thickness, it can be sufficiently thickened. For example, the thickness of the second portion 118b and the third portion 118c of the gate insulating layer 118 may be at least five times greater than the thickness of the first portion 118a.

In this embodiment, the gate electrode layer 120 and the source electrode layer 122 may be formed side by side in the depth direction inside the trench 116 . For example, the gate electrode layer 120 and the source electrode layer 122 may be formed to have the same depth and parallel to each other in the trench 116 .

Also, the gate electrode layer 120 and the source electrode layer 122 may be respectively formed in a closed loop along the trench 116 . For example, as shown in FIG. 5 , the gate electrode layer 120 is formed in the trench 116 in a shape surrounding the well region 110 , and the source electrode layer 122 surrounds the gate electrode layer 120 . shape may be formed in the trench 116 .

Meanwhile, the emitter electrode layer 145 may be formed on the emitter region 112 to be connected to the emitter region 112 and the well region 110 . An insulating layer 130 may be interposed between the semiconductor layer 105 and the emitter electrode layer 145 .

In this embodiment, the gate electrode layer 122 and the source electrode layer 122 may be separated from each other and connected to different potentials. For example, the source electrode layer 122 may be connected to the emitter electrode layer 145 . For example, the emitter electrode layer 145 may be grounded, and in this case, the source electrode layer 122 may also be grounded.

According to this embodiment, by disposing the source electrode layer 122 connected to the emitter electrode layer 145 in the trench 116 adjacent to the floating region 125 , the gate-collector capacitance Cgc in the floating region 125 can be significantly lowered. can Furthermore, the third portion 118c of the thick gate insulating layer 118 may also contribute to lowering this gate-collector capacitance.

Accordingly, the gate-collector capacitance Cgc is reduced, so that the negative gate charging (NGC) phenomenon can be largely suppressed, and the displacement current through the floating region 125 can be suppressed.

In this embodiment, the number of the trench 116 , the gate electrode layer 120 , and the source electrode layer 122 may be appropriately selected according to the operating specifications of the power semiconductor device 100 , and the scope of this embodiment is not limited.

Although the above descriptions have been made on the assumption that the power semiconductor device is an IGBT, it may be applied to a power MOSFET as it is. For example, in a power MOSFET, there is no collector region) and a drain electrode may be disposed instead of a collector electrode.

6 to 9 are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 6 , at least one trench 116 is formed to be recessed by a predetermined depth into the semiconductor layer 105 from the surface of the semiconductor layer 105 , and the semiconductor layer 105 on one side of the trench 116 . A well region 110 may be defined in the region, and a floating region 125 may be defined in the semiconductor layer 116 on the other side of the trench 116 . The emitter region 112 may be confined within the well region 110 .

For example, the trench 116 has a closed loop shape, the well region 110 is formed in the semiconductor layer 105 inside the trench 116 , and the floating region 125 is formed outside the trench 116 . It may be formed on the semiconductor layer 105 .

For example, in the trench 116 , a photoresist pattern is formed in the semiconductor layer 105 in which the drift region 107 , the well region 110 , and the floating region 125 are formed using a photolithography technique, and the photoresist It may be formed by etching the semiconductor layer 105 using the pattern as an etch protection layer.

7 to 9 , a gate insulating layer 118 is formed on at least a sidewall of the trench 116 , and on the gate insulating layer 118 inside the trench 116 , the well region 110 direction forming at least one gate electrode layer 120 biased toward An electrode layer 122 may be formed.

For example, as shown in FIG. 7 , the gate insulating layer 118 filling the inside of the trench 116 may be formed.

Subsequently, as shown in FIG. 8 , a first trench GT1 biased toward the well region 110 and a second trench GT2 biased toward the floating region 125 may be formed in the gate insulating layer 118 . have. The first trench GT1 and the second trench GT2 may be formed to be spaced apart from each other by a predetermined depth inside the trench 116 .

Subsequently, as shown in FIG. 9 , the inside of the first trench GT1 may be filled with the gate electrode layer 120 and the inside of the second trench GT2 may be filled with the source electrode layer 122 . In some embodiments, the process steps may be reduced by simultaneously forming the first trench GT1 and the second trench GT2 , and simultaneously forming the gate electrode layer 120 and the source electrode layer 122 .

For example, the gate electrode layer 120 and the source electrode layer 122 may include metal or doped polysilicon.

Subsequently, the insulating layer 130 may be formed, and the emitter electrode layer 145 may be formed to be connected to the emitter region 112 and the well region 110 . For example, the emitter electrode layer 145 may be formed by forming a conductive layer and then patterning it. Furthermore, the emitter electrode layer 145 may be further connected to the source electrode layer 122 . For example, the source electrode layer 122 and the emitter electrode layer 145 may be connected to each other through a contact plug penetrating the insulating layer 130 .

According to the above-described manufacturing method, by arranging the source electrode layer 122 in the trench 116 adjacent to the floating region 125 using an existing process, the gate-collector capacitance (Cgc) is reduced to achieve negative gate charging (NGC). shape can be suppressed.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: power semiconductor device
105: semiconductor layer
107: drift zone
110: well area
112: emitter area
118: gate insulating layer
120: gate electrode layer
122: source electrode layer
125: floating area
130: insulating layer
145: emitter electrode layer

Claims (13)

semiconductor layer;
at least one trench recessed by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer and forming a closed loop;
a well region formed in the semiconductor layer inside the at least one trench;
a floating region formed in the semiconductor layer outside the at least one trench;
a gate insulating layer formed on at least a sidewall of the at least one trench;
at least one gate electrode layer formed on the gate insulating layer inside the at least one trench, the gate electrode layer being biased toward the well region; and
at least one source electrode layer formed on the gate insulating layer inside the at least one trench, the at least one source electrode layer being spaced apart from the gate electrode layer and biased toward the floating region;
In the at least one trench, the gate electrode layer and the source electrode layer extend in parallel in a depth direction;
The gate insulating layer,
a first portion between the well region and the gate electrode layer;
a second portion between the gate electrode layer and the source electrode layer; and
a third portion between the bottom of the at least one trench and the gate electrode layer and between the bottom of the at least one trench and the source electrode layer;
The thickness of the second part is thicker than the thickness of the first part,
The thickness of the third part is thicker than the thickness of the first part,
the floating region entirely surrounds a bottom portion of the third portion of the gate insulating layer;
power semiconductor devices. The method of claim 1,
an emitter region within the well region; and
an emitter electrode layer connected to the well region and the emitter region;
the at least one source electrode layer is connected to the emitter electrode layer;
power semiconductor devices. delete delete delete 3. The method of claim 2,
the semiconductor layer and the emitter region are doped with an impurity of a first conductivity type;
the well region and the floating region are doped with an impurity of a second conductivity type opposite to the first conductivity type;
power semiconductor devices. The method of claim 1,
wherein the gate electrode layer and the source electrode layer are each formed in a closed loop along the at least one trench;
power semiconductor devices. forming at least one trench recessed by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer and forming a closed loop;
forming a well region in the semiconductor layer inside the at least one trench;
forming a floating region in the semiconductor layer outside the at least one trench;
forming a gate insulating layer on at least sidewalls of the at least one trench;
forming at least one gate electrode layer biased toward the well region on the gate insulating layer inside the at least one trench; and
forming at least one source electrode layer on the gate insulating layer inside the at least one trench, the at least one source electrode layer being spaced apart from the gate electrode layer and biased toward the floating region;
Forming the gate insulating layer comprises:
forming a gate insulating layer filling the inside of the at least one trench; and
forming a first trench biased toward the well region and a second trench biased toward the floating region in the gate insulating layer;
The forming of the gate electrode layer includes filling the inside of the first trench with the gate electrode layer,
The forming of the source electrode layer includes filling the inside of the second trench with the source electrode layer,
In the at least one trench, the gate electrode layer and the source electrode layer extend in parallel in a depth direction;
The gate insulating layer,
a first portion between the well region and the gate electrode layer;
a second portion between the gate electrode layer and the source electrode layer; and
a third portion between the bottom of the at least one trench and the gate electrode layer and between the bottom of the at least one trench and the source electrode layer;
The thickness of the second part is thicker than the thickness of the first part,
The thickness of the third part is thicker than the thickness of the first part,
the floating region entirely surrounds a bottom portion of the third portion of the gate insulating layer;
A method of manufacturing a power semiconductor device. delete delete delete 9. The method of claim 8,
forming an emitter region in the well region; and
Forming an emitter electrode layer connected to the well region and the emitter region; further comprising,
the at least one source electrode layer is connected to the emitter electrode layer;
A method of manufacturing a power semiconductor device. delete

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