JP4910889B2 - Semiconductor device - Google Patents

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JP4910889B2
JP4910889B2 JP2007145083A JP2007145083A JP4910889B2 JP 4910889 B2 JP4910889 B2 JP 4910889B2 JP 2007145083 A JP2007145083 A JP 2007145083A JP 2007145083 A JP2007145083 A JP 2007145083A JP 4910889 B2 JP4910889 B2 JP 4910889B2
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semiconductor device
semiconductor chip
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幹昌 鈴木
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Denso Corp
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、対向する例えば２枚の放熱板の間に半導体チップを設けると共に、前記半導体チップ及び前記放熱板を樹脂でモールドしてなる半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor chip is provided between, for example, two heat sinks facing each other, and the semiconductor chip and the heat sink are molded with a resin.

半導体チップの両面から放熱を行う構成として、特許文献１に記載された半導体装置が知られている。この半導体装置は、２枚の放熱板の間にＩＧＢＴチップとＦＷＤチップとを設けると共に、これらチップ及び放熱板を樹脂でモールドして構成したパワー素子パッケージである。
特許第３５２５８３２号公報 As a configuration for radiating heat from both sides of a semiconductor chip, a semiconductor device described in Patent Document 1 is known. This semiconductor device is a power element package in which an IGBT chip and an FWD chip are provided between two heat radiating plates, and these chips and the heat radiating plates are molded with a resin.
Japanese Patent No. 3525832

上記構成の半導体装置の場合、ワイヤボンディング用の隙間を確保するために、ＩＧＢＴチップ及びＦＷＤチップの各一方の面と一方の放熱板との間にそれぞれスペーサを介在させている。ＩＧＢＴチップとＦＷＤチップは、製造するウエハが異なるため、厚み寸法が異なる。半導体装置の２枚の放熱板は、冷却器と良好に接触させるために、平行に構成する必要がある。   In the case of the semiconductor device having the above-described configuration, a spacer is interposed between each surface of the IGBT chip and the FWD chip and one heat sink in order to secure a gap for wire bonding. The IGBT chip and the FWD chip have different thickness dimensions because different wafers are manufactured. The two heat sinks of the semiconductor device need to be configured in parallel to make good contact with the cooler.

このため、ＩＧＢＴチップの厚み寸法をｔ１、ＦＷＤチップの厚み寸法をｔ２、ＩＧＢＴチップ用のスペーサの厚み寸法をｔ３、ＦＷＤチップ用のスペーサの厚み寸法をｔ４としたとき、ｔ１＋ｔ３＝ｔ２＋ｔ４が成立するように、各部品の寸法を管理しなければならなかった。このため、部品点数が多くなり、製造工程が複雑になるという問題点があった。   Therefore, when the thickness dimension of the IGBT chip is t1, the thickness dimension of the FWD chip is t2, the thickness dimension of the spacer for the IGBT chip is t3, and the thickness dimension of the spacer for the FWD chip is t4, t1 + t3 = t2 + t4 is established. So we had to manage the dimensions of each part. For this reason, there are problems that the number of parts increases and the manufacturing process becomes complicated.

尚、上記特許文献１の構成は、１個のＩＧＢＴチップと１個のＦＷＤチップを１対の放熱板で挟んで樹脂モールドする構造であるが、例えば２ｉｎ１構造の半導体装置の場合、２個のＩＧＢＴチップと２個のＦＷＤチップ（インバータ回路を構成する上相スイッチング素子と下相スイッチング素子）を対向する放熱板で挟んで樹脂モールドする構造であるため、部品点数がより一層多くなり、製造工程がより一層複雑になる。更に、６ｉｎ１構造の半導体装置の場合には、６個のＩＧＢＴチップと６個のＦＷＤチップ（インバータ回路を構成する３相分の上相スイッチング素子及び下相スイッチング素子）を対向する放熱板で挟んで樹脂モールドする構造であるため、部品点数が更に一層多くなり、製造工程が更に一層複雑になる。   The configuration of Patent Document 1 is a structure in which one IGBT chip and one FWD chip are sandwiched between a pair of heat sinks and resin-molded. For example, in the case of a 2-in-1 semiconductor device, Because the structure is resin-molded with an IGBT chip and two FWD chips (an upper-phase switching element and a lower-phase switching element constituting the inverter circuit) sandwiched between opposing heat sinks, the number of parts is further increased, and the manufacturing process Becomes even more complex. Further, in the case of a 6-in-1 semiconductor device, six IGBT chips and six FWD chips (the upper-phase switching element and the lower-phase switching element for three phases constituting the inverter circuit) are sandwiched between opposing heat sinks. Because of the resin molding structure, the number of parts is further increased and the manufacturing process is further complicated.

そこで、本発明の目的は、部品点数を削減すると共に、製造工程を簡単化することができ、また、寄生インダクタンスを低減することができる半導体装置を提供することにある。   Accordingly, an object of the present invention is to provide a semiconductor device that can reduce the number of components, simplify the manufacturing process, and reduce parasitic inductance.

請求項１の発明によれば、半導体チップを、ＦＷＤを内蔵したＩＧＢＴチップで構成したので、部品点数を削減すると共に、製造工程を簡単化することができる。
さらに、請求項１の発明によれば、対向する放熱板の間に半導体チップを複数個設けたので、例えば２ｉｎ１構造の半導体装置や６ｉｎ１構造の半導体装置などを容易に製造することができ、また、寄生インダクタンスを低減することができる。
加えて、請求項１の発明によれば、前記複数個の半導体チップは、同一のウエハから製造されたものであるように構成したので、複数個の半導体チップを挟む２枚の放熱板の平行度を高めることができる。 According to the first aspect of the present invention, since the semiconductor chip is composed of an IGBT chip with a built-in FWD, the number of parts can be reduced and the manufacturing process can be simplified.
Furthermore, according to the invention of claim 1, since a plurality of semiconductor chips are provided between the opposing heat sinks, for example, a semiconductor device having a 2 in 1 structure, a semiconductor device having a 6 in 1 structure, or the like can be easily manufactured. Inductance can be reduced.
In addition, according to the first aspect of the present invention, since the plurality of semiconductor chips are manufactured from the same wafer, the two heat sinks sandwiching the plurality of semiconductor chips are arranged in parallel. The degree can be increased.

請求項４の発明によれば、前記複数個の半導体チップは、同一のウエハの中の近接した部分から製造されたものであるように構成したので、複数個の半導体チップを挟む２枚の放熱板の平行度をより一層高めることができる。
According to a fourth aspect of the present invention, since the plurality of semiconductor chips are manufactured from adjacent parts in the same wafer, two heat dissipations sandwiching the plurality of semiconductor chips are performed. The parallelism of the plate can be further increased.

以下、本発明の第１の実施例について、図１を参照しながら説明する。図１は、本実施例の半導体装置１の縦断面図である。本実施例の半導体装置１は、パワー素子パッケージであり、図１に示すように、対向する例えば２枚の放熱板（ヒートシンク）２、３と、これら２枚の放熱板２、３の間に設けられた半導体チップ４と、この半導体チップ４及び放熱板２、３をモールドする樹脂５とから構成されている。   A first embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a longitudinal sectional view of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 of this embodiment is a power element package, and as shown in FIG. 1, for example, between two opposing heat sinks (heat sinks) 2 and 3 and between the two heat sinks 2 and 3. The semiconductor chip 4 is provided and a resin 5 that molds the semiconductor chip 4 and the heat sinks 2 and 3.

放熱板２、３は、例えばアルミや銅等の金属板材で構成されている。放熱板２は、半導体チップ４よりも大きい部材であり、その上面のほぼ中央部に半導体チップ４が半田６付けされている。放熱板３は、半導体チップ４よりも少し小さい程度の大きさの部材であり、半導体チップ４の上面に半田６付けされている。これにより、半導体チップ４の両面に放熱板２、３が取り付けられる構成となっている。   The heat sinks 2 and 3 are made of a metal plate material such as aluminum or copper. The heat radiating plate 2 is a member larger than the semiconductor chip 4, and the semiconductor chip 4 is soldered to the center of the upper surface thereof. The heat radiating plate 3 is a member having a size slightly smaller than the semiconductor chip 4 and is soldered to the upper surface of the semiconductor chip 4. Thus, the heat radiation plates 2 and 3 are attached to both surfaces of the semiconductor chip 4.

上記半導体チップ４は、ＦＷＤを内蔵したＩＧＢＴチップで構成されている。半導体チップ４の下面には、ＩＧＢＴのコレクタ（ＦＷＤのカソード）のパッドが形成されており、このパッドは放熱板２に接続されている。半導体チップ４の上面のうちの放熱板３が半田付けされた部分には、ＩＧＢＴのエミッタ（ＦＷＤのアノード）のパッドが形成されており、このパッドは放熱板３に接続されている。   The semiconductor chip 4 is composed of an IGBT chip with a built-in FWD. An IGBT collector (FWD cathode) pad is formed on the lower surface of the semiconductor chip 4, and this pad is connected to the heat sink 2. An IGBT emitter (FWD anode) pad is formed on a portion of the upper surface of the semiconductor chip 4 where the heat sink 3 is soldered, and this pad is connected to the heat sink 3.

半導体チップ４の上面のうちの放熱板３が半田付けされていない部分（図１中の左端部）には、ＩＧＢＴのゲートのパッドが形成されており、このパッドはワイヤ７ボンディングにより制御用端子（リードフレーム）８に接続されている。   A portion of the upper surface of the semiconductor chip 4 where the heat radiating plate 3 is not soldered (left end portion in FIG. 1) is formed with a gate pad of an IGBT, and this pad is a control terminal by wire 7 bonding. (Lead frame) 8 is connected.

そして、半導体チップ４、放熱板２、３、制御用端子８は、樹脂５でモールドされている。この場合、放熱板２の下面及び放熱板３の上面は、モールド樹脂５から露出するように構成されている。制御用端子８の左端部は、モールド樹脂５から露出（突出）するように構成されている。   The semiconductor chip 4, the heat dissipation plates 2 and 3, and the control terminal 8 are molded with resin 5. In this case, the lower surface of the heat radiating plate 2 and the upper surface of the heat radiating plate 3 are configured to be exposed from the mold resin 5. The left end portion of the control terminal 8 is configured to be exposed (projected) from the mold resin 5.

このような構成の本実施例によれば、半導体チップ４を、ＦＷＤを内蔵したＩＧＢＴチップで構成したので、２枚の放熱板２、３の間に挟むチップの個数を１個とすることが可能となるから、従来構成とは異なり、スペーサの個数を減らすことができる、特に、本実施例では、スペーサをなくすように構成した。これにより、部品点数を削減することができると共に、製造工程を簡単化することができる。   According to the present embodiment having such a configuration, since the semiconductor chip 4 is composed of an IGBT chip having a built-in FWD, the number of chips sandwiched between the two heat sinks 2 and 3 can be set to one. Therefore, unlike the conventional configuration, the number of spacers can be reduced. In particular, in this embodiment, the spacer is eliminated. Thereby, the number of parts can be reduced, and the manufacturing process can be simplified.

図２は、本発明の第２の実施例を示すものである。尚、第１の実施例と同一構成には、同一符号を付している。この第２の実施例においては、図２に示すように、半導体チップ４の上面に取り付ける放熱板９として、半導体チップ４の下面に取り付ける放熱板２とほぼ同じ大きさのものを用いるように構成した。   FIG. 2 shows a second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals. In the second embodiment, as shown in FIG. 2, a heat sink 9 attached to the upper surface of the semiconductor chip 4 is used so as to have substantially the same size as the heat sink 2 attached to the lower surface of the semiconductor chip 4. did.

上記放熱板９の下面のほぼ中央部には、第１の実施例の放熱板３とほぼ同じ大きさの凸部９ａが形成されており、この凸部９ａの下面を半導体チップ４の上面に半田６付けしている。上述した以外の第２の実施例の構成は、第１の実施例の構成と同じ構成となっている。   A convex portion 9a having substantially the same size as that of the heat radiating plate 3 of the first embodiment is formed substantially at the center of the lower surface of the heat radiating plate 9. The lower surface of the convex portion 9a is formed on the upper surface of the semiconductor chip 4. Solder 6 is attached. The configuration of the second embodiment other than that described above is the same as the configuration of the first embodiment.

従って、第２の実施例においても、第１の実施例とほぼ同じ作用効果を得ることができる。特に、第２の実施例によれば、半導体チップ４の上面側の放熱板９の放熱面積を、下面側の放熱板２の放熱面積とほぼ同じになるように構成したので、放熱性能を高くすることができる。尚、放熱板９に凸部９ａを形成する理由は、半導体チップ４のゲートパッドにワイヤボンディングを実行するための高さ(隙間)を確保する必要があるためである。   Therefore, in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, according to the second embodiment, since the heat radiation area of the heat sink 9 on the upper surface side of the semiconductor chip 4 is configured to be substantially the same as the heat radiation area of the heat sink 2 on the lower surface side, the heat radiation performance is improved. can do. The reason why the protrusion 9 a is formed on the heat sink 9 is that it is necessary to secure a height (gap) for performing wire bonding on the gate pad of the semiconductor chip 4.

また、上記第２の実施例では、放熱板９に凸部９ａを形成したが、これに代えて、放熱板９に凸部９ａを形成することを止めて、平板状の放熱板の下面と半導体チップ４の上面との間にスペーサ（凸部９ａとほぼ同じ大きさ且つほぼ同じ厚さのスペーサ）を介装するように構成しても良い。   Moreover, in the said 2nd Example, although the convex part 9a was formed in the heat sink 9, it replaced with this and stopped forming the convex part 9a in the heat sink 9, and the lower surface of a flat plate-shaped heat sink and A spacer (a spacer having substantially the same size and the same thickness as that of the convex portion 9a) may be interposed between the upper surface of the semiconductor chip 4 and the semiconductor chip 4.

図３及び図４は、本発明の第３の実施例を示すものである。尚、第１の実施例と同一構成には、同一符号を付している。この第３の実施例においては、図３に示すように、対向する例えば３枚の放熱板２、３、３の間に、複数である例えば２個の半導体チップ４を設けるように構成した。２個の半導体チップ４は、それぞれ第１の実施例の半導体チップ４と同じ構成の半導体チップであり、ＦＷＤを内蔵したＩＧＢＴチップである。   3 and 4 show a third embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals. In the third embodiment, as shown in FIG. 3, a plurality of, for example, two semiconductor chips 4 are provided between, for example, the three heat sinks 2, 3, 3 facing each other. Each of the two semiconductor chips 4 is a semiconductor chip having the same configuration as the semiconductor chip 4 of the first embodiment, and is an IGBT chip with a built-in FWD.

上記構成の場合、放熱板２の上面に２個の半導体チップ４を並べて半田６付けし、各半導体チップ４の上面に放熱板３、３を半田６付けしている。そして、２個の半導体チップ４の上面のうちの放熱板３、３が半田付けされていない部分には、ＩＧＢＴのゲートのパッドが形成されており、このパッドはワイヤ７ボンディングにより制御用端子（リードフレーム）８、８に接続されている。   In the case of the above configuration, two semiconductor chips 4 are arranged on the upper surface of the heat radiating plate 2 and soldered 6, and the heat radiating plates 3 and 3 are soldered 6 on the upper surface of each semiconductor chip 4. An IGBT gate pad is formed on a portion of the upper surface of the two semiconductor chips 4 where the heat sinks 3 and 3 are not soldered, and this pad is connected to a control terminal (wire 7 bonding). Lead frames) 8 and 8.

更に、半導体チップ４、４、放熱板２、３、３、制御用端子８、８は、樹脂５でモールドされている。この場合、放熱板２の下面、放熱板３、３の上面、制御用端子８の左端部、制御用端子８の右端部は、モールド樹脂５から露出するように構成されている。尚、２個の半導体チップ４、４としては、同一のウエハから製造されたもの、即ち、即ち、厚み寸法がほぼ等しいものを用いるように構成されている。   Further, the semiconductor chips 4 and 4, the heat sinks 2, 3 and 3, and the control terminals 8 and 8 are molded with a resin 5. In this case, the lower surface of the radiator plate 2, the upper surfaces of the radiator plates 3 and 3, the left end portion of the control terminal 8, and the right end portion of the control terminal 8 are configured to be exposed from the mold resin 5. The two semiconductor chips 4 and 4 are configured so as to be manufactured from the same wafer, that is, those having substantially the same thickness dimension.

また、図４の等価回路に示すように、上記２個の半導体チップ４のＩＧＢＴ１０及びＦＷＤ１１は、並列接続されている。この場合、２個のＩＧＢＴ１０のコレクタ（ＦＷＤ１１のカソード）の共通接続点（即ち、端子Ａ１）が、放熱板２に対応し、２個のＩＧＢＴ１０のエミッタ（ＦＷＤ１１のアノード）の共通接続点（即ち、端子Ａ２）が、放熱板３、３に対応している。２個のＩＧＢＴ１０のゲートの端子Ａ３、Ａ４が、制御用端子８、８に対応している。   Further, as shown in the equivalent circuit of FIG. 4, the IGBT 10 and the FWD 11 of the two semiconductor chips 4 are connected in parallel. In this case, the common connection point (that is, the terminal A1) of the collectors of the two IGBTs 10 (the cathodes of the FWD 11) corresponds to the heat sink 2, and the common connection point of the emitters of the two IGBTs 10 (the anodes of the FWDs 11). , Terminal A2) corresponds to the heat sinks 3,3. The gate terminals A3 and A4 of the two IGBTs 10 correspond to the control terminals 8 and 8, respectively.

尚、上述した以外の第３の実施例の構成は、第１の実施例の構成と同じ構成となっている。従って、第３の実施例においても、第１の実施例とほぼ同じ作用効果を得ることができる。特に、第３の実施例によれば、樹脂モールドした半導体装置１（即ち、いわゆるパワーカード）の中で、２個のＦＷＤ内蔵ＩＢＧＴチップ（半導体チップ）４を並列接続する構成であるので、接続配線による寄生インダクダンスを大幅に低減することができる。ちなみに、ＩＢＧＴチップとＦＷＤチップを各１個内蔵し樹脂モールドした半導体装置（特許文献１参照）を、２個並列接続するように構成すると、接続配線によりかなり大きな寄生インダクダンスが発生してしまう。   The configuration of the third embodiment other than that described above is the same as that of the first embodiment. Accordingly, in the third embodiment, substantially the same operational effects as in the first embodiment can be obtained. In particular, according to the third embodiment, two FWD built-in IBGT chips (semiconductor chips) 4 are connected in parallel in the resin-molded semiconductor device 1 (that is, so-called power card). Parasitic inductance due to wiring can be greatly reduced. Incidentally, if two IBGT chips and one FWD chip are embedded and resin-molded semiconductor devices (see Patent Document 1) are connected in parallel, a considerably large parasitic inductance is generated by the connection wiring.

また、上記第３の実施例では、２個の半導体チップ４、４として、同一のウエハから製造されたものを用いるように構成したので、２個の半導体チップ４、４を挟む対向する３枚の放熱板２、３、３の平行度を高めることができる。   In the third embodiment, since the two semiconductor chips 4 and 4 are manufactured from the same wafer, the three semiconductor chips 4 and 4 facing each other sandwiching the two semiconductor chips 4 and 4 are used. The parallelism of the heat sinks 2, 3, and 3 can be increased.

尚、上記第３の実施例においては、２個の半導体チップ４、４として、同一のウエハから製造されたものを用いるように構成したが、これに代えて、２個の半導体チップ４、４として、同一のウエハの中の近接した部分から製造されたものを用いるように構成しても良い。   In the third embodiment, the two semiconductor chips 4 and 4 are manufactured from the same wafer. Instead, the two semiconductor chips 4 and 4 are used. As another example, a structure manufactured from a close part of the same wafer may be used.

図５は、本発明の第４の実施例を示すものである。尚、第３の実施例と同一構成には、同一符号を付している。この第４の実施例においては、図５に示すように、２個の半導体チップ４、４の上側に取り付ける放熱板１２を、下側の放熱板２とほぼ同じ大きさの１枚の放熱板で構成している。この放熱板１２の下面における２個の半導体チップ４、４と対応する部位に、第３の実施例の放熱板３、３とほぼ同じ大きさの凸部１２ａ、１２ａを設け、これら凸部１２ａ、１２ａを２個の半導体チップ４、４の上面に半田付けしている。   FIG. 5 shows a fourth embodiment of the present invention. The same components as those in the third embodiment are denoted by the same reference numerals. In the fourth embodiment, as shown in FIG. 5, the heat sink 12 attached to the upper side of the two semiconductor chips 4 and 4 is a single heat sink having substantially the same size as the lower heat sink 2. It consists of. Protrusions 12a and 12a having substantially the same size as the heat sinks 3 and 3 of the third embodiment are provided on the lower surface of the heat sink 12 at positions corresponding to the two semiconductor chips 4 and 4. , 12a are soldered to the upper surfaces of the two semiconductor chips 4,4.

尚、上述した以外の第４の実施例の構成は、第３の実施例の構成と同じ構成となっている。従って、第４の実施例においても、第３の実施例とほぼ同じ作用効果を得ることができる。特に、第４の実施例によれば、半導体チップ４の上面側の放熱板１２の放熱面積を、下面側の放熱板２の放熱面積とほぼ同じになるように構成したので、放熱性能を高くすることができる。   The configuration of the fourth embodiment other than that described above is the same as the configuration of the third embodiment. Accordingly, in the fourth embodiment, substantially the same operational effects as in the third embodiment can be obtained. In particular, according to the fourth embodiment, since the heat radiation area of the heat sink 12 on the upper surface side of the semiconductor chip 4 is configured to be substantially the same as the heat radiation area of the heat sink 2 on the lower surface side, the heat radiation performance is improved. can do.

また、上記第４の実施例では、放熱板１２に凸部１２ａを形成したが、これに代えて、放熱板１２に凸部１２ａを形成することを止めて、平板状の放熱板の下面と半導体チップ４、４の上面との各間にスペーサ（凸部１２ａとほぼ同じ大きさ且つほぼ同じ厚さのスペーサ）を介装するように構成しても良い。   Moreover, in the said 4th Example, although the convex part 12a was formed in the heat sink 12, it replaced with this and stopped forming the convex part 12a in the heat sink 12, and the lower surface of a flat plate-shaped heat sink and A spacer (a spacer having substantially the same size and thickness as the convex portion 12a) may be interposed between each of the semiconductor chips 4 and 4 and the upper surface thereof.

図６及び図７は、本発明の第５の実施例を示すものである。尚、第１の実施例と同一構成には、同一符号を付している。この第５の実施例の半導体装置１３は、２ｉｎ１構造の半導体装置、即ち、インバータ回路を構成する上相スイッチング素子と下相スイッチング素子を対向する放熱板で挟んで樹脂モールドする構造の半導体装置である。この２ｉｎ１構造の半導体装置１３の等価回路を、図７に示す。   6 and 7 show a fifth embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals. The semiconductor device 13 of the fifth embodiment is a semiconductor device having a 2 in 1 structure, that is, a semiconductor device having a resin mold structure in which an upper phase switching element and a lower phase switching element constituting an inverter circuit are sandwiched between opposing heat sinks. is there. An equivalent circuit of the 2-in-1 semiconductor device 13 is shown in FIG.

上記半導体装置１３は、図６に示すように、図６（ｂ）中の下側の図示する形状の放熱板１４の上面に２個の半導体チップ４、４を半田付けしている。この場合、図６（ｂ）中の右の半導体チップ４は、上下逆にして配置しており、図６（ｂ）中の右の半導体チップ４のＩＧＢＴのエミッタと、図６（ｂ）中の左の半導体チップ４のコレクタを放熱板１４に接続している。   As shown in FIG. 6, the semiconductor device 13 has two semiconductor chips 4 and 4 soldered to the upper surface of the heat sink 14 having the shape shown in the lower side of FIG. In this case, the right semiconductor chip 4 in FIG. 6B is arranged upside down, and the IGBT emitter of the right semiconductor chip 4 in FIG. 6B and the right semiconductor chip 4 in FIG. The collector of the left semiconductor chip 4 is connected to the heat sink 14.

そして、図６（ｂ）中の左の半導体チップ４の上面（ＩＧＢＴのエミッタ）に図示する形状の放熱板１５を半田付けし、図６（ｂ）中の右の半導体チップ４の上面（ＩＧＢＴのコレクタ）に図示する形状の放熱板１６を半田付けしている。更に、図６（ｂ）中の左の半導体チップ４の上面のＩＧＢＴのゲートパッドと、制御用端子８とをワイヤボンディングすると共に、図６（ｂ）中の右の半導体チップ４の下面のＩＧＢＴのゲートパッドと、制御用端子１７とをワイヤボンディングしている。   6B is soldered to the upper surface of the left semiconductor chip 4 (IGBT emitter) in FIG. 6B, and the upper surface of the right semiconductor chip 4 in FIG. 6B (IGBT). ) Of the shape shown in the figure is soldered. Further, the IGBT gate pad on the upper surface of the left semiconductor chip 4 in FIG. 6B and the control terminal 8 are wire-bonded, and the IGBT on the lower surface of the right semiconductor chip 4 in FIG. 6B. The gate pad and the control terminal 17 are wire-bonded.

そして、これら全体を樹脂５でモールドしている。図６（ｂ）に示すように、放熱板１４の下面、放熱板１５、１６の上面は、モールド樹脂５から露出している。図６（ａ）に示すように、放熱板１４、１５、１６の一部及び制御用端子８、１７の一部は、モールド樹脂５から外方へ突出している。   These are all molded with the resin 5. As shown in FIG. 6B, the lower surface of the heat radiating plate 14 and the upper surfaces of the heat radiating plates 15 and 16 are exposed from the mold resin 5. As shown in FIG. 6A, a part of the heat sinks 14, 15, 16 and a part of the control terminals 8, 17 protrude outward from the mold resin 5.

尚、上述した以外の第５の実施例の構成は、第１の実施例の構成と同じ構成となっている。従って、第５の実施例においても、第１の実施例とほぼ同じ作用効果を得ることができる。   The configuration of the fifth embodiment other than that described above is the same as that of the first embodiment. Accordingly, in the fifth embodiment, substantially the same operational effects as in the first embodiment can be obtained.

また、上記第５の実施例においては、例えば２ｉｎ１構造の半導体装置１３に適用したが、これに限られるものではなく、例えば６ｉｎ１構造の半導体装置等に適用しても良い。   In the fifth embodiment, the present invention is applied to the semiconductor device 13 having a 2in1 structure, for example. However, the present invention is not limited thereto, and may be applied to a semiconductor device having a 6in1 structure, for example.

また、上記各実施例においては、放熱板２、３、１２、１４、１５、１６と半導体チップ４を半田付けするように構成したが、これに限られるものではなく、接着剤等を用いて接着しても良いし、圧接構造を用いて固着（接合）するように構成しても良い。   Moreover, in each said Example, although it comprised so that the heat sink 2, 3, 12, 14, 15, 16 and the semiconductor chip 4 might be soldered, it is not restricted to this, An adhesive agent etc. are used. It may be bonded, or may be configured to be fixed (joined) using a pressure contact structure.

本発明の第１の実施例を示す半導体装置の縦断面図1 is a longitudinal sectional view of a semiconductor device showing a first embodiment of the present invention; 本発明の第２の実施例を示す図１相当図FIG. 1 equivalent view showing a second embodiment of the present invention. 本発明の第３の実施例を示す図１相当図FIG. 1 equivalent view showing a third embodiment of the present invention. 電気回路図Electrical diagram 本発明の第４の実施例を示す図１相当図FIG. 1 equivalent view showing a fourth embodiment of the present invention. 本発明の第５の実施例を示すものであり、（ａ）は半導体装置の上面図、（ｂ）は（ａ）中のＢ−Ｂ線に沿う断面図、（ｃ）は（ａ）中のＣ−Ｃ線に沿う断面図、（ｄ）は（ａ）中のＤ−Ｄ線に沿う断面図FIG. 9 shows a fifth embodiment of the present invention, where (a) is a top view of the semiconductor device, (b) is a cross-sectional view taken along line BB in (a), and (c) is in (a). Sectional drawing which follows the CC line of (d) is sectional drawing which follows the DD line in (a) 電気回路図Electrical diagram

符号の説明Explanation of symbols

図面中、１は半導体装置、２、３は放熱板、４は半導体チップ、５は樹脂、６は半田、７はワイヤ、８は制御用端子、９は放熱板、９ａは凸部、１０はＩＧＢＴ、１１はＦＷＤ、１２は放熱板、１３は半導体装置、１４は放熱板、１５は放熱板、１６放熱板は、１７は制御用端子を示す。   In the drawings, 1 is a semiconductor device, 2 and 3 are heat sinks, 4 is a semiconductor chip, 5 is resin, 6 is solder, 7 is a wire, 8 is a control terminal, 9 is a heat sink, 9a is a convex portion, 10 is IGBT, 11 is FWD, 12 is a heat sink, 13 is a semiconductor device, 14 is a heat sink, 15 is a heat sink, 16 is a heat sink, and 17 is a control terminal.

Claims (4)

対向する放熱板の間に半導体チップを設けると共に、前記半導体チップ及び前記放熱板を樹脂でモールドしてなる半導体装置において、
前記半導体チップを、ＦＷＤを内蔵したＩＧＢＴチップで構成するとともに、前記対向する放熱板の間に前記半導体チップを複数個設け寄生インダクタンスを低減し、更に、
前記複数個の半導体チップは、同一のウエハから製造されたものであることを特徴とする半導体装置。 In a semiconductor device in which a semiconductor chip is provided between opposing heat sinks, and the semiconductor chip and the heat sink are molded with a resin,
The semiconductor chip is composed of an IGBT chip with a built-in FWD, and a plurality of the semiconductor chips are provided between the opposing heat sinks to reduce parasitic inductance ,
The semiconductor device, wherein the plurality of semiconductor chips are manufactured from the same wafer . 前記半導体チップのＩＧＢＴ及びＦＷＤは並列接続されるとともに、前記複数の半導体チップは並列接続されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein IGBT and FWD of the semiconductor chip are connected in parallel, and the plurality of semiconductor chips are connected in parallel. 前記複数の半導体チップは上相スイッチング素子及び下相スイッチング素子として構成され、前記半導体チップは上下逆にして前記放熱板の間に配置されていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are configured as an upper phase switching element and a lower phase switching element, and the semiconductor chips are disposed upside down between the heat sinks. 前記複数個の半導体チップは、同一のウエハの中の近接した部分から製造されたものであることを特徴とする請求項１記載の半導体装置。 The plurality of semiconductor chips, the semiconductor device according to claim 1, characterized in that made from contiguous portion in the same wafer.
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