CN104733423A - 基板、包含该基板的三维空间封装结构及制造基板的方法 - Google Patents
基板、包含该基板的三维空间封装结构及制造基板的方法 Download PDFInfo
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Abstract
本发明揭示一种基板、包含该基板的三维空间封装结构及制造基板的方法,该基板的侧表面的形成以露出至少一部分的导孔,用以电路连接。该基板包含复数个绝缘层和被该复数个绝缘层所分离的复数个导电层。该基板的一第一侧表面凭借该复数个导电层和该复数个绝缘层所形成。该基板的该第一侧表面包含由一第一导电材料所填充的至少一第一部分的一第一导孔。
Description
技术领域
本发明涉及一基板,特别涉及一种用于三维空间封装结构的一基板。
背景技术
电子封装结构凭借复杂的封装制程所形成。不同的电子封装结构具有不同的电性和散热能力,因此设计者根据设计需求可选择具有理想电性和散热能力的电子封装结构。
图1例示传统电子封装结构10的剖面示意图。参阅图1,多个电子元件12(例如萧特基二极管(SBD)或绝缘闸极双极性电晶体(IGBT))通过焊垫15配置在印刷电路板(PCB)11的上表面上且电性连接印刷电路板11。第一铜金属化片材16可配置于电子元件12和印刷电路板11的上表面之间。施加打线(wire bond)17用于内部电性连接。包覆(encapsulating)材料14包覆电子元件12。对于外部电性连接来说,组装引脚(assembly pins)18(例如汇流排连接)以双列直插式封装(DIP)的形式露出于包覆材料14的外。外壳(housing)19可覆盖包覆材料14。第二铜金属化片材21、基板附着材22、底座(base plate)23、导热胶(thermal grease)24和散热件(heat-sink)25可配置在印刷电路板11的下表面上(例如用于较佳散热)。因为制程容易、成熟且信赖性良好,为目前最主要制程之一。
然而,这种传统制程具有许多缺点,包含:a.引线(lead)焊接至基板顶部以形成引脚(pin),且引脚会占据一部分的设计区域;b.如果引脚设计改变,需要另一个模具的开发工作;单一模具无法适用各式各样的产品。
发明内容
因此,本发明提出了一种基板、包含该基板的三维空间封装结构及制造基板的方法,以克服上述的缺点。
本发明的一个目的提供一种基板,该基板的侧表面的形成以露出至少一部分的导孔,用以电路连接。该基板包含:复数个绝缘层;以及复数个导电层,该复数个导电层被该复数个绝缘层所分离;其中该基板的一第一侧表面凭借该复数个导电层和该复数个绝缘层所形成;其中该基板的该第一侧表面包含由一第一导电材料所填充的至少一第一部分的一第一导孔(via)。
在本发明的一个实施例中,一第一引线(lead)配置在在该基板的该第一侧表面上,其中该第一引线电性连接该至少一第一部分的该第一导孔。
在本发明的一个实施例中,该至少一第一部分的该第一导孔配置成由从该基板的一上表面至该基板的一下表面。
在本发明的一个实施例中,一粘着剂配置在该第一引线上。
本发明的另一个目的提供一种三维空间封装结构。该三维空间封装结构包含:前述的一基板;以及一电子元件,配置在该基板上方且电性连接该复数个导电层。在一个实施例中,一封胶(molding)本体包覆该电子元件。在一个实施例中,该第一引线和一第一塑胶框架结合且该第二引线和第二塑胶框架结合,其中该第一塑胶框架和该第二塑胶框架依附于该封胶本体的一对相对的侧表面。在一个实施例中,一散热板配置在该封胶本体上。在一个实施例中,该散热板具有焊接于一印刷电路板(PCB)的复数个引脚(pin)。在一个实施例中,一封装结构配置在该散热板上。
本发明的另一个目的提供一种制造基板的方法。该方法包含了下列步骤:(a)提供具有复数个导电层的一片材,其中该复数个导电层包含由一导电材料所填充的一第一导孔;以及(b)切割该片材的该第一导孔以形成具有一侧表面的该基板,使得该基板的该侧表面包含一第二导孔,其中该第二导孔为至少一部分的该第一导孔。
与现有技术相比较,本发明具有的有益效果是:1.基板的侧表面的形成以露出由导电材料所填充的至少一部分的导孔以将引线结合至基板的侧表面,以使当引线焊接至印刷电路(PCB)时具有较多的设计弹性;2.配置在三维空间封装结构上或多个三维空间封装结构之间的散热板(例如铜板)可用于散热或屏蔽;3.当需要更多的散热时,散热板(例如铜板)或引线可整合/结合而不需要双重组件;4.附加于散热板的卡勾使得组件更为容易组装;5.附加于散热板的引脚可将热移转至印刷电路板。
附图说明
图1例示传统电子封装结构的剖面示意图;
图2A根据本发明例示一基板的三维空间示意图;
图2B例示图2A中基板的剖面示意图;
图2C根据本发明例示一基板的三维空间示意图,其中至少一第一部分的第一导孔的截面积(垂直于基板的侧表面)为矩形;
图2D根据本发明例示一基板的三维空间示意图,其中至少一第一部分的第一导孔配置成由从该基板的上表面至该基板的下表面,用以结合一第一引线;
图2E例示图2D中基板的剖面示意图;
图2F根据本发明例示一基板的三维空间示意图,其中该基板的第一侧表面包含复数个“非完整”或“完整”导孔(非完整导孔为完整导孔的一部分);
图3A根据本发明例示具有一第一引线的一基板的三维空间示意图;
图3B根据本发明例示一基板的三维空间示意图,其中复数个引线配置在该基板的第一侧表面上;
图3C根据本发明例示一基板的三维空间示意图,其中一对引线分别配置在基板的一对相对侧表面上;
图3D根据本发明例示一基板的三维空间示意图,其中基板的一对相对侧表面中每一个侧表面具有复数个引线;
图4为制造基板一制造流程;
图5A例示由从片材的上表面至片材的下表面配置成的第一导孔;
图5B例示由从片材的上表面至片材的下表面配置成的第二导孔,其中该第二导孔为至少一部分的第一导孔;
图6A至图6C为制造基板的一制造流程;
图7A至图7C为制造基板的一制造流程;
图8A至图8C根据本发明例示一三维空间封装结构,其中该三维空间封装结构具有包覆电子元件的一封胶(molding)本体;
图9A至图9C根据本发明例示一三维空间封装结构,其中该三维空间封装结构具有和多个引线连接的至少一塑胶框架;
图10A至图10C根据本发明例示一三维空间封装结构,其中该三维空间封装结构具有用于散热和屏蔽的一散热板;
图11A至图11C根据本发明例示一三维空间封装结构,其中散热板具有卡勾以扣住塑胶框架;
图12A至图12C根据本发明例示一三维空间封装结构,其中散热板具有焊接于印刷电路板(PCB)的复数个引脚;
图13A至图13C根据本发明例示一三维空间封装结构,其中一封装结构配置在散热板上;
图14A至图14C根据本发明例示一三维空间封装结构,其中多个引线从一第一三维空间封装结构延伸至一第二三维空间封装结构;
图15A至图15C根据本发明例示一三维空间封装结构,其中散热板配置在第二三维空间封装结构的封胶本体上;
图16根据本发明例示一产品的三维空间示意图。
附图标记说明:10传统电子封装结构;11印刷电路板;12电子元件;14包覆材料;15焊垫;16第一铜金属化片材;17打线;18组装引脚;19外壳;21第二铜金属化片材;22基板附着材;23底座;导热胶;25散热件;100基板;101绝缘层;102导电层;103A侧表面;103B侧表面;103’第二侧表面;104A第一导孔;第一侧表面;导孔;上表面;下表面;第一引线;130粘着剂;150片材;151贯穿孔;151A第一部分;151B第二部分;152导电材料;153非导电材料;161封胶本体;162塑胶框架;161A上表面;161B、161C一对相对第一侧表面;161D、161E一对相对第二侧表面;163散热板;164卡勾;165引脚;170封装结构;200三维空间封装结构;200A第一三维空间封装结构;200B第二三维空间封装结构;201步骤;202步骤。
具体实施方式
本发明的详细说明于随后描述,这里所描述的较佳实施例是作为说明和描述的用途,并非用来限定本发明的范围。
下面的多个实施例揭示一基板和用于制造该基板的一方法。下面的多个实施例也揭示一三维空间封装结构和用于制造该三维空间封装结构的一方法。
基板的侧表面的形成以露出至少一部分的导孔,用以电路连接。至少一部分的导孔填充导电材料,用以将引线(lead)结合至基板的侧表面。三维空间封装结构具有相当高的内部空间和设计面积的使用率,因此可降低电子封装结构的尺寸。
图2A根据本发明例示一基板100的三维空间示意图。图2B例示图2A中基板100的剖面示意图。关于图2A和图2B,图2B中部分X1-X1’沿着在图2A中线X1-X1’。基板100包含复数个绝缘层101和被该复数个绝缘层101所分离的复数个导电层102;其中该基板100的一第一侧表面103凭借该复数个导电层102和该复数个绝缘层所形成101;其中该基板100的该第一侧表面103包含由一第一导电材料所填充的至少一第一部分的一第一导孔(via)104。请注意由于基板100的侧表面103形成的故,完整的第一导孔104已不存在,其将在后面作详细地描述。此外,至少一第一部分的第一导孔104的截面积(垂直于基板100的侧表面103)具有任何适合的形状,例如半图形或矩形(见图2C)。
图2D根据本发明例示一基板100的三维空间示意图,其中至少一第一部分的第一导孔104配置成由从基板100的上表面105至基板100的下表面106,用以结合一第一引线111。图2E例示图2D中基板100的剖面示意图。关于图2D和图2E,图2E中部分X2-X2’沿着在图2D中线X2-X2’。图3A根据本发明例示具有一第一引线111的一基板100的三维空间示意图。第一引线111可配置在基板100的第一侧表面103上,其中该第一引线111电性连接至少一第一部分的第一导孔104(例如凭借回焊来作焊接)。
图2A至图2E例示基板100的第一侧表面103包含至少一第一部分的第一导孔104。然而,本发明不局限于这个案例。在一个实施例中,基板100的第一侧表面103进一步包含由一第二导电材料所填充的至少一第二部分的一第二导孔。较佳来说,第一导电材料和第二导电材料相同。在另一个实施例中,基板100的第一侧表面103进一步包含复数个“非完整”或“完整”导孔104(非完整导孔为完整导孔的一部分)(见图2F)。复数个引线111可配置在基板100的第一侧表面103上,其中各个引线111电性连接至少一部分的对应导孔104(图3B)。在一个实施例中,连接至一导线架的各个引线111(导线架具有一金属基底和连接至该金属基底的复数个引线)连接(例如焊接)至少一部分的对应导孔104之后,多个引线111才和金属基底分离。一粘着剂(未图示)可配置在引线111上以保护基板100内部免于锡流动(起因于再熔化)或水气入侵。
在一个实施例中,基板100的一对相对侧表面103、103’凭借复数个导电层102和复数个绝缘层101所形成,且基板100的一对相对侧表面103、103’中每一个侧表面包含至少一部分的对应导孔104(由对应的导电材料所填充)。一对引线111可分别配置在基板100的一对相对侧表面103、103’上,其中一对引线111中每一个引线电性连接至少一部分的对应导孔104(见图3C)。基板100的一对相对侧表面103、103’中每一个侧表面包含复数个“非完整”或“完整”导孔104(非完整导孔为完整导孔的一部分),因此基板100的一对相对侧表面103、103’中每一个侧表面具有复数个引线111(见图3D)。
图4为制造基板100的一制造流程。在步骤201中,提供具有复数个导电层(未图示)的一片材150,其中该复数个导电层包含由一导电材料所填充的一第一导孔104A(见图5A)。图5A例示由从片材150的上表面至片材150的下表面配置成的第一导孔;然而,第一导孔104A可埋入在如图2A所示的片材150内。在步骤202中,切割该片材150的该第一导孔104A以形成具有一侧表面103的该基板100,使得该基板100的该侧表面103包含一第二导孔104,其中该第二导孔104为至少一部分的该第一导孔104A(见图5B)。
在一个实施例中,步骤201包含:在该片材150中形成一贯穿孔151(例如机械式钻孔);以及在该贯穿孔151中填入该导电材料以形成该第一导孔104A。选择性地,贯穿孔151可完全由导电材料所填充。在该贯穿孔151中填入该导电材料以形成该第一导孔104A包含:在一第一部分151A的该贯穿孔151中填入该导电材料152,其中该第一部分151A的该贯穿孔151配置在该贯穿孔151的表面上;以及在一第二部分151B的该贯穿孔151中填入一非导电材料153(例如树脂),其中该第二部分151B的该贯穿孔151由该第一部分151A的该贯穿孔151所围绕(见图6A至图6C)。导电材料152可以任何适合的制程填入,例如铜电镀。较佳来说,铜可配置在贯穿孔151的表面上,且树脂可填入贯穿孔151的中心。在形成基板100的侧表面103后,可移除树脂用于的后的引线连接。
在一个实施例中,该复数个导电层包含复数个第一导孔104A,其中步骤201包含:在该片材150中形成复数个贯穿孔151;以及在该复数个贯穿孔151中填入该导电材料152以形成该复数个第一导孔104A,且步骤202包含:切割该复数个第一导孔104A以形成具有该侧表面103的该基板100,使得该基板100的该侧表面103包含复数个第二导孔104,其中各个该第二导孔104为至少一部分的对应该第一导孔104A(见图7A至图7C)。较佳来说,复数个贯穿孔实质上配置成一直线。
三维空间封装结构200包含上述的一基板100和配置在该基板100上方且电性连接复数个导电层102的一电子元件(未图示)。一第一引线配置在基板100的第一侧表面103上,其中该第一引线111电性连接至少一第一部分的第一导孔104。
在一个实施例中,基板100的一第二侧表面103’凭借复数个导电层102和复数个绝缘层101所形成,其中该第二侧表面103’相对于第一侧表面103;其中基板100的该第二侧表面103’包含由一第二导电材料所填充的至少一第二部分的一第二导孔104。较佳来说,第一导电材料和第二导电材料相同。一第一引线111和一第二引线111分别配置在基板100的第一侧表面103和基板100的第二侧表面103’上;该第一引线111和该第二引线111分别电性连接至少一第一部分的第一导孔104和至少一第二部分的第二导孔104。为了方便解释,下面的多个实施例陈述基板100的一对相对侧表面103、103’中每一个侧表面具有复数个引线111。然而,其它的实施例可适用;举例来说,基板100的一对相对侧表面103、103’中一个侧表面可具有复数个引线111;基板100的一对相对侧表面103、103’中每一个侧表面可具有一个引线111;或基板100的一对相对侧表面103、103’中一个侧表面可具有一个引线111。
在一个实施例中,连接至一导线架的各个引线111(导线架具有一金属基底和连接至该金属基底的复数个引线)连接(例如焊接)至少一部分的对应导孔104之后,多个引线111才和金属基底分离。一粘着剂130可配置在引线111上以保护基板100内部免于锡流动(起因于再熔化)或水气入侵。为了方便解释,下面的多个实施例包含配置在引线111上的一粘着剂130。然而,粘着剂可选择性使用。
图8A根据本发明例示一三维空间封装结构200的三维空间示意图,其中该三维空间封装结构200具有包覆电子元件的一封胶(molding)本体161(电子元件埋入至封胶本体161中而未图示)。图8B例示图8A中三维空间封装结构200的XZ平面示意图(穿过线X3-X3’)。图8C例示图8A中三维空间封装结构200的YZ平面示意图(穿过线X4-X4’)。
图9A根据本发明例示一三维空间封装结构的三维空间示意图,其中该三维空间封装结构具有和多个引线111连接的至少一塑胶框架162。图9B例示图9A中三维空间封装结构的XZ平面示意图(穿过线X5-X5’)。图9C例示图9A中三维空间封装结构的YZ平面示意图(穿过线X6-X6’)。和多个引线111连接的至少一塑胶框架162附着于封胶本体161。至少一塑胶框架162可具有分别附着于封胶本体161的一对相对侧表面161B、161C的两个塑胶框架。
图10A根据本发明例示一三维空间封装结构的三维空间示意图,其中该三维空间封装结构具有用于散热和屏蔽的一散热板163(例如一铜板)。图10B例示图10A中三维空间封装结构的XZ平面示意图(穿过线X7-X7’)。图10C例示图10A中三维空间封装结构的YZ平面示意图(穿过线X8-X8’)。散热板163可配置在封胶本体161上。在一个实施例中,封胶本体161具有一上表面161A、一对相对第一侧表面161B、161C(分别和基板100的一对相对侧表面103、103’共平面,其中多个引线111配置在该基板100的一对相对侧表面103、103’上)和一对相对第二侧表面161D、161E;散热板163可配置在封胶本体161的上表面161A和一对相对第二侧表面161D、161E上。选择性地,上述的两个塑胶框架162可分别附着于封胶本体161的一对相对第一侧表面161B、161C上。在一个实施例中,散热板163可连接多个引线111;当需要更多散热时,散热板163(例如铜板)和多个引线111可整合/结合而不需要双重组件。在一个实施例中,散热板163可不连接多个引线111。
在一个实施例中,散热板163(例如铜板)可具有卡勾(snap)164以扣住塑胶框架162(见图11A至图11C)。在另一个实施例中,散热板163可具有卡勾164以扣住多个引线111。附加于散热板163的卡勾164使得组件更为容易组装。
在一个实施例中,散热板163(例如铜板)可具有焊接于印刷电路板(PCB)的复数个(延伸)引脚165,使得热可移转至印刷电路板(见图12A至图12C)。
在一个实施例中,一封装结构170可配置在散热板163上,使得由封装结构170所产生的热可通过散热板163散逸(见图13A至图13C)。封装结构170可和上述的三维空间封装结构200不同。较佳来说,封装结构170可和上述的三维空间封装结构200相同。多个引线111可从一第一三维空间封装结构200A延伸至一第二三维空间封装结构200B,用以连接配置在该第一三维空间封装结构200A的侧表面103A上的至少一部分之一导孔和配置在该第二三维空间封装结构200B的侧表面103B上的至少一部分之一导孔(见图14A至图14C)。在一个实施例中,散热板163可配置在第二三维空间封装结构200B的封胶本体161上(见图15A至图15C)。图16根据本发明例示一产品的三维空间示意图。
从上面多个实施例的叙述中,本发明的基板/三维空间封装结构及其制造方法可提供很多优点,包含:1.基板的侧表面的形成以露出由导电材料所填充的至少一部分的导孔以将引线结合至基板的侧表面,以使当引线焊接至印刷电路(PCB)时具有较多的设计弹性;2.配置在三维空间封装结构上或多个三维空间封装结构之间的散热板(例如铜板)可用于散热或屏蔽;3.当需要更多的散热时,散热板(例如铜板)或引线可整合/结合而不需要双重组件;4.附加于散热板的卡勾使得组件更为容易组装;5.附加于散热板的引脚可将热移转至印刷电路板。
以上说明对本发明而言只是说明性的,而非限制性的,本领域普通技术人员理解,在不脱离权利要求所限定的精神和范围的情况下,可作出许多修改、变化或等效,但都将落入本发明的保护范围的内。
Claims (20)
1.一种基板,其特征在于,包含:
复数个绝缘层;以及
复数个导电层,该复数个导电层被该复数个绝缘层所分离;其中该基板的一第一侧表面凭借该复数个导电层和该复数个绝缘层所形成;其中该基板的该第一侧表面包含由一第一导电材料所填充的至少一第一部分的一第一导孔。
2.根据权利要求1所述的基板,其特征在于,进一步包含配置在该基板的该第一侧表面上的一第一引线,其中该第一引线电性连接该至少一第一部分的该第一导孔。
3.根据权利要求1所述的基板,其特征在于,该至少一第一部分的该第一导孔配置成由从该基板的一上表面至该基板的一下表面。
4.根据权利要求1所述的基板,其特征在于,进一步包含配置在该第一引线上的一粘着剂。
5.根据权利要求1所述的基板,其特征在于,该基板的该第一侧表面进一步包含由一第二导电材料所填充的至少一第二部分的一第二导孔。
6.根据权利要求5所述的基板,其特征在于,进一步包含配置在该基板的该第一侧表面上的一第一引线和一第二引线,其中该第一引线和该第二引线分别电性连接该至少一第一部分的该第一导孔和该至少一第二部分的该第二导孔。
7.一种三维空间封装结构,其特征在于,包含:
一基板,包含:复数个绝缘层;以及复数个导电层,该复数个导电层被该复数个绝缘层所分离;其中该基板的一第一侧表面凭借该复数个导电层和该复数个绝缘层所形成;其中该基板的该第一侧表面包含由一第一导电材料所填充的至少一第一部分的一第一导孔;以及
一电子元件,配置在该基板上方且电性连接该复数个导电层。
8.根据权利要求7所述的三维空间封装结构,其特征在于,进一步包含配置在该基板的该第一侧表面上的一第一引线,其中该第一引线电性连接该至少一第一部分的该第一导孔。
9.根据权利要求7所述的三维空间封装结构,其特征在于,该基板的一第二侧表面凭借该复数个导电层和该复数个绝缘层所形成,其中该基板的该第二侧表面相对于该基板的该第一侧表面;其中该基板的该第二侧表面包含由一第二导电材料所填充的至少一第二部分的一第二导孔。
10.根据权利要求9所述的三维空间封装结构,其特征在于,进一步包含分别配置在该基板的该第一侧表面和该基板的该第二侧表面上的一第一引线和一第二引线,其中该第一引线和该第二引线分别电性连接该至少一第一部分的该第一导孔和该至少一第二部分的该第二导孔。
11.根据权利要求10所述的三维空间封装结构,其特征在于,进一步包含包覆该电子元件的一封胶本体。
12.根据权利要求11所述的三维空间封装结构,其特征在于,进一步包含与该第一引线结合的一第一塑胶框架和与该第二引线结合的一第二塑胶框架,其中该第一塑胶框架和该第二塑胶框架依附于该封胶本体的一对相对的侧表面。
13.根据权利要求12所述的三维空间封装结构,其特征在于,进一步包含配置在该封胶本体上的一散热板。
14.根据权利要求13所述的三维空间封装结构,其特征在于,该散热板具有焊接于一印刷电路板的复数个引脚。
15.根据权利要求13所述的三维空间封装结构,其特征在于,进一步包含配置在该散热板上的一封装结构。
16.一种制造基板的方法,其特征在于,包含:
(a)提供具有复数个导电层的一片材,其中该复数个导电层包含由一导电材料所填充的一第一导孔;以及
(b)切割该片材的该第一导孔以形成具有一侧表面的该基板,使得该基板的该侧表面包含一第二导孔,其中该第二导孔为至少一部分的该第一导孔。
17.根据权利要求16所述的制造基板的方法,其特征在于,步骤(a)包含:在该片材中形成一贯穿孔;以及在该贯穿孔中填入该导电材料以形成该第一导孔。
18.根据权利要求17所述的制造基板的方法,其特征在于,在该贯穿孔中填入该导电材料以形成该第一导孔包含:在一第一部分的该贯穿孔中填入该导电材料,其中该第一部分的该贯穿孔配置在该贯穿孔的表面上;以及在一第二部分的该贯穿孔中填入一非导电材料,其中该第二部分的该贯穿孔由该第一部分的该贯穿孔所围绕。
19.根据权利要求16所述的制造基板的方法,其特征在于,该复数个导电层包含复数个第一导孔,其中步骤(a)包含:在该片材中形成复数个贯穿孔;以及在该复数个贯穿孔中填入该导电材料以形成该复数个第一导孔,且步骤(b)包含:切割该复数个第一导孔以形成具有该侧表面的该基板,使得该基板的该侧表面包含复数个第二导孔,其中各个该第二导孔为至少一部分的对应该第一导孔。
20.根据权利要求19所述的制造基板的方法,其特征在于,该复数个贯穿孔实质上配置成一直线。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112839437A (zh) * | 2020-12-31 | 2021-05-25 | 广州金升阳科技有限公司 | 一种双面塑封电源产品 |
CN113645776A (zh) * | 2016-11-17 | 2021-11-12 | Lg伊诺特有限公司 | Dc-dc转换器 |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9859250B2 (en) * | 2013-12-20 | 2018-01-02 | Cyntec Co., Ltd. | Substrate and the method to fabricate thereof |
CN105814978B (zh) * | 2014-01-08 | 2018-06-22 | 恩菲斯能源公司 | 双重绝缘散热器 |
JP6354600B2 (ja) * | 2015-01-16 | 2018-07-11 | 株式会社オートネットワーク技術研究所 | 回路構成体、電気接続箱及び回路構成体の製造方法 |
CN105470409A (zh) * | 2016-01-04 | 2016-04-06 | 京东方科技集团股份有限公司 | 一种oled封装结构及其制作方法、显示器件 |
CN107170723B (zh) * | 2016-03-07 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法、电子装置 |
DE102016110862B4 (de) * | 2016-06-14 | 2022-06-30 | Snaptrack, Inc. | Modul und Verfahren zur Herstellung einer Vielzahl von Modulen |
CN107785334B (zh) * | 2016-08-24 | 2019-11-01 | 矽品精密工业股份有限公司 | 电子封装结构及其制法 |
US9984995B1 (en) * | 2016-11-13 | 2018-05-29 | Nanya Technology Corporation | Semiconductor package and manufacturing method thereof |
US20190322572A1 (en) * | 2016-11-18 | 2019-10-24 | Samtec Inc. | Filling materials and methods of filling through holes of a substrate |
CN108109973A (zh) * | 2016-11-25 | 2018-06-01 | 同欣电子工业股份有限公司 | 芯片封装结构及其制造方法 |
TWI607540B (zh) * | 2016-11-25 | 2017-12-01 | Tong Hsing Electronic Industries Ltd | Chip package structure and manufacturing method thereof |
TWI645518B (zh) * | 2017-02-16 | 2018-12-21 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
CN108807294B (zh) * | 2017-04-28 | 2020-02-21 | 矽品精密工业股份有限公司 | 封装结构及其制法 |
TWI652787B (zh) * | 2017-05-25 | 2019-03-01 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
US10293478B2 (en) | 2017-06-06 | 2019-05-21 | Larry Mitchell Grela | Storage hutch assembly |
GB2567746B (en) * | 2017-08-24 | 2022-03-16 | Shindengen Electric Mfg | Semiconductor device |
WO2019037867A1 (en) * | 2017-08-25 | 2019-02-28 | Huawei Technologies Co., Ltd. | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME |
US10002821B1 (en) * | 2017-09-29 | 2018-06-19 | Infineon Technologies Ag | Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates |
US10453705B2 (en) * | 2018-01-09 | 2019-10-22 | Intel Corporation | Multi-voltage apparatus for electronics package including magnetic inductor and capacitor and manufacturing thereof |
SG11202100905XA (en) * | 2018-08-08 | 2021-02-25 | Agency Science Tech & Res | Semiconductor package and method of forming the same |
FR3088137B1 (fr) * | 2018-11-06 | 2020-11-27 | Inst Polytechnique Grenoble | Systeme electronique de puissance |
US10954696B2 (en) | 2018-11-19 | 2021-03-23 | Larry Mitchell Grela | Storage assembly with a drawer having a drawer pull assembly and a method for locking a drawer |
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
US11658410B2 (en) | 2019-03-12 | 2023-05-23 | Epirus, Inc. | Apparatus and method for synchronizing power circuits with coherent RF signals to form a steered composite RF signal |
US11616295B2 (en) | 2019-03-12 | 2023-03-28 | Epirus, Inc. | Systems and methods for adaptive generation of high power electromagnetic radiation and their applications |
US11211703B2 (en) | 2019-03-12 | 2021-12-28 | Epirus, Inc. | Systems and methods for dynamic biasing of microwave amplifier |
US11495519B2 (en) | 2019-06-07 | 2022-11-08 | Dana Canada Corporation | Apparatus for thermal management of electronic components |
US11282791B2 (en) * | 2019-06-27 | 2022-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a heat dissipation structure connected chip package |
US11894347B2 (en) | 2019-08-02 | 2024-02-06 | Semiconductor Components Industries, Llc | Low stress asymmetric dual side module |
US11462515B2 (en) * | 2019-08-02 | 2022-10-04 | Semiconductor Components Industries, Llc | Low stress asymmetric dual side module |
US11469163B2 (en) | 2019-08-02 | 2022-10-11 | Semiconductor Components Industries, Llc | Low stress asymmetric dual side module |
DE102019219238A1 (de) * | 2019-12-10 | 2021-06-10 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Mehrlagiges 3D-Folienpackage |
CN113053833A (zh) * | 2019-12-26 | 2021-06-29 | 财团法人工业技术研究院 | 一种半导体装置及其制作方法 |
TWI717170B (zh) * | 2019-12-26 | 2021-01-21 | 財團法人工業技術研究院 | 半導體裝置及其製作方法 |
US11088093B1 (en) * | 2020-05-28 | 2021-08-10 | X-Celeprint Limited | Micro-component anti-stiction structures |
US11616481B2 (en) | 2020-06-22 | 2023-03-28 | Epirus, Inc. | Systems and methods for modular power amplifiers |
US11444002B2 (en) * | 2020-07-29 | 2022-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure |
CN112117251B (zh) * | 2020-09-07 | 2022-11-25 | 矽磐微电子(重庆)有限公司 | 芯片封装结构及其制作方法 |
TWI746391B (zh) * | 2021-03-15 | 2021-11-11 | 群豐科技股份有限公司 | 積體電路封裝系統 |
DE102021115845A1 (de) | 2021-06-18 | 2022-12-22 | Rolls-Royce Deutschland Ltd & Co Kg | Leiterplattenanordnung |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050027081A1 (en) * | 2003-07-29 | 2005-02-03 | Ube Industries, Ltd., A Corporation Of Japan | Polyoxalate resin and shaped articles and resin compositions comprising same |
CN102117782A (zh) * | 2010-01-06 | 2011-07-06 | 南亚电路板股份有限公司 | 复合埋入式元件结构及其制造方法 |
US20130001756A1 (en) * | 2007-06-08 | 2013-01-03 | Cyntec Co., Ltd. | Three-dimensional package structure |
CN103165558A (zh) * | 2011-12-13 | 2013-06-19 | 乾坤科技股份有限公司 | 封装结构及其制造方法 |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61239649A (ja) * | 1985-04-13 | 1986-10-24 | Fujitsu Ltd | 高速集積回路パツケ−ジ |
TW409377B (en) * | 1999-05-21 | 2000-10-21 | Siliconware Precision Industries Co Ltd | Small scale ball grid array package |
US6847282B2 (en) * | 2001-10-19 | 2005-01-25 | Broadcom Corporation | Multiple layer inductor and method of making the same |
JP4337326B2 (ja) * | 2002-10-31 | 2009-09-30 | 千住金属工業株式会社 | 鉛フリーはんだおよびはんだ付け物品 |
JP4587676B2 (ja) * | 2004-01-29 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | チップ積層構成の3次元半導体装置 |
US20090115042A1 (en) * | 2004-06-04 | 2009-05-07 | Zycube Co., Ltd. | Semiconductor device having three-dimensional stacked structure and method of fabricating the same |
TWI256092B (en) * | 2004-12-02 | 2006-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
WO2007016649A2 (en) * | 2005-08-02 | 2007-02-08 | Satcon Technology Corporation | Double-sided package for power module |
WO2007034629A1 (ja) * | 2005-09-20 | 2007-03-29 | Murata Manufacturing Co., Ltd. | 部品内蔵モジュールの製造方法および部品内蔵モジュール |
CN100524717C (zh) * | 2005-11-25 | 2009-08-05 | 全懋精密科技股份有限公司 | 芯片内埋的模块化结构 |
CN100392849C (zh) * | 2005-12-09 | 2008-06-04 | 威盛电子股份有限公司 | 封装体及封装体模块 |
KR100755658B1 (ko) * | 2006-03-09 | 2007-09-04 | 삼성전기주식회사 | 발광다이오드 패키지 |
CN100459077C (zh) * | 2006-03-15 | 2009-02-04 | 日月光半导体制造股份有限公司 | 基板的制造方法 |
CN100505244C (zh) * | 2006-05-12 | 2009-06-24 | 乾坤科技股份有限公司 | 封装结构 |
CN100416827C (zh) * | 2006-05-18 | 2008-09-03 | 威盛电子股份有限公司 | 封装元件 |
US7531893B2 (en) * | 2006-07-19 | 2009-05-12 | Texas Instruments Incorporated | Power semiconductor devices having integrated inductor |
US20080180921A1 (en) * | 2007-01-31 | 2008-07-31 | Cyntec Co., Ltd. | Electronic package structure |
TWI376774B (en) * | 2007-06-08 | 2012-11-11 | Cyntec Co Ltd | Three dimensional package structure |
US7786837B2 (en) * | 2007-06-12 | 2010-08-31 | Alpha And Omega Semiconductor Incorporated | Semiconductor power device having a stacked discrete inductor structure |
TWI332790B (en) * | 2007-06-13 | 2010-11-01 | Ind Tech Res Inst | Image sensor module with a three-dimensional dies-stacking structure |
TWI362102B (en) * | 2007-07-11 | 2012-04-11 | Ind Tech Res Inst | Three-dimensional dice-stacking package structure and method for manufactruing the same |
US7438558B1 (en) * | 2007-11-13 | 2008-10-21 | International Business Machines Corporation | Three-dimensional stackable die configuration for an electronic circuit board |
US7868431B2 (en) * | 2007-11-23 | 2011-01-11 | Alpha And Omega Semiconductor Incorporated | Compact power semiconductor package and method with stacked inductor and integrated circuit die |
TWI355068B (en) * | 2008-02-18 | 2011-12-21 | Cyntec Co Ltd | Electronic package structure |
US9001527B2 (en) * | 2008-02-18 | 2015-04-07 | Cyntec Co., Ltd. | Electronic package structure |
US8824165B2 (en) * | 2008-02-18 | 2014-09-02 | Cyntec Co. Ltd | Electronic package structure |
TW201011869A (en) * | 2008-09-10 | 2010-03-16 | Cyntec Co Ltd | Chip package structure |
US8339802B2 (en) * | 2008-10-02 | 2012-12-25 | Enpirion, Inc. | Module having a stacked magnetic device and semiconductor device and method of forming the same |
US8153473B2 (en) * | 2008-10-02 | 2012-04-10 | Empirion, Inc. | Module having a stacked passive element and method of forming the same |
WO2010041589A1 (ja) * | 2008-10-08 | 2010-04-15 | 株式会社村田製作所 | 複合モジュール |
KR101009103B1 (ko) * | 2008-10-27 | 2011-01-18 | 삼성전기주식회사 | 양면 전극 패키지 및 그 제조방법 |
TWI407462B (zh) * | 2009-05-15 | 2013-09-01 | Cyntec Co Ltd | 電感器及其製作方法 |
TWI398949B (zh) * | 2009-07-29 | 2013-06-11 | Kingpak Tech Inc | 模造成型之影像感測器封裝結構製造方法及封裝結構 |
US8164158B2 (en) * | 2009-09-11 | 2012-04-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming integrated passive device |
TWI581384B (zh) * | 2009-12-07 | 2017-05-01 | 英特希爾美國公司 | 堆疊式電子電感封裝組件及其製造技術 |
JP5503322B2 (ja) * | 2010-02-15 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US10111333B2 (en) * | 2010-03-16 | 2018-10-23 | Intersil Americas Inc. | Molded power-supply module with bridge inductor over other components |
US8993431B2 (en) * | 2010-05-12 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating bump structure |
TWI611439B (zh) * | 2010-07-23 | 2018-01-11 | 乾坤科技股份有限公司 | 線圈元件 |
TWI448226B (zh) * | 2010-09-21 | 2014-08-01 | Cyntec Co Ltd | 電源轉換模組 |
KR101204191B1 (ko) * | 2010-11-02 | 2012-11-23 | 삼성전기주식회사 | 방열기판 |
KR101715761B1 (ko) * | 2010-12-31 | 2017-03-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US9000576B2 (en) * | 2011-04-22 | 2015-04-07 | Cyntec Co., Ltd. | Package structure and manufacturing method thereof |
US9129908B2 (en) * | 2011-11-15 | 2015-09-08 | Cisco Technology, Inc. | Manufacturing a semiconductor package including an embedded circuit component within a support structure of the package |
US10636735B2 (en) * | 2011-10-14 | 2020-04-28 | Cyntec Co., Ltd. | Package structure and the method to fabricate thereof |
CN103151316B (zh) * | 2011-12-06 | 2017-10-20 | 北京大学深圳研究生院 | 一种基于mcp封装形式的可重构算子阵列结构的规模扩展方法 |
US8716870B2 (en) * | 2011-12-16 | 2014-05-06 | General Electric Company | Direct write interconnections and method of manufacturing thereof |
US9536798B2 (en) * | 2012-02-22 | 2017-01-03 | Cyntec Co., Ltd. | Package structure and the method to fabricate thereof |
US8956918B2 (en) * | 2012-12-20 | 2015-02-17 | Infineon Technologies Ag | Method of manufacturing a chip arrangement comprising disposing a metal structure over a carrier |
CN103633056B (zh) * | 2013-12-06 | 2017-09-01 | 矽力杰半导体技术(杭州)有限公司 | 引线框、封装组件及其制造方法 |
US9859250B2 (en) * | 2013-12-20 | 2018-01-02 | Cyntec Co., Ltd. | Substrate and the method to fabricate thereof |
US10332825B2 (en) * | 2016-05-20 | 2019-06-25 | Infineon Technologies Americas Corp. | Semiconductor package including flip chip mounted IC and vertically integrated inductor |
-
2014
- 2014-09-22 US US14/492,088 patent/US9859250B2/en active Active
- 2014-09-22 US US14/492,085 patent/US9911715B2/en active Active
- 2014-11-10 US US14/536,699 patent/US9984996B2/en active Active
- 2014-12-16 CN CN201810327490.4A patent/CN108447857B/zh active Active
- 2014-12-16 TW TW103143917A patent/TWI622106B/zh active
- 2014-12-16 CN CN201410782796.0A patent/CN104733419A/zh active Pending
- 2014-12-16 TW TW103143915A patent/TWI587759B/zh active
- 2014-12-16 TW TW103143916A patent/TWI567896B/zh active
- 2014-12-16 CN CN201410782812.6A patent/CN104733423B/zh active Active
- 2014-12-16 CN CN201410781471.0A patent/CN104733450B/zh active Active
-
2017
- 2017-11-28 US US15/823,579 patent/US10128214B2/en active Active
-
2018
- 2018-01-22 US US15/876,222 patent/US10297573B2/en active Active
- 2018-04-24 US US15/961,865 patent/US10854575B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050027081A1 (en) * | 2003-07-29 | 2005-02-03 | Ube Industries, Ltd., A Corporation Of Japan | Polyoxalate resin and shaped articles and resin compositions comprising same |
US20130001756A1 (en) * | 2007-06-08 | 2013-01-03 | Cyntec Co., Ltd. | Three-dimensional package structure |
CN102117782A (zh) * | 2010-01-06 | 2011-07-06 | 南亚电路板股份有限公司 | 复合埋入式元件结构及其制造方法 |
CN103165558A (zh) * | 2011-12-13 | 2013-06-19 | 乾坤科技股份有限公司 | 封装结构及其制造方法 |
Non-Patent Citations (1)
Title |
---|
董兆文: "LTCC基板制造工艺研究", 《电子元件与材料》 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113645776A (zh) * | 2016-11-17 | 2021-11-12 | Lg伊诺特有限公司 | Dc-dc转换器 |
CN113645776B (zh) * | 2016-11-17 | 2024-02-13 | Lg伊诺特有限公司 | Dc-dc转换器 |
CN112839437A (zh) * | 2020-12-31 | 2021-05-25 | 广州金升阳科技有限公司 | 一种双面塑封电源产品 |
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CN108447857A (zh) | 2018-08-24 |
TW201543971A (zh) | 2015-11-16 |
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US9859250B2 (en) | 2018-01-02 |
US20180082979A1 (en) | 2018-03-22 |
TW201546914A (zh) | 2015-12-16 |
CN104733423B (zh) | 2019-08-27 |
CN104733450A (zh) | 2015-06-24 |
TWI587759B (zh) | 2017-06-11 |
US10297573B2 (en) | 2019-05-21 |
TWI622106B (zh) | 2018-04-21 |
US20150181733A1 (en) | 2015-06-25 |
CN104733450B (zh) | 2018-05-11 |
CN104733419A (zh) | 2015-06-24 |
US9984996B2 (en) | 2018-05-29 |
US20150181766A1 (en) | 2015-06-25 |
US20150179611A1 (en) | 2015-06-25 |
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