TWI771712B - 封裝基板及其製造方法 - Google Patents

封裝基板及其製造方法 Download PDF

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Publication number
TWI771712B
TWI771712B TW109123815A TW109123815A TWI771712B TW I771712 B TWI771712 B TW I771712B TW 109123815 A TW109123815 A TW 109123815A TW 109123815 A TW109123815 A TW 109123815A TW I771712 B TWI771712 B TW I771712B
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Taiwan
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layer
dielectric layer
photocurable
conductive
package substrate
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TW109123815A
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English (en)
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TW202137469A (zh
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顏尤龍
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日月光半導體製造股份有限公司
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Publication of TW202137469A publication Critical patent/TW202137469A/zh
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Abstract

提供一種封裝基板及製造一封裝基板及一半導體裝置封裝之方法。該封裝基板包括一電路層、一光學固化介電層、複數個阻擋層及一犧牲層。該電路層包括複數個導電襯墊。該光學固化介電層具有一上表面及與該上表面相對之一下表面。該光學固化介電層覆蓋該電路層，且該等導電襯墊之第一表面至少部分地自該光學固化介電層的該上表面暴露。該等阻擋層分別地安置於藉由該光學固化介電層暴露之該等導電襯墊之該等第一表面上。該犧牲層安置於該光學固化介電層上且覆蓋該等阻擋層。

Description

封裝基板及其製造方法
本發明係關於一種封裝基板及其製造方法，且更特定言之，係關於一種具有較薄厚度及足夠的結構強度之封裝基板及其製造方法。
由於緊湊的大小及高效能已成為對消費型電子及通信產品的典型要求，因此半導體裝置封裝經預期擁有優良的電性質、較薄總厚度及大量的I/O埠。為了提供足夠的結構強度以用於支撐半導體晶粒及形成於其上的電子組件，封裝基板需要足夠厚。通常，封裝基板之厚度需要超過100微米以提供足夠的結構強度。然而，封裝基板之較厚厚度增加了半導體裝置封裝之總厚度。
因此，需要研發一種具有較薄厚度但具有足夠的結構強度的封裝基板，以滿足對消費型電子及通信產品之緊湊性要求。
本發明之一個態樣係關於一種封裝基板。在一些實施例中，該封裝基板包括一電路層、一光學固化介電層、複數個阻擋層及一犧牲層。該電路層包括複數個導電襯墊。該光學固化介電層具有一上表面及 與該上表面相對之一下表面。該光學固化介電層覆蓋該電路層，且該等導電襯墊之第一表面至少部分地自該光學固化介電層的該上表面暴露。該等阻擋層分別地安置於藉由該光學固化介電層暴露之該等導電襯墊之該等第一表面上。該犧牲層安置於該光學固化介電層上且覆蓋該等阻擋層。
本發明之另一態樣係關於一種製造一封裝基板的方法。在一些實施例中，該方法包括以下操作。形成包括複數個導電襯墊之一電路層。形成一光敏材料以覆蓋該等導電襯墊。光學地固化該光敏材料以形成具有複數個開口之一光學固化介電層，該複數個開口部分地暴露該等導電襯墊之第一表面。在該等導電襯墊之該等第一表面上之該等開口中形成複數個阻擋層。在該光學固化介電層上及該等阻擋層上形成一犧牲層。
本發明之另一態樣係關於一種製造一半導體裝置封裝的方法。在一些實施例中，該方法包括以下操作。設置上文所提及之封裝基板。將一晶粒安置於該光學固化介電層上且使該晶粒電連接至該等導電襯墊。在該光學固化介電層上形成以一模製層以包封該晶粒。自該光學固化介電層及該等阻擋層移除該犧牲層。在該等阻擋層上形成複數個電導體。
1:封裝基板
2:封裝基板
3:封裝基板
4:封裝基板
10:載體
12:晶種層
14:抗蝕劑層
14H:開口
20:光敏材料
30:電路層
30D:介電層
32:導電襯墊
32E:邊緣
32S1:第一表面
32S2:第二表面
34:導電跡線
34E:邊緣
34S1:第一表面
34S2:第二表面
36:接合襯墊
40:光學固化介電層
40H:開口
40L:下表面
40U:上表面
42:阻擋層
42S:表面
50:犧牲層
60:晶粒
60P:電端子
62:導電結構
64:晶粒貼合膜
66:接合線
70:模製層
80:電導體
100:半導體裝置封裝
200:半導體裝置封裝
300:半導體裝置封裝
301:第一子電路層
302:第二子電路層
321:第一部分
322:第二部分
341:第一部分
342:第二部分
400:半導體裝置封裝
A:區
當結合隨附圖式閱讀時，自以下詳細描述容易地理解本發明之一些實施例的態樣。各種結構可能未按比例繪製，且各種結構之尺寸可出於論述清晰起見任意增大或減小。
圖1為根據本發明之一些實施例的封裝基板之示意性橫截面圖。
圖1A、圖1B及圖1C為根據本發明之一些實施例的圖1中的封裝基板1之區A之示意性橫截面圖。
圖2A、圖2B、圖2C、圖2D、圖2E、圖2F及圖2G說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。
圖3為根據本發明之一些實施例的封裝基板2之示意性橫截面圖。
圖4A、圖4B、圖4C及圖4D說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。
圖5A及圖5B說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。
圖6為根據本發明之一些實施例的封裝基板3之示意性橫截面圖。
圖7A、圖7B、圖7C、圖7D、圖7E及圖7F說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。
圖8為根據本發明之一些實施例的封裝基板4之示意性橫截面圖。
圖9A、圖9B、圖9C、圖9D及圖9E說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。
以下揭示內容提供用於實施所提供主題之不同特徵的許多不同實施例或實例。以下描述組件及配置的具體實例以闡明本發明之某些態樣。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵直接接觸地形成或安置之實施例，且亦可包括在第一特徵與第二特徵之間形成或安置額外特徵，使得第一特徵與第二特徵不直 接接觸的實施例。另外，本發明可在各種實例中重複參考數字及/或字母。此重複係出於簡單及清楚之目的，且本身並不規定所論述之各種實施例及/或組態之間的關係。
如本文中所使用，為易於描述，本文中可使用諸如「在......之下」、「在......下方」、「在......之上」、「在......上方」、「在......上」、「上」、「下」、「左」、「右」、「豎直」、「水平」、「側」及其類似者之空間相對術語來描述如圖式中所說明之一個元件或特徵與另一元件或特徵的關係。除了圖式中所描繪之定向以外，空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞同樣可相應地進行解釋。應理解，當將元件稱為「連接至」或「耦接至」另一元件時，其可直接連接至或耦接至另一元件，或可存在介入元件。
本發明提供具有較薄厚度及較強穩健性之封裝基板。封裝基板可經組態以支撐半導體晶粒及/或電子組件，且可經組態以使半導體晶粒及電子組件電連接至外部電子裝置，諸如印刷電路板。封裝基板可為包括暫時支撐電路層之犧牲層的中間產品。犧牲層可增強封裝基板之結構強度，且可在半導體晶粒及/或電子組件經形成且藉由包封體進行包封之後容易地移除。因此，可減小最終產品(諸如半導體裝置封裝)之總厚度。光學固化介電層可藉由光學固化(諸如UV固化)而非研磨來圖案化，且因此對研磨製程之厚度容差不需要額外厚度。因此，可進一步薄化封裝基板之厚度。
如本文中所使用，術語「光學固化介電層」可指能夠藉由光學固化來圖案化之介電層。在一些實施例中，光學固化介電層可藉由以 下操作來形成：使用諸如UV光的照射經由光罩光學地固化光敏介電材料，並使經固化之光敏介電材料顯影。
圖1為根據本發明之一些實施例的封裝基板1之示意性橫截面圖。如圖1中所展示，封裝基板1包括電路層30、光學固化介電層40、複數個阻擋層42及犧牲層50。電路層30可包括複數個導電襯墊32。導電襯墊32可各自包括第一表面32S1、與第一表面32S1相對之第二表面32S2，及使第一表面32S1連接至第二表面32S2之邊緣32E。電路層30可進一步包括導電跡線34。導電跡線34可各自包括第一表面34S1、與第一表面34S1相對之第二表面34S2，及使第一表面34S1連接至第二表面34S2的邊緣34E。在一些實施例中，導電襯墊32之寬度可比導電跡線34之寬度更寬，但不限於此。在一些實施例中，導電跡線34及導電襯墊32可包括導電材料，諸如金屬，包括銅或其類似者。在一些實施例中，導電跡線34及導電襯墊32之厚度可實質上相等且安置於實質上相同之水平位準處。
光學固化介電層40包括上表面40U及與上表面40U相對之下表面40L。在一些實施例中，光學固化介電層40之上表面40U可為用於安置電導體(諸如焊料)之封裝基板1的焊料側(球側)，且下表面40L可為用於安置電子組件(諸如晶粒)之封裝基板1的組件側。光學固化介電層40可覆蓋電路層30，且導電襯墊32之第一表面32S1至少部分地自光學固化介電層40之上表面40U暴露，而導電跡線34的第一表面34S1可由光學固化介電層40覆蓋。在一些實施例中，導電襯墊32之邊緣32E及導電跡線34之邊緣34E由光學固化介電層40覆蓋。電路層30可包括單層電路層，且導電襯墊32之第二表面32S2及導電跡線34之第二表面34S2可自光學固化介電層40的下表面40L暴露。在一些實施例中，導電襯墊32之第二表面32S2、導 電跡線34之第二表面34S2及光學固化介電層40的下表面40L可實質上共面。在一些實施例中，導電襯墊32之第一表面32S1及導電跡線34之第一表面34S1可實質上共面。在一些實施例中，導電襯墊32之第一表面32S1及/或第二表面32S2經組態以收納電連接件，諸如焊料球、焊料凸塊、金屬支柱、金屬柱或其類似者。在一些實施例中，導電跡線34之第二表面34S2可經組態以收納電連接件，諸如焊料球、焊料凸塊、金屬支柱金屬柱或其類似者。
電路層30可至少部分地嵌入於光學固化介電層40中，且鄰近的導電跡線34及/或導電襯墊32可由光學固化介電層40間隔開。光學固化介電層40可部分地覆蓋導電跡線34及導電襯墊32。由於電路層30嵌入於光學固化介電層40中，故電路層30及光學固化介電層40之總厚度可主要由光學固化介電層40之厚度決定。在一些實施例中，光學固化介電層40之厚度實質上等於50微米或比50微米薄、比40微米薄或甚至更薄以滿足較薄厚度要求。
光學固化介電層40之材料可包括光敏材料，諸如光阻劑。光學固化介電層40可經圖案化以藉由光學地固化光敏材料來暴露導電襯墊32。因此，在使光學固化介電層40圖案化時不損壞導電襯墊32。另外，由於對研磨製程之厚度容差不需要額外厚度，故光學固化介電層40允許最小化導電襯墊32之厚度。因此，可進一步薄化封裝基板1之厚度。
阻擋層42分別地安置於藉由光學固化介電層40暴露之導電襯墊32之第一表面32S1上。犧牲層50安置於光學固化介電層40上且覆蓋阻擋層42。犧牲層50覆蓋光學固化介電層40之上表面40U及導電襯墊32的第一表面32S1。在一些實施例中，犧牲層50可包括導電層，諸如銅層。 在一些實施例中，導電層可藉由電鍍形成。阻擋層42亦可稱作預鍍框架(PPF)或蝕刻終止層。阻擋層42之材料與犧牲層50之材料不同，使得阻擋層42與犧牲層50可具有相異蝕刻選擇性。因此，阻擋層42可經組態作為蝕刻犧牲層50期間之蝕刻終止層，且在移除犧牲層50期間不損壞導電襯墊32。阻擋層42之材料的實例可包括但不限於鎳(Ni)、鈀(PD)、金(Au)或其組合，且犧牲層50及導電襯墊32之材料的實例可包括但不限於銅。阻擋層42可為包括鎳(Ni)、鈀(Pd)、金(Au)或其合金之單層結構，或具有各自包括鎳(Ni)、鈀(Pd)或金(Au)的層的多層結構。
在一些實施例中，阻擋層42與犧牲層50之間及阻擋層42與導電襯墊32之間不存在氣隙。藉助於實例，阻擋層42可與導電襯墊32之第一表面32S1及犧牲層50接觸。由於阻擋層42與犧牲層50之間及阻擋層42與導電襯墊32之間未形成氣隙，故可避免因連續熱製程期間的氣泡而導致的爆裂問題(popcorn issue)。
圖1A、圖1B及圖1C為根據本發明之一些實施例的圖1中的封裝基板1之區A之示意性橫截面圖。如圖1A中所展示，阻擋層42之表面42S可低於光學固化介電層40之上表面40U。犧牲層50之一部分可與光學固化介電層40接合(engaged)。如圖1B中所展示，阻擋層42之表面42S可與光學固化介電層40之上表面40U實質上共面。如圖1C中所展示，阻擋層42之表面42S可高於光學固化介電層40的上表面40U。阻擋層42可部分地覆蓋光學固化介電層40之上表面40U。在一些實施例中，阻擋層42之表面42S可包括凸表面。
在一些實施例中，封裝基板1為中間產品。犧牲層50可經組態作為暫時增強層以支撐具有較薄厚度之光學固化介電層40及電路層 30。犧牲層50將在晶粒及/或其他組件形成於光學固化介電層40之下表面40L上之後移除。犧牲層50之厚度可經選擇以小於、等於或大於光學固化介電層40之厚度，只要犧牲層50可為光學固化介電層40提供足夠的支撐即可。因此，藉由犧牲層50支撐之光學固化介電層40及電路層30可在運送及連續製程期間進行處置。藉助於實例，犧牲層之厚度與光學固化介電層40之厚度的厚度總和實質上等於或大於約50微米、實質上等於或大於約80微米、實質上等於或大於約90微米、實質上等於或大於約100微米、實質上等於或大於約110微米或甚至更大。在一些實施例中，具有所嵌入電路層30之光學固化介電層40的總厚度在約10微米與40微米範圍內，且犧牲層50之厚度可為具有所嵌入電路層30的光學固化介電層40之總厚度的約一至十倍，以使得犧牲層50之結構強度足以向具有所嵌入電路層30之光學固化介電層40提供支撐力。藉助於一實例，具有所嵌入電路層30之光學固化介電層40之總厚度為約10微米，且犧牲層50的厚度在約10微米至約100微米範圍內。
圖2A、圖2B、圖2C、圖2D、圖2E、圖2F及圖2G說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。如圖2A中所展示，設置載體10，諸如玻璃載體、塑膠載體或半導體載體。晶種層12可視情況形成於載體10上。晶種層12可包括藉由無電電鍍或其他合適的製程形成之薄金屬層，諸如薄銅層。
如圖2B中所展示，電路層30隨後形成於載體10上。電路層30包括複數個導電襯墊32及導電跡線34。在一些實施例中，具有複數個開口14H之抗蝕劑層14形成於載體10上，且導電跡線34及導電襯墊32形成於開口14H中。抗蝕劑層14可包括光敏材料(諸如光阻劑)，且開口14H可 藉由曝光及顯影(exposure and development)操作來形成。電路層30之材料可包括金屬，諸如銅。在一些實施例中，電路層30包括單層結構，且導電跡線34及導電襯墊32可藉由晶種層12上之同一電鍍形成。因此，導電跡線34及導電襯墊32可在厚度上實質上相等。
如圖2C中所展示，可移除抗蝕劑層14。光敏材料20隨後形成於覆蓋電路層30之載體10上。光敏材料20可包括光阻劑材料，且可藉由曝光及顯影操作圖案化。如圖2D中所展示，光敏材料20隨後經光學地固化以形成具有複數個開口40H之光學固化介電層40，該複數個開口40H至少部分地暴露導電襯墊32之第一表面32S1。在一些實施例中，不需要諸如研磨製程之薄化製程來暴露導電襯墊32之第一表面32S1，且將不損壞導電襯墊32。此外，導電襯墊32之厚度可經設計成儘可能薄，此係由於對薄化製程之厚度容差不需要額外厚度。複數個阻擋層42形成於導電襯墊32之第一表面32S1上的開口40H中。阻擋層42可藉由電鍍或其他合適的製程來形成。
如圖2E中所展示，犧牲層50形成於光學固化介電層40上及阻擋層42上。在一些實施例中，犧牲層50包括導電層(諸如銅層)，且可藉由電鍍或其他適合的製程來形成。犧牲層50可幫助支撐光學固化介電層40及電路層30，且因此載體10可自光學固化介電層40移除。在存在晶種層12之情況下，可藉由(例如)蝕刻來處理光學固化介電層40之下表面40L以移除晶種層12，從而形成如圖1中所說明的封裝基板1。在一些實施例中，在表面處理之後，導電襯墊32之第二表面32S2可略微低於光學固化介電層40的下表面40L或與該下表面40L共面。
如圖2F中所展示，複數個晶粒60可安置於光學固化介電層 40上且電連接至導電跡線34。在一些實施例中，晶粒60以倒裝晶片之方式電連接至電路層30。舉例而言，晶粒60可包括電端子60P(諸如面朝電路層30之接合襯墊)且經由導電結構62(諸如焊料凸塊、銅柱或其類似者)電連接至導電跡線34及/或導電襯墊32。在一些其他實施例中，晶粒60可經由線接合電連接至導電跡線34及/或導電襯墊32。模製層70可形成於光學固化介電層40上以包封晶粒60。模製層70可包括模製化合物(諸如環氧樹脂)及填充劑(諸如氧化矽填充劑)，且可藉由用模套(mold chase)進行模製操作來形成。在一些實施例中，模製層70與光學固化介電層40接觸。
如圖2G中所展示，移除犧牲層50以暴露阻擋層42。犧牲層50可藉由蝕刻或其他適合的製程來移除。阻擋層42之材料與犧牲層50之材料不同，使得阻擋層42與犧牲層50可具有相異蝕刻選擇性。因此，阻擋層42可經組態作為蝕刻犧牲層50期間之蝕刻終止層，且在移除犧牲層50期間不損壞導電襯墊32。阻擋層42之材料的實例可包括但不限於鎳(Ni)、鈀(PD)、金(Au)或其組合，且犧牲層50及導電襯墊32之材料的實例可包括但不限於銅。阻擋層42可為包括鎳(Ni)、鈀(Pd)、金(Au)或其合金之單層結構，或具有各自包括鎳(Ni)、鈀(Pd)或金(Au)的層的多層結構。
複數個電導體80(諸如焊料球)可形成於導電襯墊32之第一表面32S1上以有助於與外部電子組件(諸如印刷電路板(PCB)或其類似者)的外部電連接。可實行單切以將封裝基板1、晶粒60及模製層70分割成複數個半導體裝置封裝100。
封裝基板1包括嵌入於光學固化介電層40中的電路層20，且因此可減小封裝基板1之厚度。電路層30及光學固化介電層40暫時由犧牲層50支撐，該犧牲層50增強封裝基板1之結構強度且允許在連續製造操 作中載送及處置封裝基板1。犧牲層50可在其他電子組件(諸如半導體晶粒)安置於封裝基板1上之後經移除，且因此可減小半導體裝置封裝100之總厚度。
本發明之封裝基板及製造方法不限於上文所描述的實施例，且可根據其他實施例來實施。為了簡化描述且為了在本發明之各種實施例之間方便比較，以下實施例之類似組件係以相同數字標記且可能不冗餘地描述。
圖3為根據本發明之一些實施例的封裝基板2之示意性橫截面圖。如圖3中所展示，與如圖1中所說明之封裝基板1相比，封裝基板2之導電襯墊32及導電跡線34的佈局可與封裝基板1之佈局不同。在一些實施例中，封裝基板2可經組態以藉由線接合來電連接半導體晶粒。
圖4A、圖4B、圖4C及圖4D說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。如圖4A中所展示，晶種層12、電路層30及光學固化介電層40可形成於載體10上。晶種層12、電路層20及光學固化介電層40可藉由與在圖2A至圖2D中所說明之操作類似的操作來形成。如圖4B中所展示，複數個阻擋層42形成於導電襯墊32之第一表面32S1上的開口40H中。阻擋層42可藉由電鍍或其他合適的製程來形成。犧牲層50形成於光學固化介電層40上及阻擋層42上。犧牲層50可幫助支撐光學固化介電層40及電路層30，且因此載體10及晶種層12可自光學固化介電層40移除以形成如圖3中所說明的封裝基板2。
如圖4C中所展示，接合襯墊36可形成於導電襯墊32上。複數個晶粒60可安置於光學固化介電層40上且電連接至導電襯墊32。在一些實施例中，晶粒60可包括電端子60P，諸如與電路層30相對之接合襯 墊。晶粒60之非主動表面可藉由晶粒貼合膜(DAF)64黏著至光學固化介電層40，且晶粒60可經由接合線66電連接至接合襯墊36。接合襯墊36之材料可經如此選擇以增強接合線66與接合襯墊36之間的黏著力。接合襯墊36之材料可與導電襯墊32之材料不同。舉例而言，接合襯墊36之材料可包括金(Au)。模製層70可形成於光學固化介電層40上以包封晶粒60。模製層70可包括模製化合物(諸如環氧樹脂)及填充劑(諸如氧化矽填充劑)，且可藉由用模套進行模製操作來形成。在一些實施例中，模製層70可與光學固化介電層40接觸且包封接合線66。
如圖4D中所展示，移除犧牲層50以暴露阻擋層42。犧牲層50可藉由蝕刻或其他適合的製程來移除。阻擋層42之材料與犧牲層50之材料不同，使得阻擋層42與犧牲層50可具有相異蝕刻選擇性。因此，阻擋層42可經組態作為蝕刻犧牲層50期間之蝕刻終止層，且在移除犧牲層50期間不損壞導電襯墊32。複數個電導體80(諸如焊料球)可形成於導電襯墊32之第一表面32S1上以有助於與外部電子組件(諸如印刷電路板(PCB)或其類似者)的外部電連接。可實行單切以將封裝基板2、晶粒60及模製層70分割成複數個半導體裝置封裝200。
圖5A及圖5B說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。如圖5A中所展示，與圖4A至圖4D中所說明之操作相比，接合襯墊36在導電襯墊32形成之前形成於載體10或晶種層12上。因此，接合襯墊36可部分地嵌入於如圖5B中所展示之導電襯墊32中。
圖6為根據本發明之一些實施例的封裝基板3之示意性橫截面圖。如圖6中所展示，與如圖1中所說明之封裝基板1相比，電路層30包 括多層電路層。電路層30可包括第一子電路層301、介電層30D及第二子電路層302。第一子電路層301及第二子電路層302可形成於不同製程中。第一子電路層301可包括導電襯墊32之第一部分321，且導電襯墊32之第一部分321可包括導電襯墊32的第二表面32S2。介電層30D安置於光學固化介電層40之下表面40L上且部分地覆蓋導電襯墊32的第一部分321。介電層30D之材料可包括有機介電材料或無機介電材料。第二子電路層302包括導電襯墊32之第二部分322，且導電襯墊32之第二部分322部分地由光學固化介電層40覆蓋並且可包括導電襯墊32的第一表面32S1。阻擋層42分別地安置於藉由光學固化介電層40暴露之導電襯墊32之第一表面32S1上。犧牲層50安置於光學固化介電層40上且覆蓋阻擋層42。
圖7A、圖7B、圖7C、圖7D、圖7E及圖7F說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。如圖7A中所展示，晶種層12可形成於載體10上。電路層30隨後形成於載體10上。在一些實施例中，電路層30藉由如圖7A及圖7B中所說明之操作來形成。如圖7A中所展示，導電襯墊32之複數個第一部分321及導電跡線34之第一部分341形成於載體10上。在一些實施例中，導電襯墊32之第一部分321及導電跡線34之第一部分341可藉由電鍍形成且由抗蝕劑層圖案化。如圖7B中所展示，介電層30D形成於導電襯墊32之第一部分321及導電跡線34之第一部分341上。介電層30D經圖案化以部分地暴露導電襯墊32之第一部分321。在一些實施例中，介電層30D可藉由打孔來圖案化。在一些實施例中，介電層30D可包括光敏材料且藉由光學固化來圖案化。導電襯墊32之複數個第二部分322及導電跡線34之第二部分342形成於介電層30D上。導電襯墊32之第二部分322可穿透介電層30D以電連接導電襯墊32的第一部 分321。導電跡線34之第二部分342可直接連接至導電跡線34之第一部分341，或經由導電襯墊32電連接至導電跡線34的第一部分341。
如圖7C中所展示，光學固化介電層40形成於介電層30D上。光學固化介電層40可藉由光學固化來圖案化以形成至少部分地暴露導電襯墊32之第一表面32S1的複數個開口40H。複數個阻擋層42形成於導電襯墊32之第一表面32S1上的開口40H中。阻擋層42可藉由電鍍或其他合適的製程來形成。
如圖7D中所展示，犧牲層50形成於光學固化介電層40上及阻擋層42上。在一些實施例中，犧牲層50包括導電層(諸如銅層)，且可藉由電鍍或其他適合的製程來形成。犧牲層50可幫助支撐光學固化介電層40及電路層30，且因此載體10及晶種層12可自光學固化介電層40移除。在存在晶種層12之情況下，可藉由(例如)蝕刻來處理光學固化介電層40之下表面40L以移除晶種層12，從而形成如圖3中所說明的封裝基板3。在一些實施例中，在表面處理之後，導電襯墊32之第二表面32S2可略微低於光學固化介電層40的下表面40L或與該下表面40L共面。
如圖7E中所展示，複數個晶粒60可安置於光學固化介電層40上且電連接至導電跡線34及/或導電襯墊32。在一些實施例中，晶粒60以倒裝晶片之方式電連接至電路層30。模製層70可形成於光學固化介電層40上以包封晶粒60。模製層70可包括模製化合物(諸如環氧樹脂)及填充劑(諸如氧化矽填充劑)，且可藉由用模套進行模製操作來形成。在一些實施例中，模製層70與光學固化介電層40接觸。
如圖7F中所展示，移除犧牲層50以暴露阻擋層42。犧牲層50可藉由蝕刻或其他適合的製程來移除。阻擋層42之材料與犧牲層50之 材料不同，使得阻擋層42與犧牲層50可具有相異蝕刻選擇性。因此，阻擋層42可經組態作為蝕刻犧牲層50期間之蝕刻終止層，且在移除犧牲層50期間不損壞導電襯墊32。複數個電導體80(諸如焊料球)可形成於導電襯墊32之第一表面32S1上以有助於與外部電子組件(諸如印刷電路板(PCB)或其類似者)的外部電連接。可實行單切以將封裝基板3、晶粒60及模製層70分割成複數個半導體裝置封裝300。
圖8為根據本發明之一些實施例的封裝基板4之示意性橫截面圖。如圖8中所展示，與如圖6中所說明之封裝基板3相比，封裝基板4之導電襯墊32及導電跡線34的佈局可與封裝基板3之佈局不同。在一些實施例中，封裝基板4可經組態以藉由線接合來電連接半導體晶粒。
圖9A、圖9B、圖9C、圖9D及圖9E說明根據本發明之一些實施例的製造封裝基板及半導體裝置封裝之操作。如圖9A中所展示，晶種層12可形成於載體10上。電路層30隨後形成於載體10上。在一些實施例中，電路層30可包括多層電路層，且藉由與圖7A及圖7B中所說明之操作類似的操作來形成。
如圖9B中所展示，光學固化介電層40形成於介電層30D上。光學固化介電層40可藉由光學固化來圖案化以形成至少部分地暴露導電襯墊32之第一表面32S1的複數個開口40H。複數個阻擋層42形成於導電襯墊32之第一表面32S1上的開口40H中。阻擋層42可藉由電鍍或其他合適的製程來形成。
如圖9C中所展示，犧牲層50形成於光學固化介電層40上及阻擋層42上。在一些實施例中，犧牲層50包括導電層(諸如銅層)，且可藉由電鍍或其他適合的製程來形成。犧牲層50可幫助支撐光學固化介電層 40及電路層30，且因此載體10及晶種層12可自光學固化介電層40移除。在存在晶種層12之情況下，可藉由(例如)蝕刻來處理光學固化介電層40之下表面40L以移除晶種層12，從而形成如圖8中所說明的封裝基板4。在一些實施例中，在表面處理之後，導電襯墊32之第二表面32S2可略微低於光學固化介電層40的下表面40L或與該下表面40L共面。
如圖9D中所展示，接合襯墊36可形成於導電襯墊32上。接合襯墊36之寬度可與導電襯墊32之寬度實質上相同，但不限於此。在一些其他實施例中，接合襯墊36可在導電襯墊32形成之前形成，且因此可由介電層30D嵌入。複數個晶粒60可安置於光學固化介電層40上且電連接至導電襯墊32。在一些實施例中，晶粒60可包括電端子60P，諸如與電路層30相對之接合襯墊。晶粒60之非主動表面可藉由晶粒貼合膜(DAF)64黏著至光學固化介電層40，且晶粒60可經由接合線66電連接至接合襯墊36。模製層70可形成於光學固化介電層40上以包封晶粒60。模製層70可包括模製化合物(諸如環氧樹脂)及填充劑(諸如氧化矽填充劑)，且可藉由用模套進行模製操作來形成。在一些實施例中，模製層70可與光學固化介電層40接觸且包封接合線66。
如圖9E中所展示，移除犧牲層50以暴露阻擋層42。犧牲層50可藉由蝕刻或其他適合的製程來移除。阻擋層42之材料與犧牲層50之材料不同，使得阻擋層42與犧牲層50可具有相異蝕刻選擇性。因此，阻擋層42可經組態作為蝕刻犧牲層50期間之蝕刻終止層，且在移除犧牲層50期間不損壞導電襯墊32。複數個電導體80(諸如焊料球)可形成於導電襯墊32之第一表面32S1上以有助於與外部電子組件(諸如印刷電路板(PCB)或其類似者)的外部電連接。可實行單切以將封裝基板2、晶粒60及 模製層70分割成複數個半導體裝置封裝400。
在本發明之一些實施例中，封裝基板包括嵌入於光學固化介電層中之電路層，且因此可減小封裝基板的厚度。封裝基板進一步包括暫時支撐電路層及光學固化介電層之犧牲層，以增強封裝基板之結構強度且允許在連續製造操作中載送及處置封裝基板。犧牲層可在其他電子組件(諸如半導體晶粒)安置於封裝基板上之後經移除，且因此可減小半導體裝置封裝之總厚度。光學固化介電層可藉由光學固化(諸如UV固化)而非研磨來圖案化，且因此對研磨製程之厚度容差不需要額外厚度。因此，可進一步薄化封裝基板之厚度。
如本文中所使用，除非上下文另外清楚地規定，否則單數術語「一(a/an)」及「該」可包括複數個指示物。
如本文中所使用，術語「大約」、「實質上」、「實質的」及「約」用以描述及考慮較小變化。當與事件或情形結合使用時，術語可指事件或情形明確發生之情況以及事件或情形極近似於發生之情況。舉例而言，當結合數值使用時，該等術語可指小於或等於彼數值之±10%的變化範圍，諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%之變化範圍。舉例而言，若兩個數值之間的差小於或等於該等值之平均值的±10%，諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%，則可認為該等值「實質上」相同或相等。舉例而言，「實質上」平行可指相對於0°而言小於或等於±10°之角度變化範圍，諸如，小於或等於±5°、小於或等於±4°、小於 或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°，或小於或等於±0.05°之角度變化範圍。舉例而言，「實質上」垂直可指相對於90°而言小於或等於±10°之角度變化範圍，諸如，小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°或小於或等於±0.05°之角度變化範圍。
另外，在本文中有時以範圍格式呈現量、比率及其他數值。應理解，此類範圍格式係為便利及簡潔起見而使用，且應靈活地理解為不僅包括明確指定為範圍限制之數值，且亦包括涵蓋於彼範圍內之所有個別數值或子範圍，如同明確指定各數值及子範圍一般。
儘管已參考本發明之特定實施例描述並說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者應理解，在不脫離如由所附申請專利範圍界定的本發明之真實精神及範疇的情況下，可作出各種改變且可取代等效物。圖示可不必按比例繪製。歸因於製造製程及容差，本發明中之藝術再現與實際設備之間可存在區別。可存在並未特定說明的本發明之其他實施例。說明書及圖式應視為說明性，而非限制性。可作出修改，以使特定情形、材料、物質組成、方法或製程適應於本發明之目標、精神及範疇。所有此類修改意欲在此隨附申請專利範圍之範疇內。儘管參考按特定次序執行之特定操作描述本文中所揭示之方法，但應理解，在不脫離本發明之教示的情況下，可組合、再細分，或重新定序此等操作以形成等效方法。因此，除非本文中特定地指示，否則操作之次序及分組並非對本發明之限制。
32:導電襯墊
32E:邊緣
32S1:第一表面
32S2:第二表面
34:導電跡線
34E:邊緣
34S1:第一表面
34S2:第二表面
40:光學固化介電層
40L:下表面
40U:上表面
42:阻擋層
50:犧牲層
A:區

Claims (21)

  1. 一種封裝基板，其包含：一電路層，其包含複數個導電襯墊；一光學固化介電層，其具有一上表面及與該上表面相對之一下表面，其中該光學固化介電層覆蓋該電路層，且界定暴露該等導電襯墊之第一表面之至少一部分的開口；複數個阻擋層，分別地安置於藉由該光學固化介電層之該等開口暴露之該等導電襯墊之該等第一表面上，其中該等阻擋層之上表面低於該光學固化介電層之該上表面；及一犧牲層，其安置於該光學固化介電層上，延伸至該光學固化介電層之該等開口中且覆蓋該等阻擋層，其中該電路層包含一單層電路層，且該等導電襯墊之第二表面自該光學固化介電層之該下表面暴露，且該等導電襯墊之該等第二表面與該光學固化介電層之該下表面實質上共面。
  2. 如請求項1之封裝基板，其中該等導電襯墊之邊緣由該光學固化介電層覆蓋。
  3. 如請求項1之封裝基板，其中該電路層包含一多層電路層，該多層電路層包含：一第一子電路層，其包含該等導電襯墊之第一部分，其中該等導電襯墊之該等第一部分具有該等導電襯墊的該等第二表面； 一介電層，其安置於該光學固化介電層之該下表面上且部分地覆蓋該等導電襯墊之該等第一部分；及一第二子電路層，其包含該等導電襯墊之第二部分，其中該等導電襯墊之該等第二部分部分地由該光學固化介電層覆蓋且具有該等導電襯墊的該等第一表面。
  4. 如請求項1之封裝基板，其中該電路層進一步包含部分地由該光學固化介電層覆蓋之複數個導電跡線，且該等導電跡線及該等導電襯墊之厚度實質上相等且安置於實質上相同位準處。
  5. 如請求項1之封裝基板，其中該犧牲層之一厚度大於該光學固化介電層之一厚度。
  6. 如請求項1之封裝基板，其中該光學固化介電層之一厚度小於約40微米。
  7. 如請求項1之封裝基板，其中該犧牲層接觸該光學固化介電層之該等開口的側壁。
  8. 如請求項1之封裝基板，其進一步包含安置鄰近於該光學固化介電層之該下表面的晶粒及安置於該光學固化介電層之該下表面上的模製層，其中該導電襯墊的該第一表面在該光學固化介電層之該下表面上的投影面積延伸超過該晶粒在該光學固化介電層之該下表面上的投影面積。
  9. 如請求項8之封裝基板，其中該晶粒經由接合線電連接至該導電襯墊，且該晶粒藉由晶粒貼合膜附著至該光學固化介電層之該下表面。
  10. 如請求項1之封裝基板，其中該犧牲層包含導電層。
  11. 如請求項1之封裝基板，其中該犧牲層係經組態作為暫時增強層。
  12. 一種製造一封裝基板之方法，其包含：形成包含複數個導電襯墊的一電路層在一載體上；形成覆蓋該等導電襯墊的一光敏材料；光學地固化該光敏材料以形成具有複數個開口之一光學固化介電層，該複數個開口部分地暴露該等導電襯墊之第一表面；在該等導電襯墊之該等第一表面上之該等開口中形成複數個阻擋層，其中該等阻擋層之上表面低於該光學固化介電層之上表面；及在該光學固化介電層上及該等阻擋層上形成一犧牲層，該犧牲層延伸至該光學固化介電層之該等開口中。
  13. 如請求項12之方法，其中在該光學固化介電層上及該等阻擋層上形成該犧牲層包含將在該等阻擋層及該光學固化介電層上之一導電層電鍍作為該犧牲層。
  14. 如請求項13之方法，其進一步包含使用該等阻擋層作為蝕刻終止層 來蝕刻該導電層。
  15. 如請求項12之方法，其進一步包含：在形成該電路層之前在該載體上形成一晶種層；及藉由電鍍在該晶種層上形成該電路層。
  16. 如請求項15之方法，其進一步包含：移除該載體；及自該光學固化介電層移除該晶種層以暴露該等導電襯墊之第二表面。
  17. 如請求項12之方法，其進一步包含與該等導電襯墊同時形成複數個導電跡線。
  18. 如請求項14之方法，其中在該光學固化介電層上形成該犧牲層包含形成該犧牲層以接觸該光學固化介電層之該等開口的側壁。
  19. 如請求項14之方法，其進一步包含：安置一晶粒鄰近於該光學固化介電層之與該上表面相對之下表面；及安置一模製層於該光學固化介電層之該下表面，其中該導電襯墊的該第一表面在該光學固化介電層之該下表面上的投影面積延伸超過該晶粒在該光學固化介電層之該下表面上的投影面積。
  20. 如請求項19之方法，其中安置該晶粒鄰近於該光學固化介電層之該下表面包含藉由晶粒貼合膜將該晶粒安置於該光學固化介電層之該下表面，且經由接合線將該晶粒電連接至該導電襯墊。
  21. 一種製造一半導體裝置封裝之方法，其包含：提供如請求項12製造出之該封裝基板；在該光學固化介電層上安置一晶粒且使該晶粒電連接至該等導電襯墊；在該光學固化介電層上形成一模製層以包封該晶粒；自該光學固化介電層及該等阻擋層移除該犧牲層；及在該等阻擋層上形成複數個電導體。
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