CN110634756A - Fan-out packaging method and packaging structure - Google Patents
Fan-out packaging method and packaging structure Download PDFInfo
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- CN110634756A CN110634756A CN201910734809.XA CN201910734809A CN110634756A CN 110634756 A CN110634756 A CN 110634756A CN 201910734809 A CN201910734809 A CN 201910734809A CN 110634756 A CN110634756 A CN 110634756A
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract
The invention discloses a fan-out packaging method and a packaging structure, wherein the method comprises the following steps: forming rewiring layers at two ends of the first surface of the carrier plate; forming a conductive metal pillar on the upper surface of the rewiring layer; attaching the back surface of the chip to the blank area of the first surface of the carrier plate; and forming a plastic package layer on the first surface of the carrier plate, forming a conductive interconnection layer on the front surface of the chip and the upper surface of the plastic package layer, wherein the conductive interconnection layer is electrically connected with the chip and the conductive metal column respectively. And removing the carrier plate and the temporary bonding layer formed on the first surface of the carrier plate, and forming a welding spot electrically connected with the rewiring layer through the insulating medium layer connected with the rewiring layer. The method provided by the invention realizes double-sided fan-out packaging of the chip, and the conductive metal column penetrates through the plastic packaging layer, so that the two sides of the chip layer can be electrically connected through the conductive metal column, the production difficulty of the packaging structure is reduced, the reliability of each process is improved, and the volume of the packaging structure is reduced.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a fan-out packaging method and a fan-out packaging structure.
Background
With the rapid development of integrated circuit technology, the packaging of integrated circuits is also continuously perfected. The feature size of the chip is gradually miniaturized to meet the requirement of moore's law, and although the feature size of the chip is reduced, the number of electronic components (including resistors, capacitors, diodes, transistors, etc.) in the chip is continuously increased. In order to realize the application of chip functions to product terminals, a packaging technology with compact packaging size and more output terminal I/O quantity is required in the packaging field. Currently, advanced packaging methods include: wafer level Chip scale packaging, fan-out Flip Chip (Flip Chip), and stack-up packaging, among others.
The fan-out package is an embedded package, has more I/O (input/output) numbers and better integration flexibility, and is a main advanced packaging mode. In order to meet the requirement of a user on the higher and higher packaging size, in the prior art, in order to enable the number and functions of components in a packaging piece not to be affected, the packaging size is not compact enough, the size is large, and in the process of manufacturing a packaging structure, the number of steps is large, the process is complex, and therefore the requirement of the user cannot be met frequently.
Disclosure of Invention
In view of this, the present invention provides a fan-out packaging method and structure, so as to solve the technical problems of the prior art that the packaging structure has a large volume and a complicated manufacturing process.
The technical scheme provided by the invention is as follows:
in a first aspect, an embodiment of the present invention provides a fan-out packaging method, including: forming rewiring layers at two ends of the first surface of the carrier plate; forming a conductive metal pillar on the upper surface of the rewiring layer; attaching the back surface of the chip to the blank area of the first surface of the carrier plate; forming a plastic package layer on the first surface of the carrier plate, wherein the plastic package layer covers the chip and the side wall of the conductive metal column and exposes the front surface of the chip and the conductive metal column; and forming a conductive interconnection layer on the front surface of the chip and the upper surface of the plastic packaging layer, wherein the conductive interconnection layer is electrically connected with the chip and the conductive metal column respectively.
Optionally, after the step of forming the molding compound layer on the first surface of the carrier board and before the step of forming the conductive interconnection layer on the front surface of the chip and the upper surface of the molding compound layer, the fan-out packaging method further includes forming a conductive layer on the front surface of the chip, wherein the upper surface of the conductive layer and the upper surface of the conductive metal pillar are in the same horizontal plane.
Optionally, before the step of forming the redistribution layer on the first surface of the carrier, the method further includes: forming a temporary bonding layer on the first surface of the carrier plate; and forming an insulating medium layer on the temporary bonding layer.
Optionally, after the step of forming the conductive interconnection layer on the front surface of the chip and the upper surface of the plastic package layer, the method further includes: and removing the carrier plate and the temporary bonding layer.
Optionally, the method further includes: and forming a welding point which is electrically connected with the rewiring layer through the insulating medium layer.
In a second aspect, an embodiment of the present invention further provides a fan-out package structure, including: the back surface of the chip and the lower surface of the rewiring layer are positioned on the same horizontal plane; the conductive metal column is arranged on the upper surface of the rewiring layer and is electrically connected with the rewiring layer; the plastic packaging layer coats the chip and the side wall of the conductive metal column, and the front surface of the chip and the conductive metal column are exposed; and the conductive interconnection layer is formed on the front surface of the chip and is electrically connected with the chip and the conductive metal column respectively.
Optionally, the redistribution layer includes: re-laying a transfer line layer and a first dielectric layer; the first medium layer is formed in a gap between the redistribution transfer line layer and the first medium layer, and the upper surface of the first medium layer and the upper surface of the redistribution transfer line layer are positioned on the same horizontal plane.
Optionally, the fan-out package structure further includes: the conductive layer is formed on the front surface of the chip, and the upper surface of the conductive layer and the upper surface of the conductive metal column are in the same horizontal plane.
Optionally, the conductive layer includes: a conductive pad and a second dielectric layer; the second dielectric layer is formed in a gap between the conductive pad and the front surface of the chip, and the upper surface of the second dielectric layer and the upper surface of the conductive pad are located on the same horizontal plane.
Optionally, the fan-out package structure further includes: and the insulating medium layer is fixedly connected with the back surface of the chip and the lower surface of the rewiring layer.
Optionally, the fan-out package structure further includes: and the welding spot penetrates through the insulating medium layer and is electrically connected with the rewiring layer.
The technical scheme of the invention has the following advantages:
according to the fan-out packaging method and the packaging structure provided by the embodiment of the invention, the rewiring layers are formed at two ends of the first surface of the carrier plate; forming a conductive metal pillar on the upper surface of the rewiring layer; therefore, due to the existence of the rewiring layer, the conductive metal column cannot move in the manufacturing process of the packaging structure; attaching the back surface of the chip to the blank area of the first surface of the carrier plate; forming a plastic packaging layer on the first surface of the carrier plate, coating the side walls of the chip and the conductive metal column, and exposing the front surface of the chip and the conductive metal column; and forming a conductive interconnection layer on the front surface of the chip and the upper surface of the plastic packaging layer, wherein the conductive interconnection layer is electrically connected with the chip and the conductive metal column respectively. Removing the carrier plate and the temporary bonding layer formed on the first surface of the carrier plate, and forming a welding spot electrically connected with the rewiring layer by penetrating through the insulating medium layer connected with the rewiring layer, so that double-sided fan-out packaging of the chip is realized; in addition, because the conductive metal column penetrates through the plastic packaging layer, the two sides of the chip layer can be electrically connected through the conductive metal column without arranging a through hole in the chip or reserving a preset position when the chip is designed, so that the design difficulty of the chip is reduced, the requirements on the consistency of design specifications and technologies of different upstream and downstream manufacturers of the chip are reduced, the production difficulty of the packaging structure is reduced, the reliability of each process is improved, and the volume of the packaging structure is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flow diagram illustrating one example of a fan-out packaging method provided by an embodiment of the invention;
FIG. 2 illustrates another example flow diagram of a fan-out packaging method provided by the present invention;
fig. 3 to fig. 8 are schematic structural diagrams obtained by the fan-out packaging method according to the embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a fan-out packaging method, and as shown in fig. 1, the fan-out packaging method includes the steps of:
step S1: rewiring layers 2 are formed at both ends of the first surface of the carrier board 1. As shown in fig. 6, the rewiring layer 2 includes: a rewiring transfer line layer 21 and a first dielectric layer 22; in the manufacturing process, a redistribution transfer line layer 21 is formed on the carrier board 1, the first dielectric layer 22 is formed in the gap of the redistribution transfer line layer 21, and the upper surface of the first dielectric layer 22 and the upper surface of the redistribution transfer line layer 21 are located on the same horizontal plane. The material of the first dielectric layer 22 may be inorganic material such as silicon oxide, silicon carbide, etc., or organic material such as PBO, PI, etc., which is only used as an example and not limited herein; the redistribution layer 21 may be made of a metal material such as copper, aluminum, gold, nickel, palladium, silver, etc., and the present invention is not limited thereto.
Step S2: a conductive metal pillar 3 is formed on the upper surface of the rewiring layer 2. Specifically, as shown in fig. 4, the conductive metal stud 3 is formed on the upper surface of the redistribution transfer line layer 21; since the conductive metal pillar 3 and the redistribution layer 21 are made of metal materials, the conductive metal pillar 3 will not move during the fabrication process of the package structure after the conductive metal pillar 3 and the redistribution layer are fixedly connected, and thus the open circuit caused by the deviation of the conductive metal pillar 3 will not occur.
Step S3: the back surface of the chip 10 is attached to the blank area of the first surface of the carrier plate 1. As shown in fig. 4 and 5, the width of the blank area is the distance between the redistribution layers 2 at the two ends of the carrier board 1, and in order to enable the back surface of the chip 10 to be attached to the carrier board 1, the distance between the redistribution layers 2 at the two ends of the carrier board 1 should be greater than the width of the chip 10 or equal to the width of the chip 10.
Step S4: and forming a plastic package layer 4 on the first surface of the carrier plate 1, wherein the plastic package layer 4 covers the chip 10 and the side walls of the conductive metal posts, and exposes the front surface of the chip 10 and the conductive metal posts 3. As shown in fig. 6, the conductive metal posts 3, the rewiring layer 2 and the chip 10 are insulated and fixed by the plastic package layer 4; the molding layer 4 may be made of an organic material such as epoxy resin, phenolic resin, etc., and is planarized and reduced in height by processes such as grinding and chemical etching (for example, but not limited thereto), and the metal conductive pillars are exposed, so as to implement electrical interconnection of the package structure.
Step S5: and forming a conductive interconnection layer 5 on the front surface of the chip 10 and the upper surface of the plastic packaging layer 4, wherein the conductive interconnection layer 5 is electrically connected with the chip 10 and the conductive metal column 3 respectively. As shown in fig. 7, the conductive interconnect layer 5 includes: a conductive portion 51 and an insulating portion 52; first, the conductive parts 51 electrically connected to the chip 10 and the conductive metal posts 3, respectively, are formed to achieve electrical conduction; the insulation part 52 is formed in the gap of the conductive part 51; the conductive portion 51 may be made of conductive metal such as copper, aluminum, tungsten, tin, etc.; the material of the insulating portion 52 can be PBO, PI, BCB, etc., and the invention is not limited thereto.
In an embodiment, after forming the molding layer 4 on the first surface of the carrier board 1 in step 4 and before forming the conductive interconnection layer 5 on the front surface of the chip 10 and the upper surface of the molding layer 4 in step 5, as shown in fig. 2, the fan-out packaging method further includes:
step 41: a conductive layer 6 is formed on the front surface of the chip 10, and the upper surface of the conductive layer 6 is at the same level as the upper surface of the conductive metal pillar 3. As shown in fig. 6, the conductive layer 6 includes: conductive pads 61 and a second dielectric layer 62; first, a conductive pad 61 fixedly connected to the chip 10 is formed, and a second dielectric layer 62 is formed in a gap between the conductive pad 61 and the front surface of the chip 10, and an upper surface of the second dielectric layer 62 and an upper surface of the conductive pad 61 are located on the same horizontal plane. Specifically, the conductive pad 61 is electrically connected to the chip 10 and the conductive portion 51 of the conductive interconnection layer 5; the conductive pad 61 may be made of metal such as copper, aluminum, nickel, tin, gold, etc., and the second dielectric layer 62 may be made of inorganic material such as silicon oxide, silicon carbide, etc., or organic material such as PBO, PI, etc., which are not limited to the above embodiments.
In an embodiment, as shown in fig. 2, before the step 1 of forming the redistribution layer 2 on the first surface of the carrier 1, the method further includes:
step 100: a temporary bonding layer 7 is formed on the first surface of the carrier 1.
Step 200: an insulating dielectric layer 8 is formed on the temporary bonding layer 7.
As shown in fig. 3, the carrier 1 and the insulating medium layer 8 are connected together by the temporary bonding layer 7, and the rewiring layer 2 and the back surface of the chip 10 are disposed on the insulating medium layer 8. The insulating dielectric layer 8 makes it easier and simpler to form the rewiring layer 2 and the chip 10.
In one embodiment, as shown in fig. 2, after forming the conductive interconnection layer 5 on the front surface of the chip 10 and the upper surface of the molding layer 4 in step 5, the electrically connecting the conductive interconnection layer 5 with the chip 10 and the conductive metal pillar 3 respectively further includes:
step 6: and removing the carrier plate 1 and the temporary bonding layer 7. The temporary bonding layer 7 is removed by a de-bonding process, which is not limited in the present invention.
And 7: pads 9 electrically connected to the rewiring layer 2 are formed through the insulating dielectric layer 8. Before forming the welding spot 9, as shown in fig. 8, the welding spot 9 penetrates through the insulating medium layer 8 to be electrically connected with the redistribution transfer line layer 21, and a welding hole can be formed on the insulating medium layer 8 through a photoetching or etching process and the lower surface of the redistribution transfer line layer 21 is exposed; forming a welding spot 9 in the welding hole and fixedly connecting the welding spot with the lower surface of the redistribution transfer line layer 21; electrical connection can also be achieved through the solder joint 9; therefore, double-sided fan-out packaging of the chip is realized; the material of the insulating dielectric layer 8 may be inorganic material such as silicon oxide, silicon nitride, etc., or PBO or other photosensitive or non-photosensitive organic material, which is only an example and not a limitation of the present invention.
By the fan-out packaging method, double-sided fan-out packaging is realized; in addition, because the conductive metal column 3 runs through and sets up in the plastic envelope layer 4, so 10 layers of both sides of chip can realize the electricity through this conductive metal column 3 and connect, need not to set up the through-hole in chip 10 inside, also need not to reserve the preset position when designing chip 10, thereby reduced the design degree of difficulty of chip 10, reduced the requirement of the uniformity to different upstream and downstream producer design specification and technique of chip 10, thereby reduced packaging structure's the production degree of difficulty, improved each technological reliability, reduced packaging structure's volume.
An embodiment of the present invention provides a fan-out package structure, as shown in fig. 3 to 8, including: a chip 10 and a rewiring layer 2, the back surface of the chip 10 and the lower surface of the rewiring layer 2 being located on the same horizontal plane; the rewiring layers 2 are formed at two ends of the insulating medium layer 8, and the middle blank area is provided with a chip 10; note that the width of the blank area is greater than the width of the chip 10, or equivalent to the width of the chip 10; wherein, rewiring layer 2 includes: a rewiring transfer line layer 21 and a first dielectric layer 22; the first dielectric layer 22 is formed in the gap of the redistribution transfer line layer 21, and the upper surface of the first dielectric layer 22 and the upper surface of the redistribution transfer line layer 21 are located on the same horizontal plane. In the embodiment of the present invention, the material of the first dielectric layer 22 may be an inorganic material such as silicon oxide, silicon carbide, or the like, or an organic material such as PBO, PI, or the like, which is not limited herein; the redistribution layer 21 may be made of a metal material such as copper, aluminum, gold, nickel, palladium, silver, etc., but the invention is not limited thereto.
A conductive metal pillar 3 provided on the upper surface of the rewiring layer 2 and electrically connected to the rewiring layer 2; specifically, the conductive metal posts 3 are formed on the upper surface of the redistribution transfer line layer 21; since the conductive metal pillar 3 and the redistribution layer 21 are made of metal materials, the conductive metal pillar 3 will not move during the fabrication process of the package structure after the conductive metal pillar 3 and the redistribution layer are fixedly connected, and thus the open circuit caused by the deviation of the conductive metal pillar 3 will not occur.
The plastic packaging layer 4 covers the chip 10 and the side wall of the conductive metal column 3, and exposes the front surface of the chip 10 and the conductive metal column; the insulation among the conductive metal columns 3, the rewiring layer 2 and the chip 10 is realized through the plastic packaging layer 4, and the conductive metal columns, the rewiring layer and the chip can be fixed; the material of the plastic package layer 4 may be an organic material such as epoxy resin, phenolic resin, etc., and planarization and height reduction are achieved through processes such as grinding, chemical etching, etc., and the metal conductive pillars are exposed, so as to achieve electrical interconnection of the package structure, which is not limited by the invention.
And the conductive interconnection layer 5 is formed on the front surface of the chip 10 and is electrically connected with the chip 10 and the conductive metal column 3 respectively. The conductive interconnect layer 5 includes: a conductive portion 51 and an insulating portion 52; the conductive parts 51 are electrically connected with the conductive metal posts 3 and the chip 10 respectively to realize electric conduction; the conductive portion 51 may be made of conductive metal such as copper, aluminum, tungsten, tin, etc.; the material of the insulating portion 52 can be PBO, PI, BCB, etc., and the invention is not limited thereto.
In an embodiment, the fan-out package structure further comprises: and the conductive layer 6 is formed on the front surface of the chip 10, and the upper surface of the conductive layer 6 and the upper surface of the conductive metal column 3 are in the same horizontal plane. The conductive layer 6 includes: conductive pads 61 and a second dielectric layer 62; the second dielectric layer 62 is formed in the gap between the conductive pad 61 and the front surface of the chip 10, and the upper surface of the second dielectric layer 62 and the upper surface of the conductive pad 61 are located on the same horizontal plane. Specifically, the conductive pad 61 is electrically connected to the chip 10 and the conductive portion 51 of the conductive interconnection layer 5; the conductive pad 61 may be made of metal such as copper, aluminum, nickel, tin, gold, etc., and the second dielectric layer 62 may be made of inorganic material such as silicon oxide, silicon carbide, etc., or organic material such as PBO, PI, etc., which are not limited to the above embodiments.
In an embodiment, the fan-out package structure further comprises: and the insulating medium layer 8 is fixedly connected with the back surface of the chip 10 and the lower surface of the rewiring layer 2. And a pad 9 electrically connected to the rewiring layer 2 through the insulating dielectric layer 8. The material of the insulating dielectric layer 8 may be inorganic material such as silicon oxide, silicon nitride, etc., or PBO or other photosensitive or non-photosensitive organic material, which is not limited in the present invention. Specifically, the pad 9 is electrically connected to the redistribution transfer line layer 21 in the redistribution layer 2, and since the redistribution transfer line layer 21 and the pad 9 are both made of metal, the function of electrical conduction can be realized when the two are connected, and a functional signal of the chip is derived.
The fan-out packaging structure realizes double-sided fan-out packaging, can lead functional signals of the chip to be led out on double sides, and also provides more I/O (input/output) quantity of output terminals; in addition, because the conductive metal column 3 runs through and sets up in the plastic envelope layer 4, so 10 layers of both sides of chip can realize the electricity through this conductive metal column 3 and connect, need not to set up the through-hole in chip 10 inside, also need not to reserve the preset position when designing chip 10, thereby reduced the design degree of difficulty of chip 10, reduced the requirement of the uniformity to different upstream and downstream producer design specification and technique of chip 10, thereby reduced packaging structure's the production degree of difficulty, improved each technological reliability, reduced packaging structure's volume.
Although the present invention has been described in detail with respect to the exemplary embodiments and the advantages thereof, those skilled in the art will appreciate that various changes, substitutions and alterations can be made to the embodiments without departing from the spirit and scope of the invention as defined by the appended claims. For other examples, one of ordinary skill in the art will readily appreciate that the order of the process steps may be varied while maintaining the scope of the present invention.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims (11)
1. A fan-out packaging method, comprising:
forming rewiring layers at two ends of the first surface of the carrier plate;
forming a conductive metal pillar on the upper surface of the rewiring layer;
attaching the back surface of the chip to the blank area of the first surface of the carrier plate;
forming a plastic package layer on the first surface of the carrier plate, wherein the plastic package layer covers the chip and the side wall of the conductive metal column and exposes the front surface of the chip and the conductive metal column;
and forming a conductive interconnection layer on the front surface of the chip and the upper surface of the plastic packaging layer, wherein the conductive interconnection layer is electrically connected with the chip and the conductive metal column respectively.
2. The fan-out packaging method of claim 1, wherein after the step of forming the molding layer on the first surface of the carrier board and before the step of forming the conductive interconnection layer on the front surface of the chip and the upper surface of the molding layer, further comprising:
and forming a conductive layer on the front surface of the chip, wherein the upper surface of the conductive layer and the upper surface of the conductive metal column are in the same horizontal plane.
3. The fan-out packaging method of claim 1, wherein prior to the step of forming a re-routing layer on the first surface of the carrier board, further comprising:
forming a temporary bonding layer on the first surface of the carrier plate;
and forming an insulating medium layer on the temporary bonding layer.
4. The fan-out packaging method of claim 1, further comprising, after the step of forming a conductive interconnect layer on the front side of the die and the upper surface of the molding layer:
and removing the carrier plate and the temporary bonding layer.
5. The fan-out packaging method of claim 3, further comprising:
and forming a welding point which is electrically connected with the rewiring layer through the insulating medium layer.
6. A fan-out package structure, comprising:
a chip and a re-wiring layer,
the back surface of the chip and the lower surface of the rewiring layer are positioned on the same horizontal plane;
the conductive metal column is arranged on the upper surface of the rewiring layer and is electrically connected with the rewiring layer;
the plastic packaging layer coats the chip and the side wall of the conductive metal column, and the front surface of the chip and the conductive metal column are exposed;
and the conductive interconnection layer is formed on the front surface of the chip and is electrically connected with the chip and the conductive metal column respectively.
7. The fan-out package structure of claim 6, wherein the re-routing layer comprises: re-laying a transfer line layer and a first dielectric layer;
the first dielectric layer is formed in a gap of the redistribution transfer line layer, and the upper surface of the first dielectric layer and the upper surface of the redistribution transfer line layer are positioned on the same horizontal plane.
8. The fan-out package structure of claim 6, further comprising: the conductive layer is formed on the front surface of the chip, and the upper surface of the conductive layer and the upper surface of the conductive metal column are in the same horizontal plane.
9. The fan-out package structure of claim 8, wherein the conductive layer comprises: a conductive pad and a second dielectric layer;
the second dielectric layer is formed in a gap between the conductive pad and the front surface of the chip, and the upper surface of the second dielectric layer and the upper surface of the conductive pad are located on the same horizontal plane.
10. The fan-out package structure of claim 6, further comprising: and the insulating medium layer is fixedly connected with the back surface of the chip and the lower surface of the rewiring layer.
11. The fan-out package structure of claim 10, further comprising: and the welding spot penetrates through the insulating medium layer and is electrically connected with the rewiring layer.
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