CN105304605A - Chip embedded encapsulation structure and encapsulation method of same - Google Patents
Chip embedded encapsulation structure and encapsulation method of same Download PDFInfo
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- CN105304605A CN105304605A CN201510808355.8A CN201510808355A CN105304605A CN 105304605 A CN105304605 A CN 105304605A CN 201510808355 A CN201510808355 A CN 201510808355A CN 105304605 A CN105304605 A CN 105304605A
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- 238000005538 encapsulation Methods 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 72
- 239000010409 thin film Substances 0.000 claims abstract description 57
- 238000002161 passivation Methods 0.000 claims abstract description 41
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010931 gold Substances 0.000 claims abstract description 9
- 229910052737 gold Inorganic materials 0.000 claims abstract description 9
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 9
- 239000000178 monomer Substances 0.000 claims description 78
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 239000010408 film Substances 0.000 claims description 24
- 235000012431 wafers Nutrition 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 239000003351 stiffener Substances 0.000 claims description 17
- 238000004806 packaging method and process Methods 0.000 claims description 15
- 238000012856 packing Methods 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 238000010329 laser etching Methods 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000011946 reduction process Methods 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000003014 reinforcing effect Effects 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 6
- 239000006185 dispersion Substances 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229920002521 macromolecule Polymers 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000011863 silicon-based powder Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a chip embedded encapsulation structure and an encapsulation method of the same, which belong to the technical field of semiconductor encapsulation. The chip embedded encapsulation structure comprises a chip single body and a thin film encapsulation body, wherein one or more than one chip single bodies are embedded into the thin film encapsulation body from the back face, a nickel/gold layer is filled in a passivation layer opening in the chip surface, the upper surface of the chip single body and the upper surface of the thin film encapsulation body are covered by insulating thin film layers I, an opening of the insulating thin film layer I is disposed in the upper surface of the nickel/gold layer, a re-wiring metal layer and an insulating thin film layer II are formed on the upper surface of the insulating thin film layer I, the re-wiring metal layer is electrically connected to a chip electrode by the nickel/gold layer, an input/output end is disposed on the outmost layer of the re-wiring metal layer, a connecting part is formed at the input/output end, and a silicon substrate reinforcing plate is disposed on the back face of the thin film encapsulation body. The encapsulation method disclosed by the invention reduces a product thickness, increases product reliability and realizes the multi-chip encapsulation structure through wafer-level technological forming.
Description
Technical field
The present invention relates to a kind of chip embedded encapsulating structure and method for packing thereof, belong to technical field of semiconductor encapsulation.
Background technology
Along with the development of semiconductor silicon technique, the critical size of chip is more and more less, in order to reduce costs, tends to the chip fabrication technique selecting more advanced integrated level higher when carrying out chip manufacturing, this just makes the size of chip more and more less, and the I/O density of chip surface is also more and more higher.But meanwhile the manufacturing process of printed circuit board (PCB) and surface mounting technology do not have greatly improved.For the chip that this I/O density ratio is higher, if carry out wafer level packaging, can form interconnection in order to ensure chip to be packaged and printed substrate must be low-density packaging pin by highdensity I/O fan-out, that is carry out the encapsulation of level chip fan-out, as shown in Figure 1, its chip 1-1 to be packaged realizes fan-out connection by substrate 1-6.But along with further developing of portable electric appts, electronic installation as mobile phone one class has been converted into the integrated system of comprehensive multifrequency nature from single communication tool, become versatile exquisite instrument, the deficiency of existing level chip fan-out packaging structure highlights day by day:
1, existing level chip fan-out packaging structure needs substrate 1-6 to realize fan-out, then need multilager base plate 1-6 many fan-outs could complete interconnection with printed substrate for the little chip with high number of pins, not only increase mismatch probability and the heat radiation difficulty of ever-increasing interconnect pitch, reduce the reliability of product, and the existence of substrate 1-6 makes the thickness of whole encapsulating structure reduce, the body thickness of general existing level chip fan-out packaging structure is at 700 ~ 1500 microns;
2, existing level chip fan-out packaging structure needs substrate 1-6 to realize fan-out, often limits adding of the various chips with difference in functionality, is unfavorable for the integrated development of portable electric appts.
Summary of the invention
The object of the invention is to the deficiency overcoming current level chip encapsulating structure, the chip embedded encapsulating structure of the multi-chip package that a kind of thinning product thickness is provided, improves product reliability, realizes and method for packing thereof.
the object of the present invention is achieved like this:
A kind of chip embedded encapsulating structure of the present invention, it comprises the chip monomer that upper surface is provided with chip electrode and related circuit layout, the upper surface of the chip body of described chip monomer covers chip surface passivation layer and offers chip surface passivation layer opening, the upper surface exposed chip surface passivation layer opening of chip electrode
Also comprise thin film encapsulation body, chip monomer described in one or more embeds in thin film encapsulation body by the back side, fill in described chip surface passivation layer opening and first form the ni/au layers that nickel dam forms layer gold again, insulating thin layer I is covered at the upper surface of described chip monomer and the upper surface of thin film encapsulation body, and offer insulating thin layer I opening in the upper surface of described ni/au layers, interconnection metal layer and insulating thin layer II is formed again at the upper surface of insulating thin layer I, described interconnection metal layer again fills insulating thin layer I opening, described interconnection metal layer again realizes being electrically connected by chip electrode described in ni/au layers and each, and optionally realize two or more association described chip electrode between electric connection, input/output terminal is provided with at the outermost layer of interconnection metal layer again, described insulating thin layer II covers interconnection metal layer again and exposes input/output terminal, connector is formed at described input/output terminal place, the back side of described thin film encapsulation body arranges silica-based stiffener.
The input/output terminal of described interconnection metal layer is again arranged at the periphery of the vertical area of chip monomer.
Described interconnection metal layer is again single or multiple lift.
The size of described insulating thin layer I opening is not more than the size of chip surface passivation layer opening.
Described insulating thin layer I opening is implanted into metal column, and described metal column connects interconnection metal layer and ni/au layers again.
Described connector is solder bumps, welding block or metal derby.
The method for packing of a kind of chip embedded encapsulating structure of the present invention, comprises step:
Step one, gets IC wafers, and its surface is provided with chip electrode and related circuit layout, and the chip surface passivation layer being covered in IC wafers upper surface offers the upper surface of chip surface passivation layer opening exposed chip electrode above chip electrode;
Step 2, plates ni/au layers in chip surface passivation layer opening;
Step 3, carries out parameter testing to IC wafers, and reduction process is carried out at the back side of qualified IC wafers, then cuts into plural independently chip monomer;
Step 4, the prop carrier body of prop carrier pastes stripping film;
Step 5, by chip monomer, upside-down mounting is on prop carrier in an orderly manner, and chip monomer is fixed by stripping film and prop carrier;
Step 6, under vacuum conditions, prop carrier pastes thin film encapsulation chip monomer, forms thin film encapsulation body;
Step 7, is bonded to the back side of thin film encapsulation body by silica-based stiffener, and upper and lower 180 degree of upsets;
Step 8, peels off the surface of chip monomer and thin film encapsulation body, and cleans the surface of chip monomer, and remove residue, expose the upper surface of ni/au layers by prop carrier body and stripping film;
Step 9, pastes insulating thin layer at the upper surface of chip monomer and the upper surface of thin film encapsulation body;
Step 10, utilizes laser etching process or photoetching process formation insulating thin layer I opening to expose the upper surface of ni/au layers;
Step 11, utilizes the ripe layer process of wiring metal again to form interconnection metal layer again, and be provided with input/output terminal at the outermost layer of interconnection metal layer again, insulating thin layer II covers interconnection metal layer again, and exposes input/output terminal;
Step 12, forms connector at the input/output terminal place of interconnection metal layer again;
Step 13, is thinned to silica-based stiffener by the lower surface of silica-based stiffener and leaves thickness h, the structure of the chip embedded encapsulation completed above by wafer level technique is carried out cutting and forms plural independently packaging body.
Alternatively, in step 4, described stripping film is UV stripping film or hot stripping film.
Compare and existing scheme, the invention has the beneficial effects as follows:
1, by thin film technique, in conjunction with wafer level, interconnection metal layer technology and flip-chip technology realize the fan-out packaging structure of single or multiple lift again in the present invention, be low-density packaging pin to guarantee that the little chip of the especially high number of pins of chip to be packaged or super tiny chip and printed substrate can realize highdensity I/O fan-out, do not need substrate, insert or underfill, be thinned whole encapsulating structure;
2, the present invention adopts the restructuring wafer encapsulation technology of chip package system collaborative design and advanced person and reliable interconnection technique, achieve the multichip packaging structure of difference in functionality, be conducive to the integrated development of portable electric appts, achieve the miniaturization of encapsulating structure, slimming and lightweight simultaneously;
3, apply materials of the present invention, adopts thin-film material to be embedded in wherein by chip to be packaged, makes all around four faces and the back side of chip to be packaged all obtain physics and electic protection, prevent external interference, improve the reliability of encapsulating products;
4, the present invention utilizes film Filming Technology to replace existing technology, reduce the requirement of packaging technology to equipment, the silica-based stiffener at the film back side not only strengthens the intensity of thin film encapsulation body simultaneously, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer, also contribute to the reliability improving encapsulating products.
Accompanying drawing explanation
Fig. 1 is the generalized section of existing level chip fan-out packaging structure;
Fig. 2 is the flow chart of the method for packing of a kind of chip embedded encapsulating structure of the present invention;
Fig. 3 A is the generalized section of the embodiment one of a kind of chip embedded encapsulating structure of the present invention;
Fig. 3 B is the front schematic view of thin film encapsulation body in Fig. 3 A, chip monomer, soldered ball position relationship;
Fig. 4 A ~ 4Q is the flow chart of the method for packing of a kind of chip embedded encapsulating structure of the present invention of Fig. 3 A;
Fig. 5 A is the generalized section of the embodiment two of a kind of chip embedded encapsulating structure of the present invention;
Fig. 5 B is the front schematic view of thin film encapsulation body in Fig. 5 A, chip monomer, soldered ball position relationship;
Fig. 6 is the generalized section of the embodiment three of a kind of chip embedded encapsulating structure of the present invention;
In figure:
Chip monomer 10, chip monomer 20
Chip body 11, chip body 21
Chip electrode 13, chip electrode 23
Chip surface passivation layer 15, chip surface passivation layer 25
Chip surface passivation layer opening 151, chip surface passivation layer opening 251
Ni/au layers 17
Thin film encapsulation body 3
Interconnection metal layer 41 again
Input/output terminal 411
Insulating thin layer I 51
Insulating thin layer I opening 511
Insulating thin layer II 52
Connector 6;
IC wafers 100
Prop carrier T1
Prop carrier body T11
Stripping film T13
Silica-based stiffener 7
Line of cut 8.
Embodiment
See Fig. 2, the technological process of the method for packing of a kind of chip embedded encapsulating structure of the present invention is as follows:
S1: get IC wafers, plates ni/au layers in its chip surface passivation layer opening;
S2: reduction process is carried out to the back side of IC wafers, then cut into plural independently chip monomer;
S3: by the upside-down mounting of chip monomer on prop carrier;
S4: paste film to the chip monomer on prop carrier under vacuum conditions, forms thin film encapsulation body;
S5: the back side silica-based stiffener being bonded to thin film encapsulation body;
S6: prop carrier is peeled off chip monomer and thin film encapsulation body;
S7: paste insulating thin layer I at the upper surface of chip monomer and the upper surface of thin film encapsulation body;
S8: utilize photoetching or laser etching process formation insulating thin layer I opening to expose the upper surface of ni/au layers;
S9: utilize the ripe layer process of wiring metal again to form interconnection metal layer again, is provided with input/output terminal at the outermost layer of interconnection metal layer again, covers insulating thin layer II, and expose input/output terminal;
S10: form connector at the input/output terminal place of interconnection metal layer again;
S11: the said structure completing packaging technology is cut into the embedded encapsulation monomer of plural chips.
Describe the present invention more fully hereinafter with reference to accompanying drawing now, exemplary embodiment of the present invention shown in the drawings, thus scope of the present invention is conveyed to those skilled in the art by the disclosure fully.But the present invention can realize in many different forms, and should not be interpreted as being limited to the embodiment set forth here.
Embodiment one, see Fig. 3 A and Fig. 3 B
Fig. 3 A is the generalized section of the embodiment one of a kind of chip embedded encapsulating structure of the present invention, chip embedded encapsulating structure of the present invention comprises the chip monomer 10 that a back side embeds thin film encapsulation body 3, the upper surface of the chip body 11 of chip monomer 10 is provided with chip electrode 13 and related circuit layout thereof, chip surface passivation layer 15 covers the upper surface of chip body 11 and offers chip surface passivation layer opening 151, the upper surface exposed chip surface passivation layer opening 151 of chip electrode 13, and filling first forms the ni/au layers 17 that nickel dam forms layer gold again in chip surface passivation layer opening 151, be not destroyed with protect IC electrode 13 in post laser etching process.The material of thin film encapsulation body 3 includes but not limited to epoxy-plastic packaging material; it is generally curing agent with High Performance Phenolic Resins; adding silicon powder etc. is filler; and add multiple additive mixture and form; it is first in molten condition at high temperature 175 ~ 185 DEG C; all around four faces and the back side of tight parcel chip monomer 10; can harden gradually after cooling; final molding; all around four faces and the back side of chip monomer 10 is made all to obtain physics and electic protection; prevent external interference, to improve its reliability.
Insulating thin layer I 51 covers the upper surface of chip monomer 10 and the upper surface of thin film encapsulation body 3, and offer insulating thin layer I opening 511 in the upper surface of ni/au layers 17 by laser etching process or photoetching process, the size of insulating thin layer I opening 511 is not more than the size of chip surface passivation layer opening 151, the rounded or polygon such as quadrangle, hexagon of the shape of its cross section.The material of insulating thin layer I 51 is generally the macromolecule such as epoxy resin, polyimides organic insulating material.Discontinuous interconnection metal layer again 41 is optionally formed at the upper surface of insulating thin layer I 51 and fills insulating thin layer I opening 511.Interconnection metal layer 41 realizes being electrically connected by ni/au layers 17 and chip electrode 13 again.Also can implant the metal column that copper etc. has conducting function in insulating thin layer I opening 511, this metal column connects interconnection metal layer 41 and ni/au layers 17 again, realizes being electrically connected.Interconnection metal layer 41 can be individual layer again, and as shown in Figure 3A, be provided with input/output terminal 411 at the outermost layer of interconnection metal layer 41 again, the number of input/output terminal 411 is arranged according to actual needs.For little chip or the super tiny chip of high number of pins, by wafer level again interconnection metal layer technology its input/output terminal 411 can be made to be arranged at the periphery of the vertical area of little chip or super tiny chip, so that the electrode signal fan-out of individuality is less, electrode comparatively dense connects.As little for 1 × 1mm chip made 3 × 3mm encapsulating structure, I/O:20, pitch:0.4mm.Connector 6 can be formed at input/output terminal 411 place; connector 6 can be solder bumps, welding block or other metal connecting piece; solder bumps for connector 6 in Fig. 3 B; show the front schematic view of chip monomer 10 and the position relationship of thin film encapsulation body 3, solder bumps; visible; chip monomer 10 is arranged at the inside of thin film encapsulation body 3, and it all obtains physics and electic protection in four faces and the back side all around, improves its reliability.
The back side of thin film encapsulation body 3 arranges the silica-based stiffener 7 of silicon material, its thickness is not more than 200 microns, and be good with its thickness range 50 ~ 100 microns, not only strengthen the intensity of thin film encapsulation body 3, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer 10, also contribute to the reliability promoting encapsulating products.
A kind of chip embedded encapsulating structure of the present invention can obtain the encapsulating structure of body thickness 500 ~ 800 microns, thinner more than traditional encapsulating structure, gentlier, less.
The method for packing of above-described embodiment one of a kind of chip embedded encapsulating structure of the present invention, see Fig. 4 A to 4P, its technique comprises the steps:
Step one, see Fig. 4 A, get IC wafers 100, its surface is provided with chip electrode 13 and related circuit layout, and the chip surface passivation layer 15 being covered in IC wafers 100 upper surface offers the upper surface of chip surface passivation layer opening 151 exposed chip electrode 13 above chip electrode 13;
Step 2, see Fig. 4 B, first nickel coating Gold plated Layer again in chip surface passivation layer opening 151, forms the ni/au layers 17 of filling up chip surface passivation layer opening 151;
Step 3, see Fig. 4 C and 4D, carry out parameter testing to IC wafers 100, reduction process is carried out at the back side of qualified IC wafers 100, and its thickness thinning is determined according to actual conditions, then cuts into plural independently chip monomer 10;
Step 4, see Fig. 4 E, the prop carrier body T11 of prop carrier T1 pastes stripping film T13, and stripping film T13 can be UV stripping film, can also be hot stripping film, and this stripping film T13 is stripped in subsequent technique;
Step 5, see Fig. 4 F, by the chip monomer 10 of test passes, upside-down mounting is on prop carrier T1 in an orderly manner, and the front of chip monomer 10 is fixed by stripping film T13 and prop carrier body T11, and the distance between adjacent two chip monomers 10 needs to carry out arranging and increasing according to actual process;
Step 6, see Fig. 4 G, prop carrier T1 pastes thin film encapsulation chip monomer 10, form thin film encapsulation body 3, paste process entails to carry out under vacuum conditions, and by film heating to 175 ~ 185 DEG C, when making it be in molten condition, complete gapless attaching process;
Step 7, see Fig. 4 H, is bonded to another surface of thin film encapsulation body 3 by silica-based stiffener 7, and upper and lower 180 degree of upsets;
Step 8, see Fig. 4 I, by stripping technology, peels off the surface of chip monomer 10 and thin film encapsulation body 3, and cleans the surface of chip monomer 10, and remove residue, expose the upper surface of ni/au layers 17 by prop carrier body T11 and stripping film T13;
Step 9, see Fig. 4 J, pastes insulating thin layer I 51 at the upper surface of chip monomer 10 and the upper surface of thin film encapsulation body 3;
Step 10, see Fig. 4 K, utilizes laser etching process or photoetching process formation insulating thin layer I opening 511 to expose the upper surface of ni/au layers 17;
Step 11, see Fig. 4 L and 4M, utilizes the ripe layer process of wiring metal again to form interconnection metal layer 41 again, is provided with input/output terminal 411, covers insulating thin layer II 52, and expose input/output terminal 411 at the outermost layer of interconnection metal layer 41 again;
Step 12, see Fig. 4 N, form connector 6 at input/output terminal 411 place of interconnection metal layer 41 again, connector 6 can be soldered ball projection, welding block or other metal connecting piece;
Step 13, by thinning for the lower surface of silica-based stiffener 7, silica-based stiffener 7 can leave certain thickness h, see Fig. 4 O, the chip embedded encapsulating structure completed above by wafer level technique is cut along line of cut 8, forms plural independently packaging body, as shown in Fig. 4 P.
The additive with functions such as that resist warping, antistatic, reinforcement particles is added in thin film encapsulation body 3 in above-mentioned steps six, strengthen the proper property of thin film encapsulation body 3, the silica-based stiffener 7 of step 13 can be made to remove completely, to make the thickness of whole encapsulating structure thinning further, again the chip embedded encapsulating structure completed above by wafer level technique is cut along line of cut 8, form plural independently packaging body, as shown in Fig. 4 Q.
Embodiment two, see Fig. 5 A and Fig. 5 B
The number of chip monomer can be more than one, adopts chip package system collaborative design, can realize the chip package of more difference in functionalitys.
Fig. 5 A is the generalized section of the embodiment two of a kind of chip embedded encapsulating structure of the present invention, and chip embedded encapsulating structure of the present invention comprises chip monomer 10 and the chip monomer 20 that two back sides embed thin film encapsulation body 3, and its upper surface is generally flush formation.The material of thin film encapsulation body 3 includes but not limited to epoxy-plastic packaging material; it is generally curing agent with High Performance Phenolic Resins; adding silicon powder etc. is filler; and add multiple additive mixture and form; it is first in molten condition at high temperature 175 ~ 185 DEG C; all around four faces and the back side of tight parcel chip monomer 10; can harden gradually after cooling; final molding; all around four faces and the back side of chip monomer 10 and chip monomer 20 is made all to obtain physics and electic protection; prevent external interference, to improve its reliability.
The upper surface of the chip body 11 of chip monomer 10 is provided with chip electrode 13 and related circuit layout thereof, chip surface passivation layer 15 covers the upper surface of chip body 11 and offers chip surface passivation layer opening 151, the upper surface exposed chip surface passivation layer opening 151 of chip electrode 13, and filling first forms the ni/au layers 17 that nickel dam forms layer gold again in chip surface passivation layer opening 151.The upper surface of the chip body 21 of chip monomer 20 is provided with chip electrode 23 and related circuit layout thereof, chip surface passivation layer 25 covers the upper surface of chip body 21 and offers chip surface passivation layer opening 251, the upper surface exposed chip surface passivation layer opening 251 of chip electrode 23, and filling first forms the ni/au layers 27 that nickel dam forms layer gold again in chip surface passivation layer opening 251.Insulating thin layer I 51 covers the upper surface of chip monomer 10, the upper surface of chip monomer 20 and the upper surface of thin film encapsulation body 3, and offer insulating thin layer I opening 511 in the upper surface of ni/au layers 17, the size of insulating thin layer I opening 511 is not more than the size of chip surface passivation layer opening 151, chip surface passivation layer opening 251, the rounded or polygon such as quadrangle, hexagon of the shape of its cross section.
Interconnection metal layer 41 is formed at the upper surface of insulating thin layer I 51 and fills insulating thin layer I opening 511 again.Interconnection metal layer 41 realizes being electrically connected with chip electrode 13, chip electrode 23 by ni/au layers 17 respectively again.Also can implant the metal column that copper etc. has conducting function in insulating thin layer I opening 511, this metal column connects interconnection metal layer 41 and ni/au layers 17 again, realizes being electrically connected.Interconnection metal layer 41 can be individual layer again, and as shown in Figure 5A, the part of chip monomer 10 and chip monomer 20 adjacent again interconnection metal layer 41 is connected chip monomer 10 and chip monomer 20 simultaneously, makes to realize between chip monomer 10 and chip monomer 20 being electrically connected.In actual package structure, if the number of chip monomer is more than three or three, non-conterminous but also can realize being electrically connected by interconnection metal layer again between two or more chip electrodes be associated.Be provided with several input/output terminals 411 at the outermost layer of interconnection metal layer 41 again, the parameter such as number, position, shape of input/output terminal 411 is arranged according to actual needs.Connector 6 can be formed at input/output terminal 411 place; connector 6 can be solder bumps, welding block or other metal connecting piece; solder bumps for connector 6 in Fig. 5 B; show the front schematic view of chip monomer 10, chip monomer 20 and the position relationship of thin film encapsulation body 3, solder bumps; visible chip monomer 10, chip monomer 20 are arranged at the inside of thin film encapsulation body 3; it all obtains physics and electic protection in four faces and the back side all around, improves its reliability.
The back side of thin film encapsulation body 3 arranges the silica-based stiffener 7 of silicon material, not only further enhance the intensity of thin film encapsulation body 3, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer 10, chip monomer 20, also contribute to the reliability improving encapsulating products.
The method for packing of above-described embodiment two and the method for packing of embodiment one similar, difference is: again interconnection metal layer 41 need to set up between chip monomer 10 and chip monomer 20 connect, realize the electric connection of whole encapsulating structure.
Embodiment three, see Fig. 6
The encapsulating structure of embodiment three and embodiment one, embodiment two are similar, and difference is: interconnection metal layer 41 also can form plural layer Wiring technique layer again for two-layer or two-layer above again, to realize the fan-out packaging structure of multilayer, as shown in Figure 6.Plural layer again Wiring technique layer with three layers of example; comprise again interconnection metal layer 411, again interconnection metal layer 413, again interconnection metal layer 415; be communicated with to meet multi information; and insulating thin layer II 52 is also multilayer; with plural layer again Wiring technique layer mate; be separately positioned on wherein, play the effects such as insulation, protection, reinforcing.The material of insulating thin layer II 52 is generally the macromolecule such as epoxy resin, polyimides organic insulating material.Be provided with input/output terminal at the outermost layer of plural layer Wiring technique layer again, the number of input/output terminal is arranged according to actual needs.Plural layer again Wiring technique layer 4 input/output terminal place formed connector 6, connector 6 can be solder bumps, welding block or other metal connecting piece.
The method for packing of the method for packing of above-described embodiment three and embodiment one, embodiment two is similar, and difference is: plural layer again Wiring technique layer needs by repeatedly interconnection metal layer process forming again.
A kind of chip embedded encapsulation of the present invention and method for packing thereof are not limited to above preferred embodiment, chip monomer 10 of the present invention, chip monomer 20 is for IC chip, because it can reduce body thickness effectively, improve the flexibility of encapsulation, at the advantage highly significant of slim and microminiaturized application aspect, and its good heat dispersion, the application of this encapsulation also can expand to many different fields, as wireless, optics etc., but be not limited to this, any those skilled in the art without departing from the spirit and scope of the present invention, according to any amendment that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all fall in protection range that the claims in the present invention define.
Claims (8)
1. a chip embedded encapsulating structure, it comprises the chip monomer that upper surface is provided with chip electrode and related circuit layout, the upper surface of the chip body of described chip monomer covers chip surface passivation layer and offers chip surface passivation layer opening, the upper surface exposed chip surface passivation layer opening of chip electrode
It is characterized in that: also comprise thin film encapsulation body, chip monomer described in one or more embeds in thin film encapsulation body by the back side, fill in described chip surface passivation layer opening and first form the ni/au layers that nickel dam forms layer gold again, insulating thin layer I is covered at the upper surface of described chip monomer and the upper surface of thin film encapsulation body, and offer insulating thin layer I opening in the upper surface of described ni/au layers, interconnection metal layer and insulating thin layer II is formed again at the upper surface of insulating thin layer I, described interconnection metal layer again fills insulating thin layer I opening, described interconnection metal layer again realizes being electrically connected by chip electrode described in ni/au layers and each, and optionally realize two or more association described chip electrode between electric connection, input/output terminal is provided with at the outermost layer of interconnection metal layer again, described insulating thin layer II covers interconnection metal layer again and exposes input/output terminal, connector is formed at described input/output terminal place, the back side of described thin film encapsulation body arranges silica-based stiffener.
2. the chip embedded encapsulating structure of one according to claim 1, is characterized in that: the input/output terminal of described interconnection metal layer is again arranged at the periphery of the vertical area of chip monomer.
3. the chip embedded encapsulating structure of one according to claim 1 and 2, is characterized in that: described interconnection metal layer is again single or multiple lift.
4. the chip embedded encapsulating structure of one according to claim 1, is characterized in that: the size of described insulating thin layer I opening is not more than the size of chip surface passivation layer opening.
5. the chip embedded encapsulating structure of the one according to claim 1 or 4, is characterized in that: described insulating thin layer I opening is implanted into metal column, and described metal column connects interconnection metal layer and ni/au layers again.
6. the chip embedded encapsulating structure of one according to claim 1, is characterized in that: described connector is solder bumps, welding block or metal derby.
7. a method for packing for chip embedded encapsulating structure, comprises step:
Step one, gets IC wafers, and its surface is provided with chip electrode and related circuit layout, and the chip surface passivation layer being covered in IC wafers upper surface offers the upper surface of chip surface passivation layer opening exposed chip electrode above chip electrode;
Step 2, plates ni/au layers in chip surface passivation layer opening;
Step 3, carries out parameter testing to IC wafers, and reduction process is carried out at the back side of qualified IC wafers, then cuts into plural independently chip monomer;
Step 4, the prop carrier body of prop carrier pastes stripping film;
Step 5, by chip monomer, upside-down mounting is on prop carrier in an orderly manner, and chip monomer is fixed by stripping film and prop carrier;
Step 6, under vacuum conditions, prop carrier pastes thin film encapsulation chip monomer, forms thin film encapsulation body;
Step 7, is bonded to the back side of thin film encapsulation body by silica-based stiffener, and upper and lower 180 degree of upsets;
Step 8, peels off the surface of chip monomer and thin film encapsulation body, and cleans the surface of chip monomer, and remove residue, expose the upper surface of ni/au layers by prop carrier body and stripping film;
Step 9, pastes insulating thin layer at the upper surface of chip monomer and the upper surface of thin film encapsulation body;
Step 10, utilizes laser etching process or photoetching process formation insulating thin layer I opening to expose the upper surface of ni/au layers;
Step 11, utilizes the ripe layer process of wiring metal again to form interconnection metal layer again, and be provided with input/output terminal at the outermost layer of interconnection metal layer again, insulating thin layer II covers interconnection metal layer again, and exposes input/output terminal;
Step 12, forms connector at the input/output terminal place of interconnection metal layer again;
Step 13, is thinned to silica-based stiffener by the lower surface of silica-based stiffener and leaves thickness h, the structure of the chip embedded encapsulation completed above by wafer level technique is carried out cutting and forms plural independently packaging body.
8. the method for packing of a kind of chip embedded encapsulating structure according to claim 7, is characterized in that: in step 4, and described stripping film is UV stripping film or hot stripping film.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644861A (en) * | 2017-10-27 | 2018-01-30 | 无锡吉迈微电子有限公司 | Chip cloth wire encapsulation construction and its realizes technique again |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN111128760A (en) * | 2019-12-27 | 2020-05-08 | 广东工业大学 | Chip packaging method and chip packaging structure based on fan-out type packaging process |
| CN111370323A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Method for manufacturing semiconductor device |
| CN111599694A (en) * | 2019-12-30 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN111883437A (en) * | 2020-07-03 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN111883439A (en) * | 2020-07-28 | 2020-11-03 | 南通通富微电子有限公司 | Chip packaging method |
| WO2023272645A1 (en) * | 2021-06-30 | 2023-01-05 | 深南电路股份有限公司 | Packaged chip and manufacturing method therefor, and rewiring packaged chip and manufacturing method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080088004A1 (en) * | 2006-10-17 | 2008-04-17 | Advanced Chip Engineering Technology Inc. | Wafer level package structure with build up layers |
| JP2010225648A (en) * | 2009-03-19 | 2010-10-07 | Casio Computer Co Ltd | Semiconductor device and method of manufacturing the same |
| CN102194718A (en) * | 2010-03-15 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming the same |
| CN103426850A (en) * | 2013-08-27 | 2013-12-04 | 南通富士通微电子股份有限公司 | Wafer-level chip size packaging structure |
| CN205122579U (en) * | 2015-11-20 | 2016-03-30 | 江阴长电先进封装有限公司 | Chip embedded package structure |
-
2015
- 2015-11-20 CN CN201510808355.8A patent/CN105304605A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080088004A1 (en) * | 2006-10-17 | 2008-04-17 | Advanced Chip Engineering Technology Inc. | Wafer level package structure with build up layers |
| JP2010225648A (en) * | 2009-03-19 | 2010-10-07 | Casio Computer Co Ltd | Semiconductor device and method of manufacturing the same |
| CN102194718A (en) * | 2010-03-15 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming the same |
| CN103426850A (en) * | 2013-08-27 | 2013-12-04 | 南通富士通微电子股份有限公司 | Wafer-level chip size packaging structure |
| CN205122579U (en) * | 2015-11-20 | 2016-03-30 | 江阴长电先进封装有限公司 | Chip embedded package structure |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN107644861A (en) * | 2017-10-27 | 2018-01-30 | 无锡吉迈微电子有限公司 | Chip cloth wire encapsulation construction and its realizes technique again |
| CN111370323A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Method for manufacturing semiconductor device |
| CN111128760A (en) * | 2019-12-27 | 2020-05-08 | 广东工业大学 | Chip packaging method and chip packaging structure based on fan-out type packaging process |
| CN111128760B (en) * | 2019-12-27 | 2020-09-15 | 广东工业大学 | Chip packaging method and chip packaging structure based on fan-out type packaging process |
| CN111599694A (en) * | 2019-12-30 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN111883437A (en) * | 2020-07-03 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| CN111883439A (en) * | 2020-07-28 | 2020-11-03 | 南通通富微电子有限公司 | Chip packaging method |
| CN111883439B (en) * | 2020-07-28 | 2022-07-26 | 南通通富微电子有限公司 | Chip packaging method |
| WO2023272645A1 (en) * | 2021-06-30 | 2023-01-05 | 深南电路股份有限公司 | Packaged chip and manufacturing method therefor, and rewiring packaged chip and manufacturing method therefor |
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Application publication date: 20160203 |