CN110364496A - A kind of chip-packaging structure and its packaging method - Google Patents

A kind of chip-packaging structure and its packaging method Download PDF

Info

Publication number
CN110364496A
CN110364496A CN201810322550.3A CN201810322550A CN110364496A CN 110364496 A CN110364496 A CN 110364496A CN 201810322550 A CN201810322550 A CN 201810322550A CN 110364496 A CN110364496 A CN 110364496A
Authority
CN
China
Prior art keywords
chip
slot
substrate
metal substrate
encapsulating structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810322550.3A
Other languages
Chinese (zh)
Inventor
郭学平
曹立强
于中尧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201810322550.3A priority Critical patent/CN110364496A/en
Publication of CN110364496A publication Critical patent/CN110364496A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4817—Conductive parts for containers, e.g. caps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Abstract

This application discloses a kind of chip-packaging structure and packaging methods, the encapsulating structure includes the chip groove body for accommodating microwave radio chip, the groove body includes a metal substrate, core plate of the metal substrate as the first chip slot substrate and the second chip slot substrate, so, the metal substrate can be directly as the heat sink of microwave radio chip, because metal substrate has good heating conduction, therefore, metal substrate can provide good heat dissipation channel for microwave radio chip, improve the heat dissipation performance of encapsulating structure.

Description

A kind of chip-packaging structure and its packaging method
Technical field
This application involves technical field of semiconductor encapsulation more particularly to a kind of chip-packaging structure and packaging methods.
Background technique
Microwave radio chip is the core technology of field of wireless communication, be international chip design field generally acknowledge be most difficult to design Integrated circuit kind.In all mobile phones, approximately half of chip cost derives from microwave radio chip.
Currently, the encapsulating structure of common microwave radio chip is mostly single die package, then pass through surface mount Technology (Surface Mounted Technology, SMT) realizes modular functionality on a printed-wiring board, electromagnetic shielding Function is also to be realized by way of affixed metal shielding case in SMT process.This encapsulating structure be all carried out by substrate it is scattered Heat, however the heating conduction of existing substrate is poor, so as to cause the heat dissipation performance of the single die package of microwave radio chip It is poor.
Summary of the invention
In view of this, this application provides a kind of chip-packaging structure and its packaging method, to improve dissipating for encapsulating structure Hot property and integrated level.
In order to solve the above-mentioned technical problem, the application adopts the technical scheme that
A kind of chip-packaging structure, comprising:
Chip groove body, the chip groove body include metal substrate and be sequentially located on metal substrate first surface first Adhesive layer and the first chip slot substrate；It is provided on the first chip slot substrate and matched first chip of the first chip size Slot；Be provided on first adhesive layer with matched first notching construction of the first chip slot size,
The first chip being set on first chip slot and the first notching construction bottom surface；First chip and institute It states and is electrically connected between metal substrate；
And it is set to first lamination dielectric layer of the first chip slot substrate on the surface of the metal substrate, The first lamination dielectric layer is for coating first chip.
Optionally, the laminated stack chip groove body further include:
The second adhesive layer and the second chip slot substrate being sequentially located on metal substrate second surface；Wherein, the metal Substrate first surface is opposite with the metal substrate second surface；It is provided on second adhesive layer and the second chip slot size Matched second notching construction is provided with and matched second chip slot of the second chip size on the second chip slot substrate；
The encapsulating structure further include:
The second chip being set on second chip slot and the second notching construction bottom surface；Second chip and institute It states and is electrically connected between metal substrate；
And it is set to second lamination dielectric layer of the second chip slot substrate on the surface of the metal substrate, The second lamination dielectric layer is for coating second chip.
Optionally, the encapsulating structure further include: through the first lamination dielectric layer, chip groove body and the second lamination The through-hole interconnection of dielectric layer upper and lower surface, the through-hole interconnection are located at the outer of first chip slot and second chip slot It encloses, metal interconnecting wires is filled in the through-hole interconnection.
Optionally, the metal interconnecting wires are co-axial interconnection lines.
Optionally, the encapsulating structure further include:
The first line layer being set on the first lamination dielectric layer, and be set on the second lamination dielectric layer The second line layer；The through-hole interconnection is electrically connected with the first line layer and second line layer.
Optionally, the encapsulating structure further include:
The first solder mask being formed on the first line layer, and the second resistance being formed on second line layer Windowing is provided with according to electrical connection demand at different locations on layer, first solder mask and second solder mask.
Optionally, the encapsulating structure further include:
The third chip at the first solder mask windowing position, the third chip and institute are set to by face-down bonding mode State the electrical connection of the first chip.
Optionally, the encapsulating structure further include: the electric connection structure being set at the second solder mask windowing position, it is described Electric connection structure is isolated between different electric connection structures by second solder mask for being electrically connected with external circuit.
Optionally, the encapsulating structure further include: through the first lamination dielectric layer, chip groove body and the second lamination The grounding through hole of dielectric layer upper and lower surface, the grounding through hole are located at the outer of first chip slot and second chip slot It encloses, metallic ground lines is filled in the through-hole interconnection.
A kind of chip packaging method, comprising:
Chip groove body is formed by lamination process for pressing, the microwave radio groove body is including at least metal substrate and successively The first adhesive layer and the first chip slot substrate on metal substrate first surface；It is provided on the first chip slot substrate With matched first chip slot of the first chip size；It is provided on first adhesive layer and the first chip slot size matched One notching construction,
The first chip is formed on the bottom surface of first chip slot, between first chip and the metal substrate Electrical connection；
It is formed on surface of the first chip slot substrate away from the metal substrate for coating first chip First lamination dielectric layer.
Optionally, the method also includes:
Third chip, the third chip and described first are formed on the first lamination dielectric layer by face-down bonding mode Chip electrical connection.
Compared to the prior art, the application has the advantages that
Based on above technical scheme it is found that in chip-packaging structure provided by the embodiments of the present application, metal substrate is as The core plate of one chip slot substrate and the second chip slot substrate, therefore, metal substrate can dissipating directly as the first, second chip Hot plate, because metal substrate has good heating conduction, therefore, metal substrate can provide good for the first, second chip Heat dissipation channel improves the heat dissipation performance of encapsulating structure.
Detailed description of the invention
In order to which the specific embodiment of the application is expressly understood, used when the application specific embodiment is described below Attached drawing do a brief description.It should be evident that these attached drawings are only the section Examples of the application.
Fig. 1 is a kind of chip-packaging structure schematic diagram provided by the embodiments of the present application；
Fig. 2 is another chip-packaging structure schematic diagram provided by the embodiments of the present application；
Fig. 3 is chip packaging method flow diagram provided by the embodiments of the present application；
Fig. 4 A to Fig. 4 J is the corresponding structural representation of processing procedures a series of in chip packaging method provided by the embodiments of the present application Figure.
Description of symbols:
101: metal substrate, 1011: filling holes with resin,
102: the first adhesive layers, 1021: the first notching constructions,
103: the first chip slot substrates,
1031: the first chip slots,
104: the first chips,
105: the first lamination dielectric layers,
106: the second adhesive layers, 1061: the second notching constructions 1061,
107: the second chip slot substrates, 1071: the second chip slots,
108: the second chips,
109: the second lamination dielectric layers,
110: through-hole interconnection,
111: metal interconnecting wires,
112: grounding through hole,
113: metallic ground lines,
114: first line layer,
115: the second line layers,
116: the first solder masks,
117: the second solder masks,
118: third chip,
119: bottom filler,
120: metal soldered ball.
Specific embodiment
As described in the background section, there are heat dissipation performance difference and integrated levels for the encapsulating structure of common microwave radio chip Low problem, in order to overcome the technical problem, the embodiment of the present application provides a kind of chip-packaging structure, in the encapsulating structure Including the chip groove body for accommodating microwave radio chip, which includes a metal substrate, and the metal substrate is as the first core The core plate of film trap substrate and the second chip slot substrate, in this way, the metal substrate can be directly as the heat dissipation of microwave radio chip Plate, because metal substrate has good heating conduction, therefore, metal substrate can provide good heat dissipation for microwave radio chip The heat dissipation performance of encapsulating structure is improved in channel.
The specific embodiment of chip-packaging structure provided by the embodiments of the present application is retouched in detail with reference to the accompanying drawing It states.
Referring to Figure 1 and Fig. 2, the encapsulating structure of microwave radio chip provided by the embodiments of the present application include:
Chip groove body, the chip groove body include metal substrate 101 and are sequentially located on 101 first surface of metal substrate First adhesive layer 102 and the first chip slot substrate 103；It is provided with and the first chip size on the first chip slot substrate 103 The first chip slot 1031 matched；It is provided on first adhesive layer 102 and matched first notching construction of the first chip slot size 1021,
The first chip 104 being set on 1021 bottom surface of first chip slot 1031 and the first notching construction；This first It is electrically connected between chip 104 and the metal substrate 101；
And it is set to first laminating media of the first chip slot substrate 103 on the surface of the metal substrate 101 Layer 105, the first lamination dielectric layer 105 is for coating first chip 104.
It is to be appreciated that in the embodiment of the present application, the size of the first chip slot 1031 and the first notching construction 1021 can be with Greater than the size of the first chip 104, opened in this way, the first lamination dielectric layer 105 can also be located at the first chip slot 1031 and first In gap between slot structure 1021 and the first chip 104, to realize the package to the first chip 104.
In addition, be provided with weld pad on the first chip 104, in order to realize that the first chip 104 and extraneous signal transmit, the Blind hole is provided on one laminating media layer 105 at position corresponding with the first chip pad, and filled with interconnection gold in the blind hole Belong to.
It is to be appreciated that in the embodiment of the present application, in order to be conducive to improve the signal transmission performance of encapsulating structure, Metal Substrate Filling holes with resin 1011 is also provided on plate 101.The aperture of the filling holes with resin 1011 is set as the first aperture.
In order to improve microwave radio chip encapsulating structure integrated level, realize the miniaturization of electronic product, can be in gold Belong to the groove being also equipped on another surface of substrate 101 for accommodating microwave radio chip, in this way, one as the application can Embodiment is selected, said chip groove body can further include: the second bonding being sequentially located on 101 second surface of metal substrate Layer 106 and the second chip slot substrate 107；Wherein, 101 first surface of metal substrate is opposite with the metal substrate second surface； It is provided on second adhesive layer 106 and matched second notching construction 1061 of the second chip slot size, the second chip slot base It is provided on plate 107 and matched second chip slot 1071 of the second chip size；
Correspondingly, encapsulating structure provided by the embodiments of the present application can further include:
The second chip 108 being set on 1061 bottom surface of second chip slot 1071 and the second notching construction；This second It is electrically connected between chip 108 and the metal substrate 101；
And it is set to second laminating media of the second chip slot substrate 107 on the surface of the metal substrate 101 Layer 109, the second lamination dielectric layer 109 is for coating second chip 108.
It is to be appreciated that in the embodiment of the present application, the size of the second chip slot 1071 and the second notching construction 1061 can be with Greater than the size of the second chip 108, opened in this way, the second lamination dielectric layer 109 can also be located at the second chip slot 1071 and second In gap between slot structure 1061 and the second chip 108, to realize the package to the second chip 108.
In addition, be provided with weld pad on the second chip 108, in order to realize that the second chip 108 and extraneous signal transmit, the Blind hole is provided on two laminating media layers 109 at position corresponding with the second chip pad, and filled with interconnection gold in the blind hole Belong to.
In this embodiment, core of the metal substrate 101 as the first chip slot substrate 103 and the second chip slot substrate 107 Plate, therefore, metal substrate 101 can be directly as the heat sinks of the first, second chip 104 and 108, because metal substrate 101 has There is good heating conduction, therefore, it is logical that metal substrate 101 can provide good heat dissipation for the first, second chip 104 and 108 Road improves the heat dissipation performance of encapsulating structure.
In addition, as another alternative embodiment of the application, above-mentioned encapsulating structure is also in order to provide the transmission performance of signal It may further include:
Through the intercommunicated of the first lamination dielectric layer 105, chip groove body and the second lamination 109 upper and lower surface of dielectric layer Hole 110, the through-hole interconnection 110 are located at the periphery of the first chip slot 1031 and second chip slot 1071, and the through-hole interconnection Be filled with metal interconnecting wires 112 in 110, the metal interconnecting wires 112 for realizing the first chip 104 and the second chip 108 electricity Connection.In order to further improve the transmission performance of signal, as an example, which can be formed in sets in advance It sets in the filling holes with resin 1011 on metal substrate 101, the aperture of the filling holes with resin 1011 is larger, under the specific example, shape It may comprise steps of at the process of through-hole interconnection: in 1011 internal drilling of filling holes with resin, forming the through-hole in the second aperture, it should The through-hole in the second aperture is through-hole interconnection 110, then fills metal into the through-hole in second aperture again, to form coaxial gold Belong to interconnection line 112.Signal transmission is carried out using the co-axial interconnection lines, is conducive to the signal transporting for improving entire encapsulating structure Energy.
It is to be appreciated that in this embodiment, by the way that the through-hole interconnection 110 inside chip slot body is arranged in, on the one hand realizing The short distance interconnection of first chip 104 and second chip 108, on the other hand relative to traditional bonding line (wire bond, WB it) is more advantageous to interconnection line impedance matching, so that interconnection or transmission performance are preferably promoted, in addition, by metal substrate 101 On large aperture filling holes with resin 1011 in production small-bore interconnected pores, form co-axial interconnection lines, it is entire to be more advantageous to raising The signal transmission performance of encapsulating structure.
In addition, in order to realize encapsulating structure and external good earth, it is above-mentioned as another alternative embodiment of the application Encapsulating structure can further include:
Ground connection through the first lamination dielectric layer 105, chip groove body and the second lamination 109 upper and lower surface of dielectric layer is logical Hole 1120, the grounding through hole 112 are located at the periphery of the first chip slot 1031 and second chip slot 1071, and the grounding through hole Metallic ground lines 113 are filled in 110.
As an example, which can be distributed in the side of encapsulating structure, and grounding through hole 112 exists respectively The other side opposite with through-hole interconnection 110, the specific structure are as shown in Figure 1.
As another example, in order to which the transmission performance and ground connection performance, the through-hole interconnection 110 that improve signal are led to ground connection Hole 112 can be distributed in the surrounding of encapsulating structure, more specifically, grounding through hole 112 is distributed in the periphery of through-hole interconnection 110, The specific structure is as shown in Figure 2.
In addition, as depicted in figs. 1 and 2, encapsulating structure provided by the embodiments of the present application can also include:
The first line layer 114 being set on the first lamination dielectric layer 105, and it is set to the second lamination dielectric layer The second line layer 115 on 109；
In addition, the electrical connection in order to realize the first chip 104 and the second chip 108, in the weld pad phase with the first chip 104 Pair first lamination dielectric layer 105 and first line layer 114 position at be provided with blind hole, in the weld pad with the second chip 108 It is also equipped with blind hole at the position of opposite the second lamination dielectric layer 109 and the second line layer 115, and is filled in the blind hole Metal is interconnected, in this way, being laminated dielectric layer 104 and the second lamination dielectric layer 109 by being set to first line layer 114, first And the second blind hole, first line layer 114, the second line layer 115 and through-hole interconnection 109 on line layer 115 may be implemented The electrical connection of first chip 104 and the second chip 108.
In addition, encapsulating structure provided by the embodiments of the present application can also include the be covered on the first line layer 114 One solder mask 116, and the second solder mask 117 being covered on second line layer 115.Wherein, the first solder mask 116 and Need to be provided with different windowings according to different electrical connections on two solder masks 117.
In addition, in order to realize level of integrated system and miniaturization, encapsulating structure provided by the embodiments of the present application to the maximum extent It can also include: the third chip 118 being set to by face-down bonding mode on first solder mask 116, the third chip 118 Weld pad such as metal soldered ball on the back side passes through windowing, first line layer 114 and the first laminating media of the first solder mask 116 Blind hole on layer 105 is electrically connected with first chip 104.In addition, in order to reduce between third chip 118 and the first chip 104 Stress, extend the service life of entire encapsulating structure, be also filled with bottom between third chip 118 and the first solder mask 116 Filler 119.
As an example, the third chip 118 can be the driving chip of encapsulating structure.
In addition, in order to realize being electrically connected for encapsulating structure and external circuit, which can also include being set to the Metal soldered ball 120 at the windowing position of two solder masks 117, passes through the second solder mask 117 between adjacent different metal soldered ball 120 It is isolated.It is to be appreciated that the metal soldered ball 120 can be BGA soldered ball.In addition, metal soldered ball is only the encapsulating structure and outside A kind of example of the electric connection structure of circuit electrical connection, as the extension of the embodiment of the present application, which can also be Metal pad, for example, LGA pad.
As the specific example of the application, metal substrate 101 can be thick base copper sheet or other simultaneous with substrate process The metal plate of appearance.The thickness of the metal substrate 101 is thicker, generally at 100 microns or more.
Core plate of the metal substrate 101 as the first chip slot substrate 103 and the second chip slot substrate 106, can be straight Ground connection, so that the good earth for the first chip 104 and the second chip 108 provides possibility.In addition, the metal substrate 101 has There is good heating conduction, therefore, also provides good heat dissipation channel for the first chip 104 and the second chip 108, improve The heat dissipation performance of encapsulating structure.
As another specific example, the first adhesive layer 102 and the second adhesive layer 106 are generally printed wiring board (Printed Circuit Board, PCB) it uses or substrate prepreg, such as can be for FR-4, BT etc..
When forming chip groove body in order to avoid pressing, the intracorporal excessive glue of slot influences the attachment of microwave radio chip, is set to The first notching construction size on first adhesive layer 102 is slightly larger than the first chip slot size, is set on the second adhesive layer 106 Second notching construction size is slightly larger than the second chip slot size.In addition, the first notching construction size also with the first adhesive layer 102 Material type is related, and similarly, the second notching construction size is also related to the material type of the second adhesive layer 106.Therefore, it first opens Quantitative relationship and the second notching construction size and the second chip slot size between slot structure size and the first chip slot size Between quantitative relationship to be determined according to the material type of laminating media layer.
First chip 104 and the second chip 108 can be specially microwave radio chip, or power chip, more Body, the first, second chip 104 and 108 can be GaAs chip.Moreover, the first chip 104 and the second chip 108 can lead to It crosses conducting resinl attachment or sintering process is realized and the interconnection of metal substrate 101.
The above are the specific implementations of microwave radio chip-packaging structure provided by the embodiments of the present application.The specific implementation The encapsulating structure of mode is with the following functions:
1) good earth: metal substrate 101 can be directly grounded, and two microwave radio chips are passed through conductive attachment simultaneously Or sintering process is realized and is interconnected with metal substrate, and good earth effect is formed, in addition, further, it is real using grounding through hole 112 Existing encapsulating structure and external good earth effect.
2) excellent heat dispersion performance: metal substrate 101 is directly as the first chip slot substrate 103 and the second chip slot substrate 106 core plate can be used as the heat sink of the first chip 104 and the second chip 108, because metal substrate 101 heating conduction compared with It is good, therefore, heat dissipation channel can be more preferably provided, improve heat dissipation performance.
3) short distance interconnection and coaxial interconnection: the first chip 104 and the second chip 108 are directly realized mutually by route in plate Even, short distance interconnection on the one hand may be implemented, on the other hand interconnection line impedance matching is more conducive to relative to traditional WB line, thus more It is good to promote interconnection or transmission performance；In addition, through-hole interconnection can pass through the resin plug for the large aperture being arranged on metal substrate 101 Aperture production is bored in hole, then, then forms co-axial interconnection lines in aperture, which is more conducive to improve signal transporting Energy.
4) good electromagnetic shielding: the encapsulating structure is embedding by microwave radio chip, realizes microwave radio chip Full package structure, realized between different microwave radio chips the first chip and the second chip of setting (specially upper and lower level) Fine Isolated Shield effect, improves the electromagnetic shielding performance of microwave radio chip module.
5) integrated level at low cost is high: the chips such as driving are formed by face-down bonding mode in the periphery of encapsulating structure, it can Level of integrated system and miniaturization are realized to greatest extent, in addition the packaging technology can be directly based upon the technique processing of organic substrate, With low cost, it is suitable for the requirement of scale volume production.
The chip-packaging structure provided based on the above embodiment, the embodiment of the present application also provides a kind of chip package sides Method.
Chip packaging method provided by the embodiments of the present application is described in detail below with reference to Fig. 3 to Fig. 4 J.
As shown in figure 3, chip packaging method provided by the embodiments of the present application includes:
S301: it forms chip groove body: chip groove body being formed by lamination process for pressing, the chip groove body is from top to bottom successively Including the first chip slot substrate 103, the first adhesive layer 102, metal substrate 101, the second adhesive layer 106 and the second chip slot substrate 107。
This step can specifically include:
A1: by the first chip slot substrate 103 made, the first adhesive layer 102, metal substrate 101, the second adhesive layer 106 and second chip slot substrate 107 align be stacked together in the order described above, form laminated construction.
As shown in Figure 4 A, in the embodiment of the present application, it is provided with and the first core on the first chip slot substrate 103 made Matched first chip slot 1031 of chip size.
It is provided on first adhesive layer 102 made and matched first notching construction of the first chip slot size 1021, wherein when forming chip groove body in order to avoid pressing, the intracorporal excessive glue of slot influences the attachment of the first chip, is set to the The first notching construction size on one adhesive layer 102 is slightly larger than the first chip slot size, in addition, the first notching construction size also with The material type of first adhesive layer 102 is related.
It is provided on the second adhesive layer 106 made and matched second notching construction 1061 of the second chip slot size.
It is provided on the second chip slot substrate 107 made and matched second chip slot 1071 of the second chip size； When forming chip groove body in order to avoid pressing, the intracorporal excessive glue of slot influences the attachment of the second chip, is set to the second adhesive layer 106 On the first notching construction size be slightly larger than the first chip slot size, in addition, the second notching construction size also with the second adhesive layer 106 material type is related.
As an example, metal substrate 101 can be with copper metal plate or other metal plates compatible with substrate process.The metal Substrate 101 has thicker thickness, is generally not less than 100~1040 microns.In addition, for the subsequent system for facilitating through-hole interconnection Make, could be formed with the macroporous structure for being plugged with resin on the metal substrate 101.
As another example, the first adhesive layer 102 and the second adhesive layer 106 can be used for substrate or pcb board half is consolidated Change piece.
It is to be appreciated that in the laminated construction that this step A1 is formed, the first chip slot 1031 and the first notching construction 1021 It is opposite up and down.Second chip slot 1071 and the second notching construction about 1061 are opposite, so could be by the first chipset mounted in the In one chip slot 1031, by the second chipset in the second chip slot 1071.
A2: each layer structure in above-mentioned laminated construction is pressed together using lamination process for pressing, the integral knot of shape Structure.
This step can be with specifically: using lamination process for pressing customary in the art by each layer knot in above-mentioned laminated construction Structure presses together, and forms an overall structure.The overall structure is as shown in Figure 4 B.
During the pressing process, the first adhesive layer 102 and the second adhesive layer 106 play the role of key.This first, second Adhesive layer 102 and 106 all has cementation, wherein a surface of the first adhesive layer 102 can be with the of metal substrate 101 One surface is bonded together, and another surface can be bonded together with the lower surface of the first chip slot 103.Second adhesive layer 106 One side can be bonded together with the second surface of metal substrate 101, another side can be with the lower surface of the second chip slot 107 It is bonded together.In this way, passing through the cementation of the first adhesive layer 102 and the second adhesive layer 106, by above layers construction bonds It presses together, forms an overall structure.
S302: the first, second chip attachment: forming the first chip 104 on the bottom surface of the first chip slot 1031, this It is electrically connected between one chip 104 and the metal substrate 101；The second chip is formed on the bottom surface in the second chip slot 1071 108, it is electrically connected between second chip 108 and the metal substrate 101.
This step can be with specifically: first in 1031 bottom surface of the first chip slot and in the bottom surface of the second chip slot 1071 On carry out a conducting resinl or formed it is other it is conductive can adhesive layer, then, according to conducting resinl or it is other have lead The technological parameter of the binding material of electrical property mounts upper first chip 104 on 1031 bottom surface of the first chip slot, second Upper second chip 108 is mounted on the bottom surface of chip slot 1071.When mounting the first chip 104 and the second chip 108, make first Back gold on 104 back side of chip is electrically connected with the bottom surface of the first chip slot 1031, make back gold on 108 back side of the second chip and It is electrically connected on the bottom surface of the second chip slot 1071.
The size of first chip 104 can be less than the size of the first chip slot 1031, in this way, mounting to the first chip 104 After the completion, there are gaps between the first chip 104 and the first chip slot 1031.Similarly, in the second chip 108 and the second chip There may also be gaps between slot 1071.
It is electrically connected between first chip 104 and metal substrate 101, is electrically connected between the second chip 108 and metal substrate 101 It connects.
It is as shown in Figure 4 C that the step has executed corresponding the schematic diagram of the section structure.
The lamination of S303: the first, second chip is embedding: deviating from the table of the metal substrate 101 in the first chip slot substrate 103 The first lamination dielectric layer 105 for coating first chip 104 is formed on face, deviating from the second chip slot substrate 107 should The second lamination dielectric layer 109 for coating second chip 108 is formed on the surface of metal substrate 101.
This step can be with specifically: on two surfaces of chip groove body for being pasted with the first chip 104 and the second chip 108 It is respectively formed the first lamination dielectric layer 105 and the second lamination dielectric layer 109, to realize the first chip 104 and the second chip 108 it is embedding.Effect is preferably wrapped up to the first, second chip in order to realize, is used to form the first lamination dielectric layer 105 and The material of two laminating media layers 109 has preferable filling capacity, as an example, being used to form 105 He of the first lamination dielectric layer The material of second dielectric layer 109 can use for PCB or substrate semi-solid preparation material.
In the embodiment of the present application, the size of the first chip slot 1031 and the first notching construction 1021 can be greater than the first core The size of piece 104, in this way, during the pressing process, the material for being used to form the first lamination dielectric layer 105 can be extruded to first In gap between chip slot 1031 and the first notching construction 1021 and the first chip 104, in this way, the first lamination dielectric layer 105 It can also include the portion in the gap between the first chip slot 1031 and the first notching construction 1021 and the first chip 104 Point, to realize the package to the first chip 104.
Similarly, during the pressing process, the material for being used to form the second lamination dielectric layer 109 can be extruded to the second chip In gap between slot 1071 and the second notching construction 1061 and the second chip 108, in this way, the second lamination dielectric layer 109 may be used also To include the part in the gap between the second chip slot 1071 and the second notching construction 1061 and the second chip 108, from And realize the package to the second chip 108.
It is as shown in Figure 4 D that the step has executed corresponding the schematic diagram of the section structure.
S304: through-hole interconnection and grounding through hole are formed: is formed through the first lamination dielectric layer 105, chip groove body and the The through-hole interconnection 110 and grounding through hole 112 of two laminating media layers, 109 upper and lower surface.
In order to realize the preferable interconnection performance of the first chip 104 and the second chip 108, by the way of machine drilling, It is formed in the peripheral region of the first chip slot 1031 and second chip slot 1071 through the first lamination dielectric layer 105, core The through-hole interconnection 110 of piece groove body and the second lamination 109 upper and lower surface of dielectric layer.
It, can also be by the way of machine drilling, in the first chip in order to realize encapsulating structure and external good earth In the peripheral region of slot 1031 and second chip slot 1071 formed through first lamination dielectric layer 105, chip groove body and The grounding through hole 112 of second lamination 109 upper and lower surface of dielectric layer.
In order to simplify technique, through-hole interconnection 110 can be formed simultaneously with grounding through hole 112.
It is as shown in Figure 4 E that the step has executed corresponding the schematic diagram of the section structure.It is to be appreciated that structure shown in Fig. 4 E is Through-hole interconnection 110 is formed in the side of encapsulating structure, and grounding through hole 112 is formed in the other side of encapsulating structure.
In addition, another embodiment as the application, intercommunicated in order to improve the transmission performance and ground connection performance of signal Hole 110 and grounding through hole 112 can be distributed in the surrounding of encapsulating structure, more specifically, grounding through hole 112 be distributed in it is intercommunicated The periphery in hole 110.
It is to be appreciated that after making the filling holes with resin in the first aperture on metal substrate 101, in order to improve the transmission of signal Performance, through-hole interconnection 110 can form the corresponding position of filling holes with resin, and specific formed may comprise steps of:: in resin plug The corresponding position drilling in hole is formed through the first lamination dielectric layer 105, chip groove body and the second about 109 dielectric layer of lamination The through-hole in second aperture on surface, the through-hole in second aperture are through-hole interconnection 110.
S305: metal interconnecting wires 111 are formed in through-hole interconnection 110, form metallic ground lines in grounding through hole 112 113:
In order to realize the interconnection of the first chip 104 and the second chip 108, it is also necessary to fill metal into through-hole interconnection 110 Form metal interconnecting wires 111.It is to be appreciated that when through-hole interconnection 110 is by boring hole-shaped on the filling holes with resin in the first aperture At when, S306 formed metal interconnecting wires 111 be coaxial metal interconnection line, so, it is possible improve signal transmission performance.
In order to realize encapsulating structure and external good earth, metallic ground lines 113 are formed in grounding through hole 112.
As an example, this step can with specifically includes the following steps:
Metal is filled into through-hole interconnection 110 and grounding through hole 112 by electroplating technology first, forms metal interconnecting wires 111 and metallic ground lines 113, filling holes with resin is then realized by screen printing mode again, and the remaining resin in surface layer is removed, Then the first lamination dielectric layer 105 and the second lamination dielectric layer are realized by laser drilling process in the corresponding position of chip pad The processing and fabricating of blind hole on 109.
The step has executed corresponding the schematic diagram of the section structure as illustrated in figure 4f.
S306: production line layer: first line layer 114 is made on the first lamination dielectric layer 105, in the second laminating media The second line layer 115 is made on layer 109.
This step can be with specifically: is making First Line on the first lamination dielectric layer 105 by subtraction or plate addition process Road floor 114 makes the second line layer 115 on the second lamination dielectric layer 109.
Subtractive processes are exactly the plating metal copper for first carrying out whole plate, then carry out pattern mask and make laggard row metal etching Line layer required for being formed.
And semi-additive process is first to carry out one layer of seed layer production, and the system of graphic mask is then carried out by exposure development Make and then wants figure with will perform etching to obtain after exposure mask removing removal after exposure mask progress graphic plating.
It is to be appreciated that can also be laminated on dielectric layer 105 and the first chip pad pair first before making line layer Blind hole is formed by laser drilling process at the position answered, it is corresponding with the second chip pad on the second lamination dielectric layer 109 Blind hole (it is as shown in Figure 4 G that the step has executed corresponding the schematic diagram of the section structure) is formed by laser drilling process at position.Such as This can also fill metal into the blind hole for being produced on the first lamination dielectric layer 105 while making first line layer 114, To realize the interconnection of signal.It, can also be to being produced on the second lamination dielectric layer 109 while making the second line layer 115 Interior filling metal, to realize the interconnection of signal.The step has executed corresponding the schematic diagram of the section structure as shown at figure 4h.
S307: production solder mask: the first solder mask 116 is made on first line layer 114, on the second line layer 115 Make the second solder mask 117.
The first solder mask 116 is made on first line layer 114 of technological means customary in the art, in the second route The second solder mask 117 is made on layer 115, and according to different electrical connection needs, the first solder mask 116 and the second solder mask 117 On be provided with different windowings.The step has executed corresponding the schematic diagram of the section structure as shown in fig. 41.
S308: chip face-down bonding: forming third chip 118 by face-down bonding mode on the first solder mask 116, should Third chip 118 is electrically connected with first chip 104.
In order to realize the integrated level of encapsulating structure, this step can by face-down bonding mode on the first solder mask 116, Third chip 118 is formed, which passes through windowing, first line layer 114 and the first layer of the first solder mask 116 Blind hole on pressure dielectric layer 105 is electrically connected with first chip 104.In addition, in order to reduce third chip 118 and the first chip Stress between 104 extends the service life of entire encapsulating structure, also fills out between third chip 118 and the first solder mask 116 Filled with bottom filler 119.
As an example, the third chip 118 can be the driving chip of encapsulating structure.
The step has executed corresponding the schematic diagram of the section structure as shown in fig. 4j.
S309: it plants metal soldered ball: planting metal soldered ball 120 at the windowing position of the second solder mask 117, pass through the metal welding The realization encapsulating structure of ball 120 is electrically connected with external circuit.
In order to realize being electrically connected for encapsulating structure and external circuit, which can also include:
Metal soldered ball 120 is planted at the windowing position of the second solder mask 117, and encapsulation knot is realized by the metal soldered ball 120 Structure is electrically connected with external circuit.It is isolated between adjacent different metal soldered ball 120 by the second solder mask 117.It is to be appreciated that Metal soldered ball is only a kind of example for the electric connection structure that the encapsulating structure is electrically connected with external circuit, as the embodiment of the present application Extension, which can also be metal pad.
It is as shown in Figure 1 or 2 that the step has executed corresponding the schematic diagram of the section structure.
The above are the specific implementations of chip packaging method provided by the embodiments of the present application.It, should in the packaging method Packaging method can be directly based upon the technique processing of organic substrate, have low cost, be suitable for the requirement of scale volume production.
The above are specific embodiments provided by the embodiments of the present application.The protection scope of the application is not limited to described above Specific embodiment, the technical solution obtained to the modification of above-mentioned specific embodiment, replacement is in the protection scope of the application Column.

Claims (11)

1. a kind of chip-packaging structure characterized by comprising
Chip groove body, the chip groove body include metal substrate and the first bonding being sequentially located on metal substrate first surface Layer and the first chip slot substrate；It is provided on the first chip slot substrate and matched first chip slot of the first chip size； Be provided on first adhesive layer with matched first notching construction of the first chip slot size,
The first chip being set on first chip slot and the first notching construction bottom surface；First chip and the gold Belong to and being electrically connected between substrate；
And it is set to first lamination dielectric layer of the first chip slot substrate on the surface of the metal substrate, it is described First lamination dielectric layer is for coating first chip.
2. encapsulating structure according to claim 1, which is characterized in that the laminated stack chip groove body further include:
The second adhesive layer and the second chip slot substrate being sequentially located on metal substrate second surface；Wherein, the metal substrate First surface is opposite with the metal substrate second surface；It is provided on second adhesive layer and is matched with the second chip slot size The second notching construction, be provided with and matched second chip slot of the second chip size on the second chip slot substrate；
The encapsulating structure further include:
The second chip being set on second chip slot and the second notching construction bottom surface；Second chip and the gold Belong to and being electrically connected between substrate；
And it is set to second lamination dielectric layer of the second chip slot substrate on the surface of the metal substrate, it is described Second lamination dielectric layer is for coating second chip.
3. encapsulating structure according to claim 2, which is characterized in that the encapsulating structure further include: run through described first The through-hole interconnection of laminating media layer, chip groove body and the second lamination dielectric layer upper and lower surface, the through-hole interconnection is located at described The periphery of first chip slot and second chip slot, the through-hole interconnection is interior to be filled with metal interconnecting wires.
4. encapsulating structure according to claim 3, which is characterized in that the metal interconnecting wires are co-axial interconnection lines.
5. encapsulating structure according to claim 1-4, which is characterized in that the encapsulating structure further include:
The first line layer being set on the first lamination dielectric layer, and be set on the second lamination dielectric layer the Two line layers；The through-hole interconnection is electrically connected with the first line layer and second line layer.
6. encapsulating structure according to claim 5, which is characterized in that the encapsulating structure further include:
The first solder mask being formed on the first line layer, and the second welding resistance being formed on second line layer Layer, windowing is provided with according to electrical connection demand at different locations on first solder mask and second solder mask.
7. structure according to claim 6, which is characterized in that the encapsulating structure further include:
The third chip that the first solder mask opens a window at position, the third chip and described the are set to by face-down bonding mode The electrical connection of one chip.
8. structure according to claim 5, which is characterized in that the encapsulating structure further include: be set to the second solder mask Electric connection structure at windowing position, the electric connection structure with external circuit for being electrically connected, between different electric connection structures It is isolated by second solder mask.
9. encapsulating structure according to claim 1-4, which is characterized in that the encapsulating structure further include: run through The grounding through hole of the first lamination dielectric layer, chip groove body and the second lamination dielectric layer upper and lower surface, the grounding through hole Metallic ground lines are filled in the periphery of first chip slot and second chip slot, the through-hole interconnection.
10. a kind of chip packaging method characterized by comprising
Chip groove body is formed by lamination process for pressing, the microwave radio groove body includes at least metal substrate and is sequentially located at The first adhesive layer and the first chip slot substrate on metal substrate first surface；It is provided on the first chip slot substrate and the Matched first chip slot of one chip size；It is provided on first adhesive layer and is opened with the first chip slot size matched first Slot structure,
The first chip is formed on the bottom surface of first chip slot, is electrically connected between first chip and the metal substrate It connects；
The for coating first chip is formed on surface of the first chip slot substrate away from the metal substrate One laminating media layer.
11. according to the method described in claim 10, it is characterized in that, the method also includes:
Third chip, the third chip and first chip are formed on the first lamination dielectric layer by face-down bonding mode Electrical connection.
CN201810322550.3A 2018-04-11 2018-04-11 A kind of chip-packaging structure and its packaging method Pending CN110364496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810322550.3A CN110364496A (en) 2018-04-11 2018-04-11 A kind of chip-packaging structure and its packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810322550.3A CN110364496A (en) 2018-04-11 2018-04-11 A kind of chip-packaging structure and its packaging method

Publications (1)

Publication Number Publication Date
CN110364496A true CN110364496A (en) 2019-10-22

Family

ID=68214659

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810322550.3A Pending CN110364496A (en) 2018-04-11 2018-04-11 A kind of chip-packaging structure and its packaging method

Country Status (1)

Country Link
CN (1) CN110364496A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112349700A (en) * 2020-09-28 2021-02-09 中国电子科技集团公司第二十九研究所 Airtight high heat conduction LCP packaging substrate and multi-chip system level packaging structure
CN112512205A (en) * 2020-12-15 2021-03-16 深圳市诚之益电路有限公司 PCBA mainboard and intelligent robot
CN113271709A (en) * 2021-03-25 2021-08-17 中国电子科技集团公司第二十九研究所 Multilayer printed circuit laminated structure and packaging structure of metal core plate
CN114121823A (en) * 2021-11-19 2022-03-01 中国电子科技集团公司第二十九研究所 Airtight packaging structure of embedded metal matrix composite substrate

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798564A (en) * 1995-12-21 1998-08-25 Texas Instruments Incorporated Multiple chip module apparatus having dual sided substrate
US6410977B1 (en) * 1997-12-12 2002-06-25 Seiko Epson Corporation Semiconductor device, circuit board electronic instrument and method of making a semiconductor device
US20060055017A1 (en) * 2004-09-10 2006-03-16 Jeong-Hyeon Cho Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted
CN1791305A (en) * 2004-12-06 2006-06-21 阿尔卑斯电气株式会社 Circuit component module, electronic circuit device, and method for manufacturing the circuit component module
US20060273458A1 (en) * 2005-06-07 2006-12-07 Wen-Shien Huang Substrate structure of semiconductor package
CN101819964A (en) * 2009-02-27 2010-09-01 株式会社电装 Integrated circuit mounted board, printed wiring board and manufacturing integrated circuit mounted board method
CN105161474A (en) * 2015-07-08 2015-12-16 华进半导体封装先导技术研发中心有限公司 Fan-out packaging structure and production technology thereof
US20160322315A1 (en) * 2015-04-30 2016-11-03 Thales Moisture-resistant electronic component, notably microwave, and method for packaging such a component
CN106206488A (en) * 2015-05-27 2016-12-07 钰桥半导体股份有限公司 The heat-dissipating gain-type of built-in radiating seat faces surface semiconductor group body and manufacture method

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798564A (en) * 1995-12-21 1998-08-25 Texas Instruments Incorporated Multiple chip module apparatus having dual sided substrate
US6410977B1 (en) * 1997-12-12 2002-06-25 Seiko Epson Corporation Semiconductor device, circuit board electronic instrument and method of making a semiconductor device
US20060055017A1 (en) * 2004-09-10 2006-03-16 Jeong-Hyeon Cho Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted
CN1791305A (en) * 2004-12-06 2006-06-21 阿尔卑斯电气株式会社 Circuit component module, electronic circuit device, and method for manufacturing the circuit component module
US20060273458A1 (en) * 2005-06-07 2006-12-07 Wen-Shien Huang Substrate structure of semiconductor package
CN101819964A (en) * 2009-02-27 2010-09-01 株式会社电装 Integrated circuit mounted board, printed wiring board and manufacturing integrated circuit mounted board method
US20160322315A1 (en) * 2015-04-30 2016-11-03 Thales Moisture-resistant electronic component, notably microwave, and method for packaging such a component
CN106206488A (en) * 2015-05-27 2016-12-07 钰桥半导体股份有限公司 The heat-dissipating gain-type of built-in radiating seat faces surface semiconductor group body and manufacture method
CN105161474A (en) * 2015-07-08 2015-12-16 华进半导体封装先导技术研发中心有限公司 Fan-out packaging structure and production technology thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112349700A (en) * 2020-09-28 2021-02-09 中国电子科技集团公司第二十九研究所 Airtight high heat conduction LCP packaging substrate and multi-chip system level packaging structure
CN112349700B (en) * 2020-09-28 2023-05-09 中国电子科技集团公司第二十九研究所 Airtight high heat conduction LCP packaging substrate and multi-chip system level packaging structure
CN112512205A (en) * 2020-12-15 2021-03-16 深圳市诚之益电路有限公司 PCBA mainboard and intelligent robot
CN113271709A (en) * 2021-03-25 2021-08-17 中国电子科技集团公司第二十九研究所 Multilayer printed circuit laminated structure and packaging structure of metal core plate
CN114121823A (en) * 2021-11-19 2022-03-01 中国电子科技集团公司第二十九研究所 Airtight packaging structure of embedded metal matrix composite substrate

Similar Documents

Publication Publication Date Title
US8952526B2 (en) Stackable semiconductor assembly with bump/flange heat spreader and dual build-up circuitry
CN104170076B (en) Electronic Packaging for millimeter wave semiconductor die
US8841171B2 (en) Method of making stackable semiconductor assembly with bump/flange heat spreader and dual build-up circuitry
US9331030B1 (en) Integrated antenna package and manufacturing method thereof
US8343808B2 (en) Method of making stackable semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8614502B2 (en) Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device
CN110364496A (en) A kind of chip-packaging structure and its packaging method
TWI559443B (en) Integrated circuit packaging system with post type interconnector and method of manufacture thereof
US6731014B2 (en) Semiconductor package substrate, semiconductor package
CN105789847B (en) Aerial integration formula encapsulating structure and its manufacturing method
CN107123601B (en) High-heat-dissipation device packaging structure and board-level manufacturing method
CN209029359U (en) A kind of chip chamber full-shield encapsulating structure based on substrate embedment technical module
TWI586233B (en) Integrated antenna package and manufacturing method thereof
US20080298023A1 (en) Electronic component-containing module and manufacturing method thereof
CN103229293A (en) Semiconductor chip package, semiconductor module, and method for manufacturing same
CN100511614C (en) Package method for multi-chip stack and package structure thereof
CN103474361A (en) Packaging process and packaging structure of embedded substrate with active chip embedment function
CN105789173B (en) Integrate wiring board of intermediary layer and double wire structures and preparation method thereof
CN208722873U (en) The full frame shield structure of chip and full-shield package system
WO2019227956A1 (en) Wireless transmission module and fabrication method therefor
CN110364490A (en) A kind of chip-packaging structure and its packaging method
JP4935320B2 (en) Component built-in multilayer wiring board device and manufacturing method thereof
CN108538803A (en) Assembling fan-out package structure and production method after a kind of chip
CN100472780C (en) Electronic component and method for manufacturing the same
CN112259528A (en) SIP structure with double-sided selective electromagnetic shielding package and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20191022