CN112635436A - Chip packaging structure and preparation method thereof - Google Patents

Chip packaging structure and preparation method thereof Download PDF

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Publication number
CN112635436A
CN112635436A CN202011499407.5A CN202011499407A CN112635436A CN 112635436 A CN112635436 A CN 112635436A CN 202011499407 A CN202011499407 A CN 202011499407A CN 112635436 A CN112635436 A CN 112635436A
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China
Prior art keywords
chip
semiconductor chip
packaging
layer
conductive
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CN202011499407.5A
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CN112635436B (en
Inventor
陈鹏
钱卫松
曾心如
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Abstract

The invention discloses a chip packaging structure and a preparation method thereof, wherein the chip packaging structure comprises: the packaging substrate is provided with a first surface and a second surface which are opposite; the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate; a plurality of ground pads disposed on the first surface of the package substrate and at least partially surrounding the semiconductor chip; the plastic packaging layer covers the first surface of the packaging substrate and covers the semiconductor chip and the plurality of grounding pads; the metal layer covers the top surface and the side surface of the plastic packaging layer; and a plurality of conductive arcs embedded in the plastic package layer and having opposite first and second ends, wherein the first ends of the conductive arcs are respectively connected to one of the grounding pads, and the second ends of the conductive arcs are exposed from the side surface of the plastic package layer and contact the metal layer.

Description

Chip packaging structure and preparation method thereof
Technical Field
The disclosure relates to the field of integrated circuit packaging technologies, and in particular, to a chip package structure and a method for manufacturing the same, which have an anti-electromagnetic interference function.
Background
In the fabrication of integrated circuits, chips are obtained by the steps of wafer fabrication, forming integrated circuits, and dicing wafers. The chips formed by wafer dicing may be electrically connected to a carrier, such as a leadframe or a package substrate, and the chips may be encapsulated by chip packaging techniques to prevent the chips from contacting the outside world and from being damaged by the outside world. With the rapid development of photoelectric and micro-electrical manufacturing technology, electronic products are always developed toward smaller, lighter and cheaper products, and therefore, the packaging form of chip components is continuously improved.
With the increasing demand of people for the functionality of electronic products, various chips are widely used in various electrical appliances. The chips are easily affected by electromagnetic radiation in the operation process, the operation frequency of the chips is disturbed, and the working stability of the chips is reduced.
Disclosure of Invention
In order to solve the above technical problems, the present disclosure provides a novel chip package structure and a method for manufacturing the same, which has an anti-electromagnetic interference function.
According to an aspect of the present disclosure, there is provided a chip packaging structure, including: the packaging substrate is provided with a first surface and a second surface which are opposite; the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate; a plurality of ground pads disposed on the first surface of the package substrate and at least partially surrounding the semiconductor chip; the plastic packaging layer covers the first surface of the packaging substrate and covers the semiconductor chip and the plurality of grounding pads; the metal layer covers the top surface and the side surface of the plastic packaging layer; and a plurality of conductive arcs embedded in the plastic package layer and having opposite first and second ends, wherein the first ends of the conductive arcs are respectively connected to one of the grounding pads, and the second ends of the conductive arcs are exposed from the side surface of the plastic package layer and contact the metal layer.
In some embodiments, the chip package structure further includes a plurality of conductive balls disposed on the second surface of the package substrate and electrically connected to the semiconductor chip.
In some embodiments, the second ends of the plurality of conductive arcs are located at 1/4-3/4 of the height of the side of the molding layer.
In some embodiments, the pitch of the second ends of the plurality of conductive arcs is greater than or equal to 50 μm and less than or equal to 500 μm.
In some embodiments, the wire diameter of the plurality of conductive arcs is greater than or equal to 20 and less than or equal to 30 microns.
In some embodiments, the material of the metal layer is selected from the following materials or any combination thereof: aluminum, copper, iron.
In some embodiments, the conductive arcs are made of gold, silver, aluminum, or copper.
In some embodiments, the plurality of grounding pads entirely surrounds the semiconductor chip, and the metal layer and the plurality of conductive arcs form a bottom-shrinking faraday cage.
In some embodiments, the semiconductor chip is electrically connected to the package substrate through wire bonding or flip chip bonding.
In some embodiments, the operating frequency of the semiconductor chip is between 0.5GHz and 10 GHz.
In some embodiments, the plurality of conductive arcs are arcs resembling an 1/4 circle.
According to another aspect of the present disclosure, there is provided a method for manufacturing a chip package structure, including the steps of:
providing a package substrate having a semiconductor chip, a plurality of ground pads, a plurality of leads, and wires disposed on a first surface, wherein the wires are disposed along a periphery of the package substrate and at least partially surround the semiconductor chip, the plurality of ground pads correspond to the wires and are disposed closer to the semiconductor chip than the wires, and the plurality of ground pads partially surround the semiconductor chip and are connected to the wires through the plurality of leads;
forming a plastic packaging layer on the first surface of the packaging substrate, wherein the plastic packaging layer covers the wires, the leads and the grounding pads of the semiconductor chip;
cutting the plastic package layer and the package substrate along the periphery of the semiconductor chip to cut off the leads between the plurality of ground pads and the leads to form a plurality of conductive arcs embedded in the plastic package layer, wherein the plurality of conductive arcs have first ends respectively connected with one of the plurality of ground pads and second ends exposed from the side surface of the plastic package layer; and
and forming a metal layer on the top surface and the side surface of the plastic packaging layer subjected to the cutting process to contact the second end process of the plurality of conductive arcs exposed from the side surface of the plastic packaging layer.
In some embodiments, the plurality of leads are severed from their highest points in the step of cutting the molding layer and the package substrate along the periphery of the semiconductor chip.
In certain embodiments, the method of making further comprises the steps of: and arranging a plurality of conductive balls on the second surface of the packaging substrate, wherein the conductive balls are electrically connected with the semiconductor chip.
The chip packaging structure has the advantages that the metal layer which covers the top surface and the side surface of the plastic packaging layer is contacted through one ends of the arc-shaped wires which are embedded in the plastic packaging layer and exposed out of the side surface of the plastic packaging layer, so that the metal layer grounding function is realized, the Faraday cage with the anti-electromagnetic interference function is provided to shield electromagnetic interference, and the semiconductor chip in the chip packaging structure can effectively operate at the operating frequency of 0.5GHz-10 GHz. Meanwhile, the metal layer for electromagnetic interference (EMI) shielding does not depend on the fact that grounding must be achieved in a narrow area at the bottom of the packaging substrate, the grounding structure and the grounding cost are simplified, the manufacturing method of the chip packaging structure is simple and convenient to implement, the cost is low, and the chip packaging structure is suitable for batch production.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1-3 are schematic diagrams of a method of fabricating a chip package structure according to an embodiment of the disclosure.
Fig. 4 is a schematic diagram of a chip package structure according to an embodiment of the disclosure.
Fig. 5 is a schematic view of a bottom-collapsed faraday cage comprised of the metal layer 700 and the plurality of conductive arcs 304' of fig. 4.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. Directional phrases used in the present invention, such as [ upper ], [ lower ], [ top ], [ bottom ], [ left ], [ right ], [ inner ], [ outer ], [ side ], refer to the directions of the attached drawings only. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
A method for manufacturing a chip package structure according to an embodiment of the disclosure is illustrated in fig. 1 to 3.
Referring to fig. 1, a package substrate 100 having a first surface a and a second surface B opposite to each other is provided. As shown in fig. 1, two semiconductor chips 200 are separately disposed on the first surface a of the package substrate 100, and the two semiconductor chips 200 are electrically connected to the package substrate 100, respectively. In the present embodiment, the two semiconductor chips 200 are respectively electrically connected to the pads 206 disposed on the semiconductor chips 200 and the pads 202 disposed on the package substrate 100 through a wire bonding (wire bonding) process by a plurality of wires 204, so as to form electrical connections between the semiconductor chips 200 and the package substrate 100. In other embodiments, other processes such as flip-chip bonding (flip-chip bonding) may be used to form the electrical connection between the semiconductor chip 200 and the package substrate 100.
Referring to fig. 1, the first surface a of the package substrate 10 is further provided with a conductive trace 300 and a plurality of ground pads 302. As shown in fig. 1, the conductive lines 300 are disposed along the periphery of the package substrate 10 and at least partially surround the plurality of semiconductor chips 200, and the plurality of ground pads 302 are disposed corresponding to the conductive lines and closer to each semiconductor chip 200 than the conductive lines. The connection between the grounding pads 302 and the conductive wires 300 is formed through the leads 304. The plurality of ground pads 302 are electrically connected to ground lines 120 (shown in fig. 4, but not shown in fig. 1) within the package substrate 10. In the present embodiment, the package substrate 100 is, for example, a printed circuit board such as FR4 copper clad circuit board or BT resin-based circuit board, or other types of package substrates. The semiconductor chip 200 has an operating frequency of 0.5GHz-10GHz, and can be used as an RF chip, a GPS positioning chip, a memory chip such as DRAM and NAND, a Controller chip, or a bluetooth chip. In the present embodiment, the plurality of leads 204 and 304 may be shaped like a semi-circular conductive arc, which may be formed by a wire bonding process.
Referring to fig. 2, a molding layer 400 is formed on the first surface a of the package substrate by a molding process (not shown). The molding compound layer 400 covers the entire first surface a of the package substrate 100 and covers the semiconductor chip 200, the bonding pads 206, the wires 300, the leads 204 and 304, and the grounding pads 302. A plurality of conductive balls 450 (shown in fig. 4, but not shown in fig. 2) are then formed on the surface of the package substrate B corresponding to the positions where the semiconductor chips 200 are disposed by a ball-mounting process (not shown). The conductive balls 450 may be arranged in a ring or rectangle, and are electrically connected to the semiconductor chip 200 through a circuit (not shown) disposed in the package substrate 100.
Referring to fig. 3, the structure shown in fig. 2 is cut along a plurality of directions, such as line a-a, line B-B, line C-C, line D-D, and line E-E in fig. 3, by a cutting process 600, so as to obtain two separated chip package structures. In the dicing process, the wire 304 is cut from the highest point of the wire 304 to form a plurality of conductive arcs 304' (shown in fig. 4-5, but not shown in fig. 3) embedded in the molding layer 400. Here, the conductive arc 304' after cutting is an arc similar to 1/4 circle (approximate circle). It is understood that the conductive arcs 304 ' are embedded in the molding layer 400, but have opposite first and second ends, wherein the first ends of the conductive arcs 304 ' are respectively connected to one of the grounding pads 302, and the second ends of the conductive arcs 304 ' are exposed at the side of the molding layer 400. Next, a metal layer 700 (shown in fig. 4-5, but not shown in fig. 3) is formed on the top and side surfaces of the molding layer 400 and the side surfaces of the package substrate 100 in the two divided chip package structures by a sputtering or spraying process. Thus, one end of the conductive arcs 304' exposed to the side of the molding layer 400 can be used as exposed ground metal terminals to contact the metal layer 700.
Referring to fig. 4, a schematic diagram of a chip package structure after being divided according to an embodiment of the disclosure is shown. Here, for the sake of simplifying the drawing, only the package substrate 100, the semiconductor chip 200, the conductive arcs 304', the molding compound 400, the metal layer 700, and the conductive balls 450 are shown. As shown in fig. 4, the second ends of the plurality of conductive arcs 304 'may be disposed (having a height H) at 1/4-3/4 (e.g., about 1/2) of the height H of the side surface of the molding layer 400, and the pitch P of the second ends of the plurality of conductive arcs 304' is greater than or equal to 50 μm and less than or equal to 500 μm (e.g., 100 μm, 300 μm). The diameter of the conductive arcs 304' may be greater than or equal to 20 and less than or equal to 30 μm (e.g., 25 μm), and the material thereof may be gold, silver, aluminum, or copper, or any combination thereof. The material of the metal layer 700 may be selected from aluminum, copper or iron, and has a thickness ranging from 1 μm to 20 μm (e.g., 10 μm).
Referring to fig. 5, a schematic diagram of a bottom-collapsed faraday cage formed by the metal layer 700 and the plurality of conductive arcs 304' of fig. 4 is shown. The bottom-shrinking faraday cage (also referred to as "faraday-like cage") formed by the metal layer 700 and the plurality of conductive arcs 304' can be used as an electromagnetic wave shield for the semiconductor chip in the molding layer 400, so as to ensure the semiconductor chip in the chip package structure to operate effectively at an operating frequency between 0.5GHz and 10 GHz.
In one embodiment, to form an effective faraday cage, grounding pad 302 may be disposed around semiconductor die 200 in a dense pattern completely surrounding semiconductor die 200, where the density of grounding pad 302 correspondingly reflects the density or adjacent spacing of conductive arcs 304', which may depend on the frequency band of noise (e.g., electromagnetic) to be suppressed.
It will be understood that the method for manufacturing the chip package structure shown in fig. 1-3 only discloses the fabrication of two chip package structures, but the invention is not limited thereto. The method of fabricating the chip package shown in fig. 1-3 is also suitable for processing a chip package including tens of semiconductor chips, and forming tens of chip packages as shown in fig. 4-5 after division. Therefore, the manufacturing method for forming the chip packaging structure shown in fig. 4-5 is simple and convenient to implement, low in cost and suitable for mass production.
It will be understood that the semiconductor chip 200 of the chip package structure in the above embodiment is illustrated as one chip diagram, but it may also represent a plurality of semiconductor chips, for example, the ground pad 302 may surround the semiconductor chip 200 representing a plurality of semiconductor chips.
In summary, the present invention provides a novel chip package structure with anti-electromagnetic interference function, which includes: the packaging substrate is provided with a first surface and a second surface which are opposite; the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate; a plurality of ground pads disposed on the first surface of the package substrate and at least partially surrounding the semiconductor chip; the plastic packaging layer covers the first surface of the packaging substrate and covers the semiconductor chip and the plurality of grounding pads; the metal layer covers the top surface and the side surface of the plastic packaging layer; and a plurality of conductive arcs embedded in the plastic package layer and having opposite first and second ends, wherein the first ends of the conductive arcs are respectively connected to one of the grounding pads, and the second ends of the conductive arcs are exposed from the side surface of the plastic package layer and contact the metal layer.
The beneficial effects of the disclosed embodiment lie in providing a novel chip packaging structure, and one end of a plurality of arc-shaped wires which are buried in the plastic package layer and exposed from the side surface of the plastic package layer is contacted with the metal layer covering the top surface and the side surface of the plastic package layer, so that the faraday cage with the function of resisting electromagnetic interference is provided to shield electromagnetic interference while the grounding function of the metal layer is realized, and further, the effective operation of the semiconductor chip in the chip packaging structure at the operation frequency of 0.5GHz-10GHz is ensured. Meanwhile, the metal layer for electromagnetic interference (EMI) shielding does not depend on the fact that grounding must be achieved in a narrow area at the bottom of the packaging substrate, the grounding structure and the grounding cost are simplified, the manufacturing method of the chip packaging structure is simple and convenient to implement, the cost is low, and the chip packaging structure is suitable for batch production.
Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention.

Claims (15)

1. A chip packaging structure is characterized in that: the chip packaging structure comprises:
the packaging substrate is provided with a first surface and a second surface which are opposite;
the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate;
a plurality of ground pads disposed on the first surface of the package substrate and at least partially surrounding the semiconductor chip;
the plastic packaging layer covers the first surface of the packaging substrate and covers the semiconductor chip and the plurality of grounding pads;
the metal layer covers the top surface and the side surface of the plastic packaging layer; and
a plurality of electrically conductive pitch arcs, bury underground in the plastic envelope layer, have relative first end and second end, wherein the first end of a plurality of electrically conductive pitch arcs is connected respectively one of a plurality of grounding pads, the second end of a plurality of electrically conductive pitch arcs is then followed the side of plastic envelope layer exposes and contact in the metal level.
2. The chip package structure according to claim 1, wherein: the packaging substrate further comprises a plurality of conductive balls which are arranged on the second surface of the packaging substrate and electrically connected with the semiconductor chip.
3. The chip package structure according to claim 1, wherein: the second ends of the plurality of conductive arcs are located at 1/4-3/4 of the height of the side of the molding layer.
4. The chip package structure according to claim 1, wherein: the pitch of the second ends of the plurality of conductive arcs is greater than or equal to 50 μm and less than or equal to 500 μm.
5. The chip package structure according to claim 1, wherein: the wire diameter of the plurality of conductive arcs is greater than or equal to 20 and less than or equal to 30 microns.
6. The chip package structure according to claim 1, wherein: the material of the metal layer is selected from the following materials or any combination thereof: aluminum, copper, iron.
7. The chip package structure according to claim 1, wherein: the plurality of conductive arcs are made of gold, silver, aluminum or copper.
8. The chip package structure according to claim 1, wherein: the semiconductor chip is completely surrounded by the grounding pads, and the metal layer and the conductive arcs form a Faraday cage with a contracted bottom.
9. The chip package structure according to claim 1, wherein: the semiconductor chip is electrically connected to the package substrate through wire bonding or flip chip bonding.
10. The chip package structure according to claim 1, wherein: the operating frequency of the semiconductor chip is between 0.5GHz and 10 GHz.
11. The chip package structure according to claim 1, wherein: the semiconductor chip includes one or more of the following chips: the device comprises an RF (radio frequency) chip, a GPS (global positioning system) positioning chip, a DRAM (dynamic random access memory) chip, a NAND memory chip, a Bluetooth chip and a controller chip.
12. The chip package structure according to claim 1, wherein: the plurality of conductive arcs are arcs like 1/4 circles.
13. A method for preparing a chip packaging structure is characterized by comprising the following steps: the preparation method of the chip packaging structure comprises the following steps:
providing a package substrate having a semiconductor chip, a plurality of ground pads, a plurality of leads, and wires disposed on a first surface, wherein the wires are disposed along a periphery of the package substrate and at least partially surround the semiconductor chip, the plurality of ground pads correspond to the wires and are disposed closer to the semiconductor chip than the wires, and the plurality of ground pads partially surround the semiconductor chip and are connected to the wires through the plurality of leads;
forming a plastic packaging layer on the first surface of the packaging substrate, wherein the plastic packaging layer covers the wires, the leads and the grounding pads of the semiconductor chip;
cutting the plastic package layer and the package substrate along the periphery of the semiconductor chip to cut off the leads between the plurality of ground pads and the leads to form a plurality of conductive arcs embedded in the plastic package layer, wherein the plurality of conductive arcs have first ends respectively connected with one of the plurality of ground pads and second ends exposed from the side surface of the plastic package layer; and
and forming a metal layer on the top surface and the side surface of the plastic packaging layer subjected to the cutting processing so as to contact the second ends of the plurality of conductive arcs exposed from the side surface of the plastic packaging layer.
14. The method for manufacturing a chip package structure according to claim 13, wherein: in the step of cutting the molding layer and the package substrate along the periphery of the semiconductor chip, the plurality of leads are cut from the highest points of the plurality of leads.
15. The method for manufacturing a chip package structure according to claim 13, wherein: further comprising the steps of: and arranging a plurality of conductive balls on the second surface of the packaging substrate, wherein the conductive balls are electrically connected with the semiconductor chip.
CN202011499407.5A 2020-12-17 2020-12-17 Chip packaging structure and preparation method thereof Active CN112635436B (en)

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