KR100319400B1 - Semiconductor Package and Manufacturing Method - Google Patents
Semiconductor Package and Manufacturing Method Download PDFInfo
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- KR100319400B1 KR100319400B1 KR1019980061610A KR19980061610A KR100319400B1 KR 100319400 B1 KR100319400 B1 KR 100319400B1 KR 1019980061610 A KR1019980061610 A KR 1019980061610A KR 19980061610 A KR19980061610 A KR 19980061610A KR 100319400 B1 KR100319400 B1 KR 100319400B1
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- lead frame
- semiconductor chip
- circuit pattern
- manufacturing
- conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체패키지 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same.
종래 칩사이즈 형태의 반도체패키지는 리드프레임(A)을 차별적으로 식각(하프에칭)처리하여 리드(4)보다 두꺼운 볼랜드(3)를 형성하는 제조방법을 채용해 왔기 때문에 그 과정이 복잡하고 고도의 기술 및 고비용이 요구되며, 한편 볼랜드(3)의 크기가 매우 작기 때문에 몰드컴파운드(6)에 의한 성형과정에서 볼랜드(3)가 플러시(금형에서 새어 나온 몰드컴파운드, 도시생략)에 의해서 덮여질 경우 볼랜드(3)에 도전성볼(5)을 붙이기 위해서 볼랜드(3)에 덮여진 플러시를 제거하는 별도의 과정을 거쳐야 하는 제조공정상의 문제점이 야기되어 왔었다.In the conventional chip size semiconductor package, since the lead frame A is differentially etched (half-etched), a manufacturing method of forming the borland 3 thicker than the lead 4 has been adopted. Technology and high cost are required, while on the other hand, when the borland 3 is covered by a flush (mold compound leaking out of the mold, not shown) during the molding process by the mold compound 6 because the size of the borland 3 is very small. In order to attach the conductive balls 5 to the ball lands 3, problems have been caused in the manufacturing process that require a separate process of removing the flush covered by the ball lands 3.
이에, 본 발명에서는 리드프레임(A)에 저가의 비전도성 커버코트(Cover Coat; PI계 감광필림 등)를 부착하는 방법을 통해 솔더볼을 손쉽게 붙일 수 있는 방법을 제안하게 된 것으로, 칩싸이즈형 반도체패키지를 형성함에 있어서, 식각(하프에칭)처리에 의한 볼랜드의 형성방법이 아닌 패턴이 형성된 동일 두께의 리드프레임에 비전도성 커버코트를 부착하여 솔더볼을 부착할 수 있도록 함으로써 제조공정의 단순화를 통하여 양산 가능하고 제조단가를 절감할 수 있는 반도체패키지 및 그 제조방법을 제공하게 되는 것이다.Accordingly, the present invention proposes a method for easily attaching solder balls through a method of attaching a low-cost non-conductive cover coat (PI-based photosensitive film, etc.) to the lead frame A, and the chip size semiconductor. In forming the package, it is not mass production method of the ball land by etching (half etching), but mass production through simplification of the manufacturing process by attaching the non-conductive cover coat to the lead frame of the same thickness where the pattern is formed to attach the solder balls. It is possible to provide a semiconductor package and a method of manufacturing the same, which can reduce manufacturing costs.
Description
본 발명은 반도체패키지 및 그 제조방법에 대한 것으로, 더욱 상세하게는 리드프레임을 이용한 칩싸이즈형 반도체패키지 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a chip sized semiconductor package using a lead frame and a method of manufacturing the same.
일반적으로, 반도체패키지는 그 내부에 반도체칩을 비롯한 고밀도의 회로를 내장함으로써 외부환경(외력, 먼지, 습기, 전기적, 열적 부하 등)으로부터 회로를 보호하고 반도체칩의 성능을 극대화하기 위하여 금속재질의 리드프레임이나 회로패턴이 실장된 플라스틱 스트립자재를 이용해 입출력단자를 형성하고 봉지수단(몰드컴파운드에 의한 성형화 또는 코팅화)으로 성형한 얇은 형태의 구조(표면실장형)를 하게 된다.In general, semiconductor packages contain high-density circuits, including semiconductor chips, to protect circuits from external environments (external forces, dust, moisture, electrical, thermal loads, etc.) and to maximize the performance of semiconductor chips. Input and output terminals are formed using a plastic strip material mounted with a lead frame or a circuit pattern, and a thin structure (surface mounted type) formed by sealing means (molding or coating by molding compound) is formed.
한편, 최근 전자기기의 고성능화와 더불어 휴대용화가 진행됨에 따라 이러한 전자기기에 사용되는 반도체패키지 또한 고집적화, 초경량화, 소형화, 박형화되는 경향으로 이미 패키지의 양측(또는 사방)으로 리드를 형성한 반도체패키지 구조에서 패키지의 하면에 도전성볼을 형성한 BGA(Ball Grid Array) 반도체패키지의 출현을 보게 되었다.On the other hand, as the high performance of electronic devices and portableization has progressed recently, semiconductor packages used in such electronic devices have also tended to be highly integrated, ultra lightweight, miniaturized, and thin, and have a semiconductor package structure in which leads are formed on both sides (or four sides) of the package. We have seen the emergence of BGA (Ball Grid Array) semiconductor packages in which conductive balls are formed on the lower surface of the package.
그러나, 이러한 BGA반도체패키지는 회로기판이 고가이고 반도체칩의 크기에 비해 기판의 크기가 훨씬 큰 구조로 이루어지기 때문에 반도체패키지를 칩싸이즈로 초소형화하는데에는 여전히 한계가 있다.However, since the BGA semiconductor package is expensive and the structure of the substrate is much larger than the size of the semiconductor chip, there is still a limitation in miniaturizing the semiconductor package to chip size.
한편, 이러한 칩사이즈 형태의 초소형 반도체패키지의 출현을 가능케 해 준 것이 본 출원인이 개발한 리드 엔드 그리드 어레이형(Lead End Grid Array Type) 리드프레임을 이용한 반도체패키지이다.On the other hand, the semiconductor package using the lead end grid array type lead frame developed by the present applicant has enabled the emergence of such a chip-type micro-miniature semiconductor package.
즉, 도1의 예시와 같이 길이가 길고 짧게 교호적으로 정열(어레이)되고 끝단부에는 볼랜드(3)를 형성한 다수개의 리드(4)를 사각형태로 정열(어레이)시킴과 동시에 그 중앙부에 반도체칩탑재판(2)을 구비한 리드프레임(A)에 반도체칩(1)을 부착함으로써 반도체칩탑재판(2)의 외주연에 리드(4) 및 볼랜드(3)가 위치하도록 하여 반도체패키지를 거이 칩싸이즈 형태로 제조할 수 있게 되어 있다.That is, as shown in FIG. 1, a plurality of leads 4 having a long and short alternating arrangement (array) and a borland (3) formed at the ends thereof are arranged in a square shape and at the center thereof. By attaching the semiconductor chip 1 to the lead frame A having the semiconductor chip mounting plate 2, the lead 4 and the borland 3 are positioned on the outer periphery of the semiconductor chip mounting plate 2 so that the semiconductor package is provided. It can be manufactured in the form of chip size.
한편, 도1과 같이 리드(4)의 끝단부 두께를 일부 두껍게 하여 도전성볼(5)을 붙일 수 있는 볼랜드(3)를 형성함에 있어서는 상기 리드(4)의 두께보다 볼랜드(3)의 두께가 두껍도록 리드프레임(A)의 하면을 식각(감광필림을 붙이고 빛을 조사함)처리하되 조사량과 시간을 정밀 조절하는 일련의 과정을 거쳐 리드(4)와 두께차가 나는 볼랜드(3)를 형성하게 된다. 도1에 있어서 부호 1은 반도체칩, 6은 몰드컴파운드(봉지재), 7은 와이어, 8은 접착제를 나타낸다.On the other hand, as shown in FIG. 1, when the thickness of the end portion of the lead 4 is partially thickened to form the ball land 3 to which the conductive balls 5 can be attached, the thickness of the ball land 3 is greater than the thickness of the lead 4. The lower surface of the lead frame (A) is etched thickly (with a photosensitive film and irradiated with light), but a series of processes of precisely adjusting the dose and time are used to form a ball land (3) having a thickness difference from the lead (4). do. In Fig. 1, reference numeral 1 denotes a semiconductor chip, 6 denotes a mold compound (an encapsulant), 7 denotes a wire, and 8 denotes an adhesive.
그러나, 종래와 같이 리드프레임을 차별적으로 식각(하프에칭)처리하여 리드 보다 두꺼운 볼랜드를 형성하는 경우는 그 과정이 복잡하고 고도의 기술 및 고비용이 요구되는 단점이 있다.However, when the lead frame is differentially etched (half etched) to form a ball land thicker than the lead as in the related art, the process is complicated and requires high technology and high cost.
또한, 최근에는 반도체집의 집적도가 증가함에 따라 동일한 면적에서 보다 많은 리드 및 도전성볼의 개수가 필요한 추세인데, 종래에는 상기 리드 및 도전성 볼이 칩탑재판의 외주연에만 형성될 수 있음으로써 도전성볼 개수의 증가에 한계가 있다.In addition, in recent years, as the degree of integration of semiconductor collections increases, more leads and conductive balls are required in the same area. In the related art, the leads and conductive balls may be formed only on the outer periphery of the chip mounting plate, thereby causing the conductive balls. There is a limit to the increase.
더불어, 종래 리드프레임의 하면에 형성되는 볼랜드는 그 크기가 매우 작기 때문에 몰드컴파운드에 의한 성형 공정에서 볼랜드가 플래시(금형에서 새어 나온 몰드컴파운드, 도시생략)에 의해서 덮여질 경우 그것을 제거하기 위한 공정이 별도로 추가되는 문제가 있다.In addition, since the size of the ball land formed on the lower surface of the conventional lead frame is very small, a process for removing it when the ball land is covered by a flash (mold compound leaking out of the mold, not shown) is formed in the molding process by the mold compound. There is an additional problem.
이에, 본. 발명의 첫번째 목적은 칩싸이즈형 반도체패키지를 형성함에 있어서, 식각(하프에칭)처리에 의한 볼랜드의 형성방법이 아닌 패턴이 형성된 동일 두께의 리드프레임에 비도전성 커버코트를 부착하여 도전성볼을 직접 부착할 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.Hence, seen. The first object of the present invention is to form a chip sized semiconductor package, in which a conductive ball is directly attached to a non-conductive cover coat on a lead frame of the same thickness in which a pattern is formed, not a method of forming a ball land by etching (half etching). The present invention provides a semiconductor package and a method of manufacturing the same.
본 발명의 두번째 목적을 반도체칩의 하면 및 그 하면 외주연 전체에 풀어레이형(Full Array Type)으로 도전성볼을 형성할 수 있도록 함으로써, 외부 도전성볼의 개수를 극대화할 수 있는 반도체패키지 및 그 제조 방법을 제공하는데 있다.The second object of the present invention is to enable the formation of conductive balls in a full array type on the lower surface of the semiconductor chip and the outer periphery of the lower surface thereof, thereby manufacturing a semiconductor package capable of maximizing the number of external conductive balls and its manufacture. To provide a method.
본 발명의 세 번째 목적은 리드프레임 하면 전체에 커버커트를 부착한 후 봉지 공정을 수행함으로써, 볼랜드 영역에 플래시가 발생하지 않도록 함으로써, 추가 적인 플래시 제거 공정이 필요없는 반도체패키지의 제조 방법을 제공하는데 있다.A third object of the present invention is to provide a method of manufacturing a semiconductor package by attaching a cover cut to the entire lower surface of the lead frame and then encapsulating the product so that no flash occurs in the borland region, thereby eliminating an additional flash removal process. have.
도 1은 종래 칩사이즈형 반도체패키지의 구성도1 is a configuration diagram of a conventional chip size semiconductor package
도 2a 및 도 2b는 본 발명의 실시예를 보여 주는 칩사이즈형 반도체패키지의 구성도2A and 2B are diagrams illustrating a chip size semiconductor package showing an embodiment of the present invention.
도 3은 본 발명의 리드프레임 구성도3 is a lead frame configuration of the present invention
도 4는 본 발명의 제조과정을 나타낸 블록도Figure 4 is a block diagram showing the manufacturing process of the present invention
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 : 리드프레임 12 : 본딩부10: lead frame 12: bonding portion
14 : 볼랜드부 16 : 회로패턴부14: Borland portion 16: Circuit pattern portion
18 : 사이드레일18: side rail
20 : 접착수단 30 : 반도체칩20: bonding means 30: semiconductor chip
40 : 와이어 50 : 봉지재40: wire 50: encapsulant
60 : 커버코트 62 : 관통부60: cover coat 62: through part
70 : 도전성볼70: conductive ball
상기와 같은 목적을 달성하기 위한 본 발명의 칩싸이즈형 반도체패키지 및 그 제조방법은 다음과 같은 특징을 제공한다.The chip sized semiconductor package of the present invention and its manufacturing method for achieving the above object provides the following features.
첫째, 반도체칩과; 상기 반도체칩의 하면에 접착수단으로 다수의 회로패턴부가 접착되어 있고, 상기 회로패턴부는 상기 반도체칩 하면의 내주연 및 외주연으로 연장되어 있으며, 상기 반도체칩의 외주연으로 연장된 회로패턴부 상면에는 다수의 본딩부가 형성되고 있으며, 상기 회로패턴부 하면 전체에는 풀어레이형(Full Array Type)으로 볼랜드부가 형성된 대략 판상의 리드프레임과; 상기 반도체칩과 상기 리드프레임의 본딩부를 상호 전기적으로 접속하는 도전성와이어와; 상기 반도체칩 및 도전성와이어와, 상기 반도체칩 외주연의 리드프레임 상면을 봉지하는 봉지재와; 상기 리드프레임의 하면 전체에 부착되어 있되, 상기 리드프레임의 각 볼랜드부와 대응되는 위치에는 관통부가 형성된 절연성의 커버코트와; 상기 커버코트의 관통부를 통해 노출된 볼랜드부에 형성된 도전성볼을 포함하여 이루어진 반도체패키지를 제공한다.First, with a semiconductor chip; A plurality of circuit pattern portions are bonded to the lower surface of the semiconductor chip by means of bonding, and the circuit pattern portion extends to the inner and outer circumferences of the lower surface of the semiconductor chip, and the upper surface of the circuit pattern portions extending to the outer circumference of the semiconductor chip. A plurality of bonding parts formed therein, and a substantially flat plate-shaped lead frame having a full land type formed in a full array type on a lower surface of the circuit pattern part; Conductive wires electrically connecting the semiconductor chip and the bonding portion of the lead frame to each other; An encapsulant for encapsulating the semiconductor chip and the conductive wire and an upper surface of the lead frame of the outer circumference of the semiconductor chip; An insulating cover coat attached to an entire lower surface of the lead frame, the penetration cover having a through portion formed at a position corresponding to each of the borland portions of the lead frame; It provides a semiconductor package comprising a conductive ball formed in the ball land portion exposed through the through portion of the cover coat.
둘째, 다수의 회로패턴부가 형성되고, 상기 회로패턴부의 상면에는 다수의 본딩부가 형성되고, 상기 회로패턴부 하면 전체에는 풀어레이형(Full Array Type)으로 볼랜드부가 형성된 대략 판상의 리드프레임을 제공하는 단계와; 상기 리드프레임의 하면에 절연성 커버코트를 부착하는 단계와; 상기 리드프레임의 상면에 접착수단을 개재한 후 반도체칩을 부착하는 단계와; 상기 반도체칩과 리드프레임의 본딩부를 도전성와이어로 접속하는 단계와; 상기 반도체칩과 도전성와이어 및 리드 프레임의 상면을 봉지재로 봉지하는 단계와; 상기 리드프레임의 하면에 부착되어 있는 커버코트 중 리드프레임의 볼랜드부 하면과 대응되는 부분에 관통부를 형성하는 단계와; 상기 관통부를 통해 노출된 리드프레임의 볼랜드부에 도전성볼이 부착되는 단계를 포함하여 이루어진 반도체패키지 제조방법을 제공한다.Second, a plurality of circuit pattern portions are formed, and a plurality of bonding portions are formed on an upper surface of the circuit pattern portion, and a plate-shaped lead frame having a borland portion formed in a full array type on the lower surface of the circuit pattern portion is provided. Steps; Attaching an insulating cover coat to a bottom surface of the lead frame; Attaching a semiconductor chip after the adhesive means is interposed on an upper surface of the lead frame; Connecting the bonding portion of the semiconductor chip and the lead frame with conductive wires; Encapsulating the upper surface of the semiconductor chip, the conductive wire and the lead frame with an encapsulant; Forming a through portion in a portion of the cover coat attached to the lower surface of the lead frame corresponding to the lower surface of the ball land portion of the lead frame; It provides a semiconductor package manufacturing method comprising the step of attaching a conductive ball to the ball land portion of the lead frame exposed through the through portion.
여기서, 상기 관통부 형성 단계는 레이저빔, 화학적 에칭 또는 빛의 조사중 어느 하나에 의해 이루어질 수 있다.Here, the step of forming the through part may be performed by any one of laser beam, chemical etching or light irradiation.
따라서, 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 식각(하프 에칭)처리에 의한 볼랜드의 형성방법이 아닌 패턴이 형성된 동일 두께의 리드프레임에 비도전성 커버코트를 부착하여 도전성볼을 직접 부착할 수 있도록 함으로써, 제조 공정이 단순화되고 또한 비용도 절감된다.Therefore, according to the semiconductor package and the manufacturing method thereof according to the present invention, the conductive ball is directly attached by attaching a non-conductive cover coat to the lead frame having the same thickness as the pattern formed, not the method of forming the ball land by etching (half etching). By doing so, the manufacturing process is simplified and the cost is reduced.
또한, 반도체칩의 하면 및 그 하면 외주연 전체에 풀어레이형(Full Array Type)으로 도전성볼을 형성할 수 있도록 함으로써, 외부 도전성볼의 개수를 극대화 할 수 있게 되어 최근의 고집적화된 반도체집을 용이하게 수용할 수 있다.In addition, it is possible to form conductive balls in a full array type on the lower surface of the semiconductor chip and the entire outer periphery of the lower surface thereof, thereby maximizing the number of external conductive balls, thereby facilitating recent highly integrated semiconductor collections. I can accept it.
더불어, 리드프레임 하면 전체에 커버커트를 부착한 후 봉지 공정을 수행함으로써, 볼랜드 영역에 플래시가 발생하지 않도록 함으로써, 추가적인 플래시 제거 공정이 필요없게 된다.In addition, by attaching a cover cut to the entire lower surface of the lead frame and then performing an encapsulation process, a flash does not occur in the borland region, thereby eliminating an additional flash removal process.
(실시예)(Example)
이하, 본 발명을 첨부된 예시도면을 통해 보다 구체적으로 설명하면 다음과 같다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도2a 및 도2b는 본 발명의 실시예를 보여 주는 칩싸이즈형 반도체패키지의 구성도를 나타낸 것이고, 도3은 본 발명에 적용되는 리드프레임(10)의 평면 구성도이다.2A and 2B show a configuration diagram of a chip sized semiconductor package showing an embodiment of the present invention, and FIG. 3 is a plan configuration diagram of a lead frame 10 applied to the present invention.
도시된 바와 같이 반도체칩(30)이 구비되어 있고, 상기 반도체칩(30)의 하면에는 리드프레임(10)이 접착수단(20)으로 접착되어 있다. 상기 리드프레임(10)은 다수의 회로패턴부(16)가 형성되어 있고, 상기 회로패턴부(16)는 상기 반도체칩(30) 하면의 내주연 및 외주연으로 연장되어 있다.As shown in the drawing, the semiconductor chip 30 is provided, and the lead frame 10 is bonded to the lower surface of the semiconductor chip 30 by the bonding means 20. The lead frame 10 includes a plurality of circuit pattern portions 16, and the circuit pattern portions 16 extend in the inner and outer circumferences of the lower surface of the semiconductor chip 30.
또한, 상기 반도체칩(30)의 외주연으로 연장된 회로패턴부(16) 상면에는 다수의 본딩부(12)가 형성되고 있고, 상기 회로패턴부(16) 하면 전체에는풀어레이형(Full Array Type)으로 볼랜드부(14)가 형성되어 있다.In addition, a plurality of bonding portions 12 are formed on an upper surface of the circuit pattern portion 16 extending along the outer circumference of the semiconductor chip 30, and a full array is formed on the entire lower surface of the circuit pattern portion 16. Borland portion 14 is formed as a type.
여기서, 상기 리드프레임(10)은 전체적으로 얇은 판 모양으로 형성되어 있다.Here, the lead frame 10 is formed in a thin plate shape as a whole.
계속해서, 상기 반도체칩(30)과 상기 리드프레임(10)의 본딩부(12)는 도전성 와이어에 의해 상호 연결되어 있음으로써, 두소자간에 전기적 도통이 가능하게 되어 있다.Subsequently, the semiconductor chip 30 and the bonding portion 12 of the lead frame 10 are connected to each other by conductive wires, thereby enabling electrical conduction between the two devices.
상기 반도체칩(30) 및 도전성와이어(40)와, 상기 반도체칩(30) 외주연의 리드프레임(10) 상면은 봉지재(40)로 봉지되어 외부 환경으로부터 보호가능하게 되어 있다.The semiconductor chip 30, the conductive wire 40, and the upper surface of the lead frame 10 on the outer circumference of the semiconductor chip 30 are encapsulated with an encapsulant 40 to be protected from the external environment.
더불어, 상기 리드프레임(10)의 하면 전체에는 절연성 커버코트(60)가 부착되어 있되, 상기 리드프레임(10)의 각 볼랜드부(14)와 대응되는 위치에는 관통부(62)가 형성되어 있다. 여기서, 상기 볼랜드부(14)는 종래와 다르게 하프에칭되어 있지 않으며, 나머지 리드프레임 구성 요소와 동일한 평면을 갖는다.In addition, an insulating cover coat 60 is attached to the entire lower surface of the lead frame 10, but a through portion 62 is formed at a position corresponding to each borland portion 14 of the lead frame 10. . Here, the borland portion 14 is not half-etched unlike the prior art, and has the same plane as the remaining leadframe components.
마지막으로, 상기 커버코트(60)의 관통부(62)를 통해 노출된 볼랜드부(14)에는 도전성볼(70)이 융착되어 차후 마더보드에 실장 가능한 형태로 되어 있다.Finally, the conductive ball 70 is fused to the ball land portion 14 exposed through the penetrating portion 62 of the cover coat 60 to be mounted on the motherboard later.
더불어, 상기 볼랜드부(14) 또는 도전성볼(70)은 반도체칩(30)의 하면중 그 내주연 및 외주연에 형성되거나(도2a 참조) 또는 반도체칩(30)의 하면 전체와 그 외주연 전체에 풀어레이형으로 형성될 수 있다(도2b 참조). 바람직하기로는 도2b 및 도 3에 도시된 바와 같이 반도체칩(30)의 하면 전체와 그 외주연 전체에 풀어레이형으로 형성됨이 효과적이다.In addition, the ball land portion 14 or the conductive ball 70 is formed on the inner and outer periphery of the lower surface of the semiconductor chip 30 (see Fig. 2a) or the entire lower surface and the outer peripheral edge of the semiconductor chip 30 It can be formed in the form of a pulley in its entirety (see Fig. 2b). Preferably, as shown in FIGS. 2B and 3, the semiconductor chip 30 is effectively formed in the form of a pulley on the entire lower surface and the entire outer circumference thereof.
여기서 본 발명의 제조과정을 보다 상세히 설명한다.Here, the manufacturing process of the present invention will be described in more detail.
<리드프레임형성단계><Lead frame formation stage>
먼저 동(Cu)재질의 금속판을 스템핑, 에칭 등의 방법에 의해 가공하여 본딩부(12)와 볼랜드부(14)와 회로패턴부(16)및 사이드레일(18)이 구비된 리드프레임(10)을 형성한다. 여기서 상기 볼랜드부(14)는 풀어레이형으로 형성한다.First, a copper (Cu) metal plate is processed by a method such as stamping or etching to form a lead frame having a bonding part 12, a borland part 14, a circuit pattern part 16, and a side rail 18. 10) form. Here, the ball land portion 14 is formed in a loose lay shape.
<커버코트부착단계><Cover Coat Attachment Step>
상기 리드프레임(10)의 저면에 비전도성의 커버코트(60; PI계 수지)를 부착한다.The non-conductive cover coat 60 (PI-based resin) is attached to the bottom of the lead frame 10.
<반도체칩부착단계><Semiconductor chip attaching step>
상기 리드프레임(10)의 상면에 접착수단(20)을 개재하여 통상의 방법으로 반도체칩(1)을 부착한다. 상기 접착수단(20)에는 반도체칩(30)과의 열팽창계수가 유사한 에폭시접착제 등을 사용한다.The semiconductor chip 1 is attached to the upper surface of the lead frame 10 through a bonding means 20 in a conventional manner. The adhesive means 20 uses an epoxy adhesive similar to the thermal expansion coefficient of the semiconductor chip 30.
<와이어본딩단계><Wire Bonding Step>
리드프레임(10)에 부착된 반도체칩(30)과 리드프레임(10)의 본딩부(12)를 도전성와이어(40)로 본딩 연결한다.The semiconductor chip 30 attached to the lead frame 10 and the bonding portion 12 of the lead frame 10 are bonded to each other by conductive wires 40.
<봉지단계><Envelope stage>
외부환경으로부터 회로를 보호하기 위해 리드프레임(10)에 부착된 반도체칩(30)과 와이어(40) 및 리드프레임(10)의 상면을 봉지재(50)로 봉지한다.In order to protect the circuit from the external environment, the semiconductor chip 30 and the wire 40 attached to the lead frame 10 and the upper surface of the lead frame 10 are encapsulated with an encapsulant 50.
<관통부형성단계><Through penetrating stage>
리드프레임(10)의 저면에 부착되어 있는 커버코트(60) 중 리드프레임(10)의 볼랜드부(14) 저면에 대응 위치되는 부분에 관통부(62)를 형성한다.A penetrating portion 62 is formed in a portion of the cover coat 60 attached to the bottom surface of the lead frame 10 corresponding to the bottom surface of the ball land portion 14 of the lead frame 10.
한편, 동 관통부형성단계는 리드프레임(10)과 커버코트(60)를 부착시키는 단계 다음에 수행할 수도 있고, 리드프레임(10)에 반도체칩(30)을 부착하기 전에 실시할 수도 있는 바, 이는 설계상의 문제라 할 것이다.Meanwhile, the forming of the through part may be performed after attaching the lead frame 10 and the cover coat 60, or may be performed before attaching the semiconductor chip 30 to the lead frame 10. This is a design problem.
상기 관통부(62)를 형성하는 방법으로는 레이저빔을 이용하거나 화학적 에칭을 이용하거나 또는 감광필림을 사용한 빛의 조사방법을 이용할 수가 있다.As the method of forming the penetrating portion 62, a laser beam, a chemical etching method, or a light irradiation method using a photosensitive film may be used.
<도전성볼부착단계><Conductive Ball Attachment Step>
커버코트(60)에 형성된 관통부(62)를 통해 노출되는 리드프레임(10)의 볼랜드부(14)에 도전성볼(70)을 부착한다.The conductive ball 70 is attached to the ball land portion 14 of the lead frame 10 exposed through the through portion 62 formed in the cover coat 60.
<사이드레일절단단계><Side rail cutting stage>
봉지재(50) 외관에 위치해 있는 리드프레임(10)의 사이드레일(18)을 절단한다.The side rails 18 of the lead frame 10 positioned on the exterior of the encapsulant 50 are cut.
상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면, 식각(하프에칭)처리에 의한 볼랜드의 형성방법이 아닌 패턴이 형성된 동일 두께의 리드프레임에 비도전성 커버코트를 부착하여 도전성볼을 직접 부착할 수 있도록 함으로써, 제조 공정이 단순화되고 또한 비용도 절감되는 효과가 있다.According to the semiconductor package and the manufacturing method according to the present invention as described above, the conductive ball is attached by attaching a non-conductive cover coat to the lead frame of the same thickness pattern is formed, not the method of forming the ball land by the etching (half etching) process By directly attaching, the manufacturing process is simplified and the cost is reduced.
또한, 반도체칩의 하면 및 그 하면 외주연 전체에 풀어레이형(Full Array Type)으로 도전성볼을 형성할 수 있도록 함으로써, 외부 도전성볼의 개수를 극대화할 수 있게 되어 최근의 고집적화된 반도체칩을 용이하게 수용할 수 있는 효과가 있다.In addition, it is possible to form conductive balls in a full array type on the lower surface of the semiconductor chip and the entire outer circumference of the lower surface thereof, thereby maximizing the number of external conductive balls, thereby facilitating recent highly integrated semiconductor chips. It has an acceptable effect.
더불어, 리드프레임 하면 전체에 커버커트를 부착한 후 봉지 공정을 수행함으로써, 볼랜드 영역에 플래시가 발생하지 않도록 함으로써, 추가적인 플래시 제거공정이 필요없는 효과가 있다.In addition, by attaching the cover cut to the entire lower surface of the lead frame and performing the encapsulation process, the flash does not occur in the borland region, thereby eliminating the need for an additional flash removal process.
이상에서 설명한 것을 본 발명에 의한 반도체패키지의 구조 및 그 제조방법을 설명하기 위한 하나의 실시예에 불과한 것이며, 본 발명은 상기한 실시예에 한정하지 않고 이하의 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양하 변경 실시가 가능할 것이다.What has been described above is only one embodiment for explaining the structure and manufacturing method of the semiconductor package according to the present invention, and the present invention is not limited to the above-described embodiment but the gist of the present invention claimed in the following claims Without departing from the present invention to those skilled in the art to which those skilled in the art will be able to vary and practice various changes.
Claims (3)
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| KR1019980061610A KR100319400B1 (en) | 1998-12-30 | 1998-12-30 | Semiconductor Package and Manufacturing Method |
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| KR1019980061610A KR100319400B1 (en) | 1998-12-30 | 1998-12-30 | Semiconductor Package and Manufacturing Method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101006907B1 (en) | 2008-02-20 | 2011-01-13 | 앰코 테크놀로지 코리아 주식회사 | Method for manufacturing semiconductor package |
| KR20170017319A (en) | 2015-08-06 | 2017-02-15 | 주식회사 레오퍼니쳐 | Furniture door panel assembly |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100583496B1 (en) * | 2000-08-14 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | Circuit board for semiconductor package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0936275A (en) * | 1995-07-21 | 1997-02-07 | Toshiba Corp | Manufacture of surface mount semiconductor device |
| JPH0997868A (en) * | 1995-09-28 | 1997-04-08 | Dainippon Printing Co Ltd | Lead frame member and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0936275A (en) * | 1995-07-21 | 1997-02-07 | Toshiba Corp | Manufacture of surface mount semiconductor device |
| JPH0997868A (en) * | 1995-09-28 | 1997-04-08 | Dainippon Printing Co Ltd | Lead frame member and its manufacturing method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101006907B1 (en) | 2008-02-20 | 2011-01-13 | 앰코 테크놀로지 코리아 주식회사 | Method for manufacturing semiconductor package |
| KR20170017319A (en) | 2015-08-06 | 2017-02-15 | 주식회사 레오퍼니쳐 | Furniture door panel assembly |
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