KR100251860B1 - Structure of csp and its making method - Google Patents
Structure of csp and its making method Download PDFInfo
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- KR100251860B1 KR100251860B1 KR1019960062304A KR19960062304A KR100251860B1 KR 100251860 B1 KR100251860 B1 KR 100251860B1 KR 1019960062304 A KR1019960062304 A KR 1019960062304A KR 19960062304 A KR19960062304 A KR 19960062304A KR 100251860 B1 KR100251860 B1 KR 100251860B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
본 발명은 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조 및 제조방법에 관한 것으로, 더욱 상세하게는 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있도록 된 CSP구조 및 제조방법에 관한 것이다.The present invention relates to a structure and a manufacturing method of a chip scale package (CSP), and more particularly, by forming the size of the semiconductor package to the size of the semiconductor chip, reducing the size of the semiconductor package to reduce the light and short Of course, the present invention relates to a CSP structure and a method for manufacturing that are capable of high integration and high performance.
일반적으로 반도체패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스밀봉 패키지, 금속 밀봉 패키지 등이 있다. 이와같은 반도체패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology, SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로서 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array)등이 있다.In general, semiconductor packages may include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into an insert type and a surface mount technology (SMT) type according to the mounting method. Representative examples of the insert type include a dual in-line package (DIP) and a pin grid array (PGA). Typical examples of the mounting type include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array).
최근에는 전자제푸므이 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해서 삽입형 반도체패키지 보다는 표면실장형 반도체패키지가 널리 사용되고 있는데, 이러한 종래의 패키지에 대한 구조를 제1도와 제2도를 참조하여 QFP와, BGA패키지에 대하여 설명하면 다음과 같다.Recently, surface mount type semiconductor packages are used rather than insert type semiconductor packages in order to increase the degree of mounting of printed circuit boards due to the miniaturization of electronic products. The structure of such a conventional package is described with reference to FIGS. 1 and 2. The following describes the BGA package.
제1도는 종래의 일반적인 반도체 패키지의 QFP로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(11)과, 상기 반도체칩(11)이 에폭시(16)에 의해 부착되는 탑재판(15)과, 상기 반도체칩(11)의 신호를 외부로 전달할 수 있는 다수의 리드(12)와, 상기 반도체칩(11)과 리드(12)를 연결시켜 주는 와이어(13)와, 상기 반도체칩(11)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 수지봉지재(14)로 이루어지는 것이다.1 is a QFP of a conventional general semiconductor package, the structure of which is a semiconductor chip 11 in which an electronic circuit is integrated, a mounting plate 15 to which the semiconductor chip 11 is attached by an epoxy 16, A plurality of leads 12 capable of transmitting signals of the semiconductor chip 11 to the outside, wires 13 connecting the semiconductor chips 11 and the leads 12, the semiconductor chips 11, In order to protect other peripheral components from external oxidation and corrosion, it is made of a resin encapsulant 14 wrapped on the outside thereof.
이러한 구성에 의한 종래의 QFP는 반도체칩(11)으로 부터 출력된 신호가 와이어(13)를 통해 리드(12)로 전달되며, 상기 리드(12)는 마더보드에 연결되어 있어 리드(12)로 전달된 신호가 마더보드를 주변소자로 전달된다. 주변소자에 발생된 신호가 반도체칩(11)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.In the conventional QFP having such a configuration, a signal output from the semiconductor chip 11 is transmitted to the lead 12 through the wire 13, and the lead 12 is connected to the motherboard to the lead 12. The transmitted signal is transmitted to the motherboard. When the signal generated in the peripheral device is transmitted to the semiconductor chip 11, the signal is transmitted in the reverse order of the path described above.
그러나, 상기의 QFP는 반도체칩이 점차적으로 고성능화되어 가면서 핀의 수가 더욱 더 많아지게 되는데 비하여, 핀과 핀 사이의 거리를 일정치 이하로 좁히는 것은 기술적으로 어려움이 있기 때문에 많은 핀을 모두 수용하기 위해서는 패키지가 커지게 되는 단점이 있다. 이것은 반도체패키지의 소형화 추세에 역행하는 결과를 낳는 문제점이 있는 것이다.However, the above QFP has a higher number of pins as the semiconductor chip is gradually improved in performance. However, it is technically difficult to narrow the distance between the pins to a certain value or less. The disadvantage is that the package becomes large. This is a problem that results in the contrary to the trend of miniaturization of semiconductor packages.
이와같이 다핀화에 따른 기술적 요구를 해결하기 위해서 등장한 것이 BGA패키지로서, 이는 입출력 수단으로서 반도체패키지의 일면전체에 융착된 솔더볼을 이용함으로써 QFP 보다 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 QFP보다 작게 형성된 것이다.The BGA package, which emerged to solve the technical demands of the multi-pinning method, can accept a larger number of input / output signals than the QFP by using solder balls fused to the entire surface of the semiconductor package as an input / output means. Is smaller than QFP.
이러한 BGA패키지의 구성은 제2도에 도시된 바와같이 표면에 회로패턴(25a)이 형성되고, 이 회로패턴(25a)을 보호하기 위해 솔더마스크(25b)가 코팅된 회로기판(25)과, 상기 회로기판(25)의 상면 중앙에 부착된 반도체칩(21)과, 상기 반도체칩(21)과 상기 회로기판(25)의 회로패턴(25a)을 전기적으로 연결하여 신호를 전달하는 와이어(23)와, 상기 회로기판(25)의 회로패턴(25a)에 융착되어 외부로 신호를 전달하는 솔더볼(22)과, 상기 반도체칩(21)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 수지봉지재(24)로 구성되는 것이다.The BGA package includes a circuit board 25 having a circuit pattern 25a formed on a surface thereof and a solder mask 25b coated thereon to protect the circuit pattern 25a, as shown in FIG. The semiconductor chip 21 attached to the center of the upper surface of the circuit board 25 and the wire 23 for electrically connecting the semiconductor chip 21 and the circuit pattern 25a of the circuit board 25 to transmit a signal. ), A solder ball 22 fused to the circuit pattern 25a of the circuit board 25 to transmit a signal to the outside, and protecting the semiconductor chip 21 and other peripheral components from external oxidation and corrosion. It is composed of a resin encapsulation material 24 wrapped to the outside.
이러한 구성의 BGA패키지는 반도체칩(21)으로 부터 출력된 신호가 와이어(23)를 통해서 회로패턴(25a)으로 전달되며, 상기 회로패턴(25a)으로 전달된 신호는 여기에 융착되어 있는 솔더볼(22)을 통하여 마더보드로 전달되어 주변소자로 전달된다. 주변소자에 발생된 신호가 반도체칩(21)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.The BGA package having such a configuration transmits a signal output from the semiconductor chip 21 to the circuit pattern 25a through the wire 23, and the signal transmitted to the circuit pattern 25a is fused to the solder ball ( 22) is transferred to the motherboard through the peripheral element. When the signal generated in the peripheral device is transferred to the semiconductor chip 21, the signal is transmitted in the reverse order of the path described above.
그러나, 이러한 BGA패키지는 내부에 내장된 반도체칩의 크기에 비해서 패키지의 크기가 몇 배 이상 크기 때문에 전자제품들을 소형화시키기에는 한계가 있었던 것이다. 또한, 상기의 BGA패키지는 회로기판이 고가이므로 제품의 가격이 상승되는 요인이 됨은 물론, 상기 회로기판을 통해서 습기가 침투됨으로써 크랙이 발생하게 되는 문제점이 있다.However, such a BGA package has a limitation in miniaturizing electronic products because the package size is several times larger than the size of a semiconductor chip embedded therein. In addition, the BGA package has a problem that the price of the product is increased because the circuit board is expensive, as well as cracks are generated by the penetration of moisture through the circuit board.
이와같은 문제점을 해결하기 위하여, BGA 방식이 아니면서도 기판 접속리드를 패키지의 외부로 돌출 시키지 않고 패키지의 하면으로 노출시킴으로써 실장면적을 줄임과 동시에, 반도체 패키지의 크기를 반도체칩의 크기로 형성하여 패키지를 경박단소화 한 BLP(Bottom Leaded Package)형 CSP(Chip Scale Package)가 제3도에 도시되어 있다.In order to solve such a problem, the surface area of the package is reduced by exposing the board connection lead to the bottom surface of the package without protruding the outside of the package, and the size of the semiconductor package is formed as the size of the semiconductor chip. A BLP (Bottom Leaded Package) type Chip Scale Package (CSP) is shown in FIG.
이러한 종래의 BLP형의 CSP의 구조는 전자회로가 집적되어 있는 반도체칩(31)과, 상기 반도체칩(31)을 지지함과 아울러 반도체칩(31)의 신호르 외부로 전기적 접속 경로를 이루는 리드(32)와, 상기 반도체칩(31)을 전기적으로 연결시키는 와이어(33)와, 상기의 반도체칩(31), 리드(32) 및 와이어(33)를 외부환경으로 부터 보호하기 위한 수지봉지재(34)를 포함하며, 상기의 리드(32)는 내측으로 수지봉지재(34)의 저면에 노출되도록 리드(32)를 절곡 형성하여서 된 것이다.The conventional BLP type CSP structure has a semiconductor chip 31 in which an electronic circuit is integrated, a lead that supports the semiconductor chip 31 and forms an electrical connection path outside the signal of the semiconductor chip 31. (32), a wire 33 for electrically connecting the semiconductor chip 31, and a resin encapsulant for protecting the semiconductor chip 31, the lead 32, and the wire 33 from an external environment. And the lead 32 is formed by bending the lead 32 to be exposed to the bottom surface of the resin encapsulant 34 inwardly.
그러나, 상기한 BLP형 CSP는 리드(32)가 수지봉지재(34)의 저면 외부로 노출되도록 되어 이 노출된 리드(32)를 입출력 단자로 사용하는데, 이는 수지봉지재(34)가 리드(32)의 노출된 부분을 가리게 되는 등의 이유로 실장시 불량이 발생되는 문제점이 있었던 것이다. 이러한 문제점을 극복하기 위하여 솔더볼을 이용하여 마더보드에 실장되는 형태도 있다.However, the BLP type CSP is such that the lead 32 is exposed to the outside of the bottom surface of the resin encapsulant 34 so that the exposed lead 32 is used as an input / output terminal. There was a problem that a defect occurs during mounting, for example, to cover the exposed part of 32). In order to overcome this problem, there is also a form that is mounted on the motherboard using a solder ball.
제4도는 종래의 CSP로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(41)과, 상기 반도체칩(41)의 신호를 외부로의 전기적 접속 경로를 이루는 리드(42)와, 상기 반도체칩(41)을 전기적으로 연결시키는 범프(43)와, 상기의 반도체칩(41), 리드(42) 및 범프(43)를 외부환경으로 부터 보호하기 위한 수지봉지재(44)를 포함하며, 상기의 리드(42)는 내측으로 수지봉지재(44)의 저면에 노출되도록 리드(42)를 절곡 형성하여서 된 것이다.4 shows a conventional CSP, the structure of which is a semiconductor chip 41 in which electronic circuits are integrated, a lead 42 which forms an electrical connection path to a signal from the semiconductor chip 41 to the outside, and the semiconductor chip. A bump 43 for electrically connecting the 41 and a resin encapsulant 44 for protecting the semiconductor chip 41, the lead 42, and the bump 43 from an external environment. The lead 42 is formed by bending the lead 42 to be exposed to the bottom surface of the resin encapsulant 44 inwardly.
그러나, 상기한 CSP는 리드(42)를 절곡 형성한 상태의 패키지이므로 리드(42)의 절곡부 만큼 패키지의 두께 및 면적이 커지게 되어 CSP에 적합하지가 않은 것이다. 또한, 리드(42)를 절곡 형성하기 위한 공정상의 어려움이 있는 것이다.However, since the CSP is a package in which the lead 42 is bent, the thickness and area of the package are increased by the bent portion of the lead 42, which is not suitable for the CSP. In addition, there is a difficulty in the process for bending the lead 42.
본 발명의 목적은 이와같은 문제점을 해결하기 위하여 발명된 것으로서, 테이프에 부착된 리드의 상부에 반도체칩을 부착하여 와이어 본딩을 한 다음, 수지봉지재로 몰딩공정 후에 상기의 테이프를 떼어냄으로서 간단하게 패키지를 제조함으로서 패키지의 크기를 반도체칩의 크기로 할 수 있는 CSP의 구조 및 제조방법을 제공함에 있다.An object of the present invention is to solve the above problems, it is simple by attaching a semiconductor chip on top of the lead attached to the tape to wire bonding, and then peeling off the tape after molding process with a resin encapsulant. By manufacturing a package to provide a structure and a manufacturing method of the CSP that can make the package size to the size of the semiconductor chip.
제1도는 종래의 일반적인 반도체 패키지의 구조를 나타낸 단면도1 is a cross-sectional view showing the structure of a conventional general semiconductor package
제2도는 종래의 BGA패키지의 구조를 나타낸 단면도2 is a cross-sectional view showing the structure of a conventional BGA package
제3도는 종래의 BLP형 CSP의 구조를 나타낸 단면도3 is a cross-sectional view showing the structure of a conventional BLP type CSP
제4도는 종래의 CSP의 구조를 나타낸 단면도4 is a cross-sectional view showing the structure of a conventional CSP
제5도는 본 발명에 따른 CSP의 구성을 나타낸 단면도5 is a cross-sectional view showing the configuration of a CSP according to the present invention
제6도는 본 발명의 실시예에 따른 CSP의 구성을 나타낸 단면도6 is a cross-sectional view showing the configuration of a CSP according to an embodiment of the present invention
제7도는 본 발명에 따른 CSP의 저면도7 is a bottom view of a CSP according to the present invention.
제8도는 본 발명에 따른 CSP의 제조공정을 나타낸 도면8 is a view showing a manufacturing process of the CSP according to the present invention
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
51 : 반도체칩 52 : 리드51: semiconductor chip 52: lead
53 : 와이어 54 : 수지봉지재53: wire 54: resin encapsulant
55 : 접착수단 56 : 테이프55: bonding means 56: tape
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제5도는 본 발명에 따른 CSP(Chip Scale Package ; 칩 스케일 패키지)의 구조를 나타낸 단면도이고, 제6도는 본 발명의 CSP의 저면에 솔더볼이 융착된 상태의 단면도이며, 제7도는 본 발명에 따른 CSP의 저면도를 나타낸 도면으로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(51)과, 상기 반도체칩(51)의 신호를 전기적 접속시키는 와이어(53)와, 상기 와이어(53)에 연결되어 반도체칩(51)의 신호를 외부로 전달하는 리드(52)와, 상기의 반도체칩(51), 와이어(53) 및 리드(52)를 외부환경으로 부터 보호하기 위하여 감싸진 수지봉지재(54)를 포함하며, 상기의 리드(52)는 반도체칩(51)의 저면에 접착수단(55)에 의해 접착되어 수지봉지재(54)의 저면으로 열과 행을 가지면서 배열되어 있는 것을 특징으로 한다.5 is a cross-sectional view showing a structure of a chip scale package (CSP) according to the present invention, Figure 6 is a cross-sectional view of a solder ball fused to the bottom surface of the CSP of the present invention, Figure 7 is a A bottom view of the CSP, which has a structure in which a semiconductor chip 51 in which an electronic circuit is integrated, a wire 53 for electrically connecting signals of the semiconductor chip 51, and a connection to the wire 53. And a lead encapsulating member 52 which transmits a signal of the semiconductor chip 51 to the outside, and a resin encapsulant wrapped to protect the semiconductor chip 51, the wire 53, and the lead 52 from an external environment. 54, wherein the lead 52 is bonded to the bottom of the semiconductor chip 51 by an adhesive means 55, and is arranged with rows and rows on the bottom of the resin encapsulant 54. do.
상기의 리드(52) 저면에는 다수의 열과 행으로 배열되는 솔더볼(57)을 융착시킬 수 있고, 상기의 접착수단(55)은 테이프를 사용하거나, 또는 에폭시로 접착시키는 것이다.The solder 52 may be fused to the bottom surface of the lead 52 in a plurality of rows and rows, and the bonding means 55 may be taped or epoxy bonded.
상기와 같이 구성된 본 발명의 CSP는 반도체칩(51)의 크기로 반도체패키지를 형성할 수 있는 것으로, 그 작용은 반도체칩(51)으로 부터 출력된 신호가 와이어(53)를 통해서 리드(52)로 전달되며, 상기 리드(52)로 전달된 신호는 마더보드(Mother Board)로 전달되어 주변소자로 전달된다. 주변소자에서 발생된 신호가 반도체칩(51)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.The CSP of the present invention configured as described above can form a semiconductor package with the size of the semiconductor chip 51, the function of which is the signal output from the semiconductor chip 51 through the lead 53 through the wire 53 The signal transmitted to the lead 52 is transmitted to the motherboard (mother board) is delivered to the peripheral element. When the signal generated from the peripheral device is transferred to the semiconductor chip 51, the signal is transmitted in the reverse order of the path described above.
이와같은 본 발명의 CSP 제조방법은, 제8도에 도시된 바와같이 테이프(56)의 상부에 리드(52)를 접착하는 단계와, 상기 리드(52)의 상부에 전자회로가 집적되어 있는 반도체칩(51)의 저면을 접착수단(55)에 의해 부착하는 단계와, 상기 반도체칩(51)의 신호를 리드(52)에 전기적으로 접속시키기 위해 와이어(53)로 본딩하는 단계와, 상기의 반도체칩(51)과 와이어(53)를 포함하여 리드(52)의 상부를 수지봉지재(54)로 몰딩하는 단계와, 상기의 몰딩 단계 후에 리드(52)의 저면이 노출되도록 테이프(56)를 떼어내는 단계로 이루어지는 것을 특징으로 한다.Such a CSP manufacturing method of the present invention comprises the steps of adhering the lead 52 to the upper portion of the tape 56, as shown in Figure 8, and the semiconductor in which the electronic circuit is integrated on the upper portion of the lead 52 Attaching the bottom surface of the chip 51 by the bonding means 55, bonding the signal of the semiconductor chip 51 with the wire 53 to electrically connect the signal to the lead 52, and Molding the upper portion of the lead 52 including the semiconductor chip 51 and the wire 53 with the resin encapsulant 54, and the tape 56 so that the bottom surface of the lead 52 is exposed after the molding step. Characterized in that the step consisting of removing.
상기 리드(52)의 저면에 다수의 열과 행으로 배열되도록 솔더볼(57)을 융착시키는 단계로 포함한다. 또한, 상기의 리드(52) 상부에 반도체칩(51)을 부착시키는 접착수단(55)은 테이프로 부착시킬 수 있고, 또는 리드(52)의 상면에 에폭시를 도포하여 부착시킬 수 있는 것으로, 상기의 리드(52)는 저면 전체에 열과 행을 가지도록 어레이 시킬 수 있어 면적당 보다 많은 리드(52)를 형성함으로서 다핀화가 가능한 것이다.And welding the solder balls 57 to the bottom surface of the lead 52 in a plurality of rows and columns. In addition, the adhesive means 55 for attaching the semiconductor chip 51 to the upper part of the lead 52 can be attached with a tape, or can be attached by applying an epoxy to the upper surface of the lead 52. The leads 52 can be arrayed to have columns and rows on the entire bottom, so that more leads 52 can be formed per area, thereby making it possible to multiply.
상기의 제조방법에 의해 형성된 본 발명의 CSP는 반도체칩의 크기로 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 패키지이다.The CSP of the present invention formed by the above-described manufacturing method is a package that can reduce the size of the package to the size of the semiconductor chip, reduce the size of the package, as well as achieve high integration and high performance.
이상의 설명에서와 같은 본 발명의 CSP에 의하면, 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 효과가 있다.According to the CSP of the present invention as described above, by forming the size of the semiconductor package to the size of the semiconductor chip, it is possible to reduce the size of the semiconductor package to reduce the size and light weight, as well as high integration and high performance.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960062304A KR100251860B1 (en) | 1996-12-06 | 1996-12-06 | Structure of csp and its making method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960062304A KR100251860B1 (en) | 1996-12-06 | 1996-12-06 | Structure of csp and its making method |
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| Publication Number | Publication Date |
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| KR19980044242A KR19980044242A (en) | 1998-09-05 |
| KR100251860B1 true KR100251860B1 (en) | 2000-04-15 |
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| KR19990000394A (en) * | 1997-06-05 | 1999-01-15 | 윤종용 | Chip scale package and its manufacturing method |
| KR100576889B1 (en) * | 2000-12-29 | 2006-05-03 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0883878A (en) * | 1994-09-09 | 1996-03-26 | Kawasaki Steel Corp | Package for semiconductor ic chip, production thereof and lead frame |
| JPH0888295A (en) * | 1994-09-19 | 1996-04-02 | Mitsui High Tec Inc | Semiconductor device |
| JPH08148603A (en) * | 1994-11-22 | 1996-06-07 | Nec Kyushu Ltd | Ball grid array type semiconductor device and manufacture thereof |
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1996
- 1996-12-06 KR KR1019960062304A patent/KR100251860B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0883878A (en) * | 1994-09-09 | 1996-03-26 | Kawasaki Steel Corp | Package for semiconductor ic chip, production thereof and lead frame |
| JPH0888295A (en) * | 1994-09-19 | 1996-04-02 | Mitsui High Tec Inc | Semiconductor device |
| JPH08148603A (en) * | 1994-11-22 | 1996-06-07 | Nec Kyushu Ltd | Ball grid array type semiconductor device and manufacture thereof |
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