KR19980044247A - Molding method of semiconductor package - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a molding method of a semiconductor package, wherein the manufacturing method of a semiconductor package including a raw material inspection, a sawing process, a semiconductor chip bonding process, a wire bonding process, and a molding process is exposed to the bottom surface of the resin encapsulant before the molding process. Including the tape attaching process to attach the tape to the lead in advance to prevent the flash generated after the molding process, it prevents defects of the package and improves the performance of the package. It is to enable high performance.

Description

Molding method of semiconductor package

The present invention relates to a method of molding a semiconductor package, and more particularly, to prevent the occurrence of a flash (Flash) when molding the semiconductor package exposed to the bottom surface of the package, as well as to prevent defects of the package, By improving the performance of the package, the package can be made lighter and thinner for high integration and high performance.

Generally, semiconductor packages include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into insertion type and surface mount technology (SMT) type according to the mounting method. Representative types of insertion type include DIP (Dual In-line Package) and PGA (Pin Grid Array). Typical examples of the mounting type include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrie), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array).

Recently, in order to increase the mounting degree of components of a printed circuit board according to the miniaturization of electronic products, surface mount type semiconductor packages are widely used rather than insert type semiconductor packages. The structure of such a conventional package is described with reference to FIGS. 1 and 2. The following describes the BGA package.

1 is a QFP of a conventional general semiconductor package, the structure of which is a semiconductor chip 11 in which an electronic circuit is integrated, a mounting plate 15 to which the semiconductor chip 11 is attached by an epoxy 16, and A plurality of leads 12 capable of transmitting signals of the semiconductor chip 11 to the outside, wires 13 connecting the semiconductor chips 11 and the leads 12, the semiconductor chips 11, In order to protect other peripheral components from external oxidation and corrosion, it is made of a resin rod support 14 wrapped around the outside thereof.

However, the above QFP has a higher number of pins as the semiconductor chip is gradually improved in performance. However, it is technically difficult to narrow the distance between the pins to a certain value or less. The disadvantage is that the package becomes large. This is a problem that results in the contrary to the trend of miniaturization of semiconductor packages.

The BGA package, which emerged to solve the technical demands of the multi-pinning method, can accept a larger number of input / output signals than the QFP by using solder balls fused to the entire surface of the semiconductor package as an input / output means. Is smaller than QFP.

As shown in FIG. 2, the BGA package includes a circuit board 25 having a circuit pattern 25a formed thereon, and a solder mask 25b coated thereon to protect the circuit pattern 25a. The semiconductor chip 21 attached to the center of the upper surface of the circuit board 25 and the wire 23 for electrically connecting the semiconductor chip 21 and the circuit pattern 25a of the circuit board 25 to transmit a signal. And solder balls 22 fused to the circuit patterns 25a of the circuit board 25 to transmit signals to the outside, and to protect the semiconductor chip 21 and other peripheral components from external oxidation and corrosion. It consists of a resin encapsulation agent 24 wrapped around the outside.

However, such a BGA package has a limitation in miniaturizing electronic products because the package size is several times larger than the size of a semiconductor chip embedded therein. In addition, the BGA package has a problem that the price of the product is increased because the circuit board is expensive, as well as cracks are generated by the penetration of moisture through the circuit board.

In order to solve such a problem, the mounting area is reduced by exposing the board connection lead to the bottom surface of the package without protruding the outside of the package without forming a BGA method, and the size of the semiconductor package is formed as the size of the semiconductor chip. A BLP (Bottom Leaded Package) type Chip Scale Package (CSP) having a light weight and short size is shown in FIG. 3.

The structure of the conventional BLP type CSP includes a semiconductor chip 31 in which an electronic circuit is integrated, a lead that supports the semiconductor chip 31 and forms an electrical connection path to an external signal of the semiconductor chip 31 ( 32, a wire 33 electrically connecting the semiconductor chip 31, and a resin encapsulant for protecting the semiconductor chip 31, the lead 32, and the wire 33 from an external environment ( 34), and the lead 32 is formed by bending the lead 32 to be exposed to the bottom surface of the resin encapsulant 34 inward.

However, the BLP type CSP is bent the lead 32 to be exposed to the outside of the bottom surface of the resin encapsulant 34, so that the exposed lead 32 is used as an input / output terminal. There was a problem that a defect occurs because the encapsulant 34 covers the exposed portion of the lid 32.

An object of the present invention has been invented to solve such a problem, a molding method of a semiconductor package to prevent the occurrence of flash (Flash) when molding the semiconductor package exposed to the bottom surface of the package with a resin encapsulation material. In providing.

1 is a cross-sectional view showing the structure of a conventional semiconductor package in the related art

Figure 2 is a cross-sectional view showing the structure of a conventional BGA package

Figure 3 is a cross-sectional view showing the structure of a conventional BLP type CSP

Figure 4 is a cross-sectional view of a package showing a state before the molding process according to the present invention

5 is a cross-sectional view of a package showing a state after the molding process according to the present invention.

Explanation of symbols on the main parts of the drawings

41: semiconductor chip 42: lead

43: wire 44: resin encapsulant

45: Tape

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The structure of the semiconductor package according to the present invention includes a semiconductor chip 41 in which an electronic circuit is integrated, a wire 43 for electrically connecting signals of the semiconductor chip 41, and a semiconductor connected to the wire 43. A lead 42 for transmitting the signal of the chip 41 to the outside, and a molded resin encapsulant 44 to protect the semiconductor chip 41, the wire 43, and the lead 42 from an external environment. The lead 42 is a semiconductor package exposed to be arranged with a plurality of columns and rows on the bottom surface of the resin encapsulant 44.

The manufacturing process of the semiconductor package structured as described above is a raw material inspection to check wafer defects largely, a sawing process of cutting the wafer to separate the semiconductor chips 41 individually, and attaching the separated semiconductor chips 41 to the lead frame. A semiconductor chip bonding process, a wire bonding process for electrically connecting a signal of the semiconductor chip 41 to the lead 42, and a resin for protecting the semiconductor chip 41, the wire 43, and the lead 42 from the external environment. It consists of a molding process and the like wrapped with an encapsulant.

In this case, after the molding process, a flash is generated to cause a defect of the package. In order to prevent such a flash, the tape on the lead 42 exposed to the bottom surface of the resin encapsulant 44 before the molding process is prevented. By including the tape attaching step of attaching (45), the flash generated after the molding step can be prevented.

The tape 45 may be an ultraviolet-ray tape, a thermoset tape, a thermoplastic tape, or the like. In order to remove the tape 45 after the molding process, the tape 45 may be used. The ultraviolet ray tape of the present invention can be easily removed by irradiation with ultraviolet rays, and the above-mentioned thermosetting or thermoplastic tape can be easily removed using a chemical agent. In addition, the tape 45 may be attached to the entire bottom surface of the resin encapsulant 44 or may be attached only to the lead 42 exposed to the bottom surface of the resin encapsulant 44.

As such, the molding process is performed with the tape 45 attached to the lid 42 exposed to the bottom surface of the resin encapsulant 44 before the molding process, and the tape 45 is removed to completely remove the flash generated during the molding process. It can be prevented.

According to the present invention as described above, when molding the semiconductor package exposed to the bottom surface of the package with the resin encapsulant to prevent the occurrence of a flash when molding the tape attached to the lead in advance to prevent defects In addition, it improves the package performance and has the effect of high integration and high performance.

Claims (3)

In the manufacturing process of a semiconductor package consisting of raw material inspection, sawing process, semiconductor chip bonding process, wire bonding process, and molding process, a tape attaching process for attaching the tape to the lead exposed to the bottom surface of the resin encapsulation material before the molding process Molding method of a semiconductor package to prevent the flash (Flash) generated after the molding process, including. The method of molding a semiconductor package according to claim 1, wherein the tape attaching step is attached to the entire bottom surface of the resin encapsulant. The method of claim 1, wherein the tape is formed of an ultra-violet tape, a thermoset tape, or a thermoplastic tape.