KR100230921B1 - A structure of csp and manufacturing method thereof - Google Patents
A structure of csp and manufacturing method thereof Download PDFInfo
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- KR100230921B1 KR100230921B1 KR1019960043842A KR19960043842A KR100230921B1 KR 100230921 B1 KR100230921 B1 KR 100230921B1 KR 1019960043842 A KR1019960043842 A KR 1019960043842A KR 19960043842 A KR19960043842 A KR 19960043842A KR 100230921 B1 KR100230921 B1 KR 100230921B1
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- H01L2924/181—Encapsulation
Abstract
본 발명은 CSP(Chip Scale Package : 칩 스케일 패키지)의 구조 및 제조방법에 관한 것으로, 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있도록 된 것이다.The present invention relates to a structure and a manufacturing method of a CSP (Chip Scale Package), in which the size of a semiconductor package is reduced to a size of a semiconductor chip, thereby reducing the size of the semiconductor package, And high performance.
Description
본 발명은 CSP(Chip Scale Package; 칩 스케일 패키지)의 구조 및 제조방법에 관한 것으로, 더욱 상세하게는 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 패키지의 크기를 축소하여 경박단소화 함은 물론, 고접적화 및 고성능화 할 수 있도록 된 CSP(Chip Scale Package; 칩 스케일 패키지)의 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and a manufacturing method of a CSP (Chip Scale Package), and more particularly, to a semiconductor package having a size of a semiconductor chip, And more particularly, to a structure and a manufacturing method of a CSP (Chip Scale Package) capable of high integration and high performance.
일반적으로 반도체 패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스 밀봉 패키지, 금속 밀봉 패키지 등이 있다. 이와 같은 반도체 패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology, SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로서 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array) 등이 있다.Generally, the semiconductor package includes a resin sealing package, a TCP (Tape Carrier Package) package, a glass sealing package, and a metal sealing package depending on the type thereof. Such a semiconductor package is classified into an insertion type and a surface mount technology (SMT) type according to a mounting method. Typical examples of the insertion type are a dual in-line package (DIP) and a pin grid array (PGA) Representative examples of the mounting type include a QFP (Quad Flat Package), a PLCC (Plastic Leaded Chip Carrier), a CLCC (Ceramic Leaded Chip Carrier), and a BGA (Ball Grid Array).
최근에는 전자제품의 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해서 삽입형 반도체 패키지보다는 표면실장형 반도체 패키지가 널리 사용되고 있는데, 이러한 종래의 패키지에 대한 구조를 도1과 도2를 참조하여 QFP와, BGA 패키지에 대하여 설명하면 다음과 같다.In recent years, a surface mounting type semiconductor package has been widely used rather than an insertion type semiconductor package in order to increase the component mounting degree of a printed circuit board in accordance with miniaturization of electronic products. The structure of such a conventional package will be described with reference to FIGS. 1 and 2, , And a BGA package will be described as follows.
도1은 종래의 일반적인 반도체 패키지의 QFP로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(11)과, 상기 반도체칩(11)이 에폭시(16)에 의해 부착되는 탑재판(15)과, 상기 반도체칩(11)의 신호를 외부로 전달할 수 있는 다수의 리드(12)와, 상기 반도체칩(11)과 리드(12)를 연결시켜 주는 와이어(13)와, 상기 반도체칩(11)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지수지(14)로 이루어지는 것이다.1 is a general QFP of a conventional semiconductor package having a semiconductor chip 11 on which electronic circuits are integrated, a mounting board 15 on which the semiconductor chip 11 is mounted by an epoxy 16, A plurality of leads 12 capable of transmitting signals of the semiconductor chip 11 to the outside, wires 13 connecting the semiconductor chip 11 and the leads 12, And a sealing resin 14 that surrounds the other components to protect the surrounding components from oxidation and corrosion of the outside.
이러한 구성에 의한 종래의 QFP는 반도체칩(11)으로부터 출력된 신호가 와이어(13)를 통해 리드(12)로 전달되며, 상기 리드(12)는 마더보드에 연결되어 있어 리드(12)로 전달된 신호가 마더보드를 주변소자로 전달된다. 주변소자에서 발생된 신호가 반도체칩(11)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.In the conventional QFP having such a structure, a signal outputted from the semiconductor chip 11 is transmitted to the lead 12 through the wire 13, and the lead 12 is connected to the mother board, The signal is transferred to the peripheral device from the motherboard. When a signal generated in the peripheral device is transmitted to the semiconductor chip 11, the signal is transmitted in the reverse order of the above-described path.
그러나, 상기의 QFP는 반도체칩이 점차적으로 고성능화되어 가면서 핀의 수가 더욱 더 많아지게 되는데 비하여, 핀과 핀 사이의 거리를 일정치 이하로 좁히는 것은 기술적으로 어려움이 있기 때문에 많은 핀을 모두 수용하기 위해서는 패키지가 커지게 되는 단점이 있다. 이것은 반도체 패키지의 소형화 추세에 역행하는 결과를 낳는 문제점이 있는 것이다.However, in the QFP described above, as the semiconductor chip is gradually improved in performance, the number of pins is further increased. On the other hand, since it is technically difficult to narrow the distance between the pin and the pin to a predetermined value or less, There is a disadvantage that the package becomes large. This leads to a problem that leads to a tendency to downsize the semiconductor package.
이와 같이 다핀화에 따른 기술적 요구를 해결하기 위해서 등장한 것이 BGA 패키지로서, 이는 입출력 수단으로서 반도체 패키지의 일면전체에 융착된 솔더볼을 이용함으로써 QFP 보다 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도QFP 보다 작게 형성된 것이다.In order to solve the technical requirement for multi-pinning, a BGA package has been introduced. This is because it is possible to accommodate a larger number of input / output signals than the QFP by using a solder ball fused to the entire one surface of the semiconductor package as the input / output means. The size is also smaller than QFP.
이러한 BGA 패키지의 구성은 도2에 도시된 바와 같이 표면에 회로패턴(25a)이 형성되고, 이 회로패턴(25a)을 보호하기 위해 솔더마스크(25b)가 코팅된 회로기판(25)과, 상기 회로기판(25)의 상면 중앙에 부착된 반도체칩(21)과, 상기 반도체칩(21)과 상기 회로기판(25)의 회로패턴(25a)을 전기적으로 연결하여 신호를 전달하는 와이어(23)와, 상기 회로기판(25)의 회로패턴(25a)에 융착되어 외부로 신호를 전달하는 솔더볼(22)과, 상기 반도체칩(21)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지수지(24)로 구성되는 것이다.The BGA package includes a circuit board 25 on which a circuit pattern 25a is formed and a solder mask 25b coated on the circuit board 25 to protect the circuit pattern 25a, A wire 23 for electrically connecting the semiconductor chip 21 and the circuit pattern 25a of the circuit board 25 to electrically connect the semiconductor chip 21 to the circuit pattern 25a of the circuit board 25, A solder ball 22 which is fused to the circuit pattern 25a of the circuit board 25 to transmit a signal to the outside and a protection circuit 25 for protecting the semiconductor chip 21 and other peripheral components from external oxidation and corrosion And a sealing resin 24 surrounding the outside.
이러한 구성의 BGA 패키지는 반도체칩(21)으로부터 출력된 신호가 와이어(23)를 통해서 회로패턴(25a)으로 전달되며, 상기 회로패턴(25a)으로 전달된 신호는 여기에 융착되어 있는 솔더볼(22)을 통하여 마더보드로 전달되어 주변소자로 전달된다. 주변소자에서 발생된 신호가 반도체칩(21)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.The signal output from the semiconductor chip 21 is transferred to the circuit pattern 25a through the wire 23 and the signal transferred to the circuit pattern 25a is transferred to the solder ball 22 ) To the motherboard and transferred to the peripheral devices. When a signal generated in the peripheral device is transmitted to the semiconductor chip 21, the signal is transmitted in the reverse order of the above-described path.
그러나, 이러한 BGA 패키지는 내부에 내장된 반도체칩의 크기에 비해서 패키지의 크기가 몇 배 이상 크기 때문에 전자제품들을 소형화시키기에는 한계가 있었던 것이다. 또한, 상기의 BGA 패키지는 회로기판이 고가이므로 제품의 가격이 상승되는 요인이 됨은 물론, 상기 회로기판을 통해서 습기가 침투됨으로써 크랙이 발생하게 되는 문제점이 있다.However, since the size of the package is several times larger than the size of the semiconductor chip embedded in the BGA package, the miniaturization of electronic products has been limited. In addition, since the circuit board is expensive, the BGA package has a problem that the price of the product is increased, and the moisture is penetrated through the circuit board, thereby causing cracks.
이와 같은 문제점을 해결하기 위하여, BGA 방식이 아니면서도 기판 접속리드를 패키지의 외부로 돌출 시키지 않고 패키지의 하면으로 노출시킴으로써 실장면적을 줄임과 동시에, 반도체 패키지의 크기를 반도체칩의 크기로 형성하여 패키지를 경박단소화 한 BLP(Bottom Leaded Package)형 CSP(Chip Scale Package)가 도3에 도시되어 있다.In order to solve the above problems, it is an object of the present invention to reduce the mounting area by exposing the substrate connection leads to the bottom surface of the package without protruding the package connection leads, (Bottom Leaded Package) -type CSP (Chip Scale Package) which is made thinner and thinner is shown in Fig.
이러한 종래의 BLP의 CSP의 구조는 전자회로가 집적되어 있는 반도체칩 (31)과, 상기 반도체칩(31)을 지지함과 아울러 반도체칩(31)의 신호를 외부로 전기적 접속 경로를 이루는 리드(32)와, 상기 반도체칩(31)을 전기적으로 연결시키는 와이어(33)와, 상기의 반도체칩(31), 리드(32) 및 와이어(33)를 외부 환경으로부터 보호하기 위한 봉지수지(34)를 포함하며, 상기의 리드(32)는 내측으로 봉지수지(34)의 저면에 노출되도록 리드(32)를 절곡 형성하여서 된 것이다.The conventional structure of the CSP of the conventional BLP includes a semiconductor chip 31 on which electronic circuits are integrated and a lead 31 for supporting the semiconductor chip 31 and for electrically connecting the signal of the semiconductor chip 31 to the outside A wire 33 for electrically connecting the semiconductor chip 31 and a sealing resin 34 for protecting the semiconductor chip 31, the lead 32 and the wire 33 from the external environment, And the leads 32 are formed by bending the leads 32 so as to be exposed to the bottom of the encapsulating resin 34 inwardly.
그러한 BLP형 CSP는 반도체칩(31)을 전기적으로 연결시키는 와이어(33)의 루프(Loop)의 높이 만큼 패키지의 두께가 두껍게 되고, 상기 와이어(33)를 리드(32)에 본딩하기 위한 본딩 에리어(Bonding Area) 만큼의 면적이 필요함으로서 패키지의 크기가 커지게 되는 등의 단점이 있어 CSP로 적합하지 못한 것이다. 또한, 상기의 BLP는 반도체칩(31)의 전기적인 신호를 와이어(33)를 통하여 연결시킴으로서 와이어(33) 길이 만큼의 경로가 길게 되어 동작 속도를 저하시키는 것이다.In such a BLP type CSP, the thickness of the package is increased by the height of the loop of the wire 33 electrically connecting the semiconductor chip 31 and the bonding area for bonding the wire 33 to the lead 32 (Bonding Area) is required, and the size of the package is increased, which is not suitable for CSP. In addition, the BLP connects the electrical signal of the semiconductor chip 31 through the wire 33, thereby increasing the length of the wire 33, thereby lowering the operating speed.
도4는 종래의 CSP로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(41)과, 상기 반도체칩(41)의 신호를 외부로의 전기적 접속 경로를 이루는 리드(42)와, 상기 반도체칩(41)을 전기적으로 연결시키는 범프(43)와, 상기의 반도체칩(41), 리드(42) 및 범프(43)를 외부환경으로부터 보호하기 위한 봉지수지(44)를 포함하며, 상기의 리드(42)는 내측으로 봉지수지(44)의 저면에 노출되도록 리드(42)를 절곡 형성하여서 된 것이다.4 shows a conventional CSP having a semiconductor chip 41 on which electronic circuits are integrated, a lead 42 serving as an electrical connection path to the outside of the semiconductor chip 41, And a sealing resin 44 for protecting the semiconductor chip 41, the lead 42 and the bump 43 from the external environment, wherein the bump 43 electrically connects the lead 41, (42) is formed by bending a lead (42) so as to be exposed on the bottom surface of the sealing resin (44) inward.
그러나, 상기한 CSP는 리드(42)를 절곡 형성한 상태의 패키지이므로 리드(42)의 절곡부 만큼 패키지의 두께 및 면적이 커지게 되어 CSP에 적합하지가 않은 것이다. 또한, 리드(42)를 절곡 형성하기 위한 공정상의 어려움이 있는 것이다.However, since the CSP is a package in which the lead 42 is bent, the thickness and the area of the package are increased by the bending portion of the lead 42, which is not suitable for CSP. Further, there is a difficulty in the process for bending the lead 42. [
본 발명의 목적은 이와 같은 문제점을 해결하기 위하여 발명된 것으로서, 반도체칩의 신호인출패드를 직접 리드에 연결하여 전기적인 신호를 전달하도록 하고, 리드의 절곡부를 없앰으로서 반도체 패키지의 크기를 반도체칩의 크기로 한 CSP의 구조 및 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor chip which is capable of connecting a signal lead pad of a semiconductor chip directly to a lead to transmit an electrical signal, And a method of manufacturing the same.
제1도는 종래의 일반적인 반도체 패키지의 구조를 나타낸 단면도.FIG. 1 is a sectional view showing the structure of a conventional general semiconductor package; FIG.
제2도는 종래의 BGA 패키지의 구조를 나타낸 단면도.FIG. 2 is a sectional view showing the structure of a conventional BGA package;
제3도는 종래의 BLP형 CSP의 구조를 나타낸 단면도.3 is a sectional view showing the structure of a conventional BLP type CSP.
제4도는 종래의 CSP의 구조를 나타낸 단면도.FIG. 4 is a sectional view showing the structure of a conventional CSP. FIG.
제5도는 본 발명에 따른 CSP의 구성을 나타낸 단면도.FIG. 5 is a cross-sectional view showing a configuration of a CSP according to the present invention; FIG.
제6도는 본 발명에 따른 CSP가 마더보드에 실장된 상태를 나타낸 단면도.FIG. 6 is a sectional view showing a state in which a CSP according to the present invention is mounted on a motherboard;
제7도는 본 발명에 따른 CSP의 실시예를 나타낸 단면도.FIG. 7 is a sectional view showing an embodiment of a CSP according to the present invention; FIG.
제8도는 이방성전도필름의 구조를 나타낸 단면도.FIG. 8 is a sectional view showing the structure of an anisotropic conductive film; FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
51 : 반도체칩 52 : 리드51: semiconductor chip 52: lead
53 : 범프 54 : 봉지수지53: bump 54: sealing resin
55 : 이방성전도필름(Anisotropic Conductive Film)55: Anisotropic Conductive Film
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 CSP(Chip Scale Package; 칩 스케일 패키지)를 나타낸 단면도이고, 도6은 본 발명에 따른 CSP를 마더보드에 실장한 상태의 단면도로서 그 구조는 전자회로가 집적되어 있는 반도체칩(51)과, 상기 반도체칩(51)의 신호를 전기적 접속시키는 범프(53)와, 상기 범프(53)에 연결되어 반도체칩(51)의 신호를 외부로 전달하는 리드(52)와, 상기의 반도체칩(51), 범프(53) 및 리드(52)를 외부환경으로부터 보호하기 위하여 감싸진 봉지수지(54)로 이루어지는 반도체 패키지에 있어서, 상기 리드(52)는 봉지수지(54)의 측면으로 돌출 됨이 없이 봉지수지(54)의 저면으로 노출되고, 상기 범프(53)와 리드(52)는 이방성전도필름 (55; Anisotropic Conductive Film)에 의해 전기적으로 연결된 것을 특징으로 한다.6 is a cross-sectional view of a CSP (Chip Scale Package) according to the present invention, in which a CSP according to the present invention is mounted on a motherboard, A lead 52 connected to the bump 53 to transmit a signal of the semiconductor chip 51 to the outside, and a semiconductor chip 51 connected to the bump 53. The bump 53 is electrically connected to the semiconductor chip 51, Wherein the lead (52) is protruded to the side of the sealing resin (54), and the lead (52) is protruded toward the side of the sealing resin (54) The bump 53 and the lead 52 are electrically connected to each other by an anisotropic conductive film 55 without being exposed to the bottom surface of the encapsulating resin 54 without being exposed.
도7은 본 발명에 따른 CSP의 실시예를 나타낸 단면도로서, 그 구성은 본 발명의 구성에서 반도체칩(51)의 상면을 봉지수지(54)의 외부로 노출시킨 것이다. 이와 같이 반도체칩(51)의 상면을 외부로 노출시키면, 상기 반도체칩(51)의 회로 동작시 발생되는 열을 효율적으로 외부로 방출시킴으로 패키지의 성능을 향상시킬 수 있다.7 is a cross-sectional view showing an embodiment of the CSP according to the present invention. In the structure of the present invention, the upper surface of the semiconductor chip 51 is exposed to the outside of the encapsulating resin 54. By exposing the upper surface of the semiconductor chip 51 to the outside, the heat generated during the circuit operation of the semiconductor chip 51 is efficiently discharged to the exterior, thereby improving the performance of the package.
상기에 있어서, 범프(53)와 리드(52)를 전기적으로 연결하는 이방성전도필름 (55; Anisotropic Conductive Film)은 도8에 도시된 바와 같이 대략 50㎛ 두께로 된 접착필름(55a)의 내부에 대략 5㎛의 직경으로 된 수백개의 금속성알맹이(55b)에 폴리머(Polymer)가 코팅되어 있는 것으로, 이러한 이방성전도필름(55)은 열압착시 압착된 부분은 열로 인하여 금속성알맹이(55b)에 코팅된 폴리머가 녹게 되어 통전상태를 유지하고, 그 외 부분은 절연상태를 유지하는 것이다. 이때, 범프(53)의 사이즈는 30㎛으로 형성되는 것이 가장 이상적이다.8, an anisotropic conductive film 55 for electrically connecting the bumps 53 and the leads 52 is formed on the inside of the adhesive film 55a having a thickness of about 50 mu m Polymer is coated on several hundreds of metal particles 55b having a diameter of about 5 占 퐉. Such anisotropic conductive film 55 is formed by coating the metal particles 55b on the pressed portion during thermocompression The polymer is melted to maintain the energized state, and the other part is maintained in an insulated state. At this time, it is most ideal that the size of the bumps 53 is 30 mu m.
상기와 같이 구성된 본 발명의 CSP는 반도체칩(51)의 크기로 반도체 패키지를 형성할 수 있는 것으로, 그 작용은 반도체칩(51)으로부터 출력된 신호가 범프(53)를 통해서 리드(52)로 직접 전달되며, 상기 리드 (52)로 전달된 신호는 마더보드(56 : Mother Board)로 전달되어 주변소자로 전달된다. 주변소자에서 발생된 신호가 반도체칩(51)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.The CSP of the present invention having the above-described structure can form a semiconductor package with the size of the semiconductor chip 51. The action of the CSP is that the signal output from the semiconductor chip 51 passes through the bump 53 to the lead 52 And the signal transmitted to the lead 52 is transferred to the mother board 56 and transferred to the peripheral device. When a signal generated in the peripheral device is transmitted to the semiconductor chip 51, the signal is transmitted in the reverse order of the above-described route.
이와 같은 본 발명의 CSP 제조방법은, 전자회로가 집적되어 있는 반도체칩(51)의 신호를 전기적 접속시키는 범프(53)를 형성하는 단계와, 상기의 범프(53)에 연결되어 반도체칩(51)의 신호를 외부로 전달하는 리드(52)를 제공하는 단계와, 상기 리드(52)와 범프(53) 사이에 이방성전도필름(55; Anisotropic Conductive Film)을 개재하여 열압착에 의해 상기 리드(52)와 범프(53)를 전기적 연결시키는 단계와, 상기 반도체칩(51)과 범프(53) 및 리드(52)를 포함하여 외부환경으로부터 보호하도록 봉지수지(54)로 몰딩하는 단계와, 상기의 봉지수지(54) 측면으로 돌출되는 리드(52)를 절단하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The method of manufacturing a CSP according to the present invention includes the steps of forming a bump 53 for electrically connecting a signal of a semiconductor chip 51 on which electronic circuits are integrated and a step of connecting the semiconductor chip 51 (55) by thermocompression via an anisotropic conductive film (55) between the lead (52) and the bump (53) to provide a lead (52) 52 and the bump 53 and molding the encapsulation resin 54 so as to protect the semiconductor chip 51 from the external environment including the bump 53 and the lead 52, And cutting the lead (52) projecting to the side of the sealing resin (54).
상기한 제조방법에 의해 형성되는 본 발명의 CSP는 반도체칩의 크기로 패키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 패키지이다.The CSP of the present invention formed by the above-described manufacturing method is a package which can reduce the size of the package by the size of the semiconductor chip and can reduce the thickness and shorten the circuit size, as well as achieve high integration and high performance.
이상의 설명에서와 같은 본 발명의 CSP에 의하면, 반도체 패키지의 크기를 반도체칩의 크기로 형성함으로서, 반도체 페키지의 크기를 축소하여 경박단소화 함은 물론, 고집적화 및 고성능화 할 수 있는 효과가 있다.According to the CSP of the present invention as described above, since the size of the semiconductor package is made to be the size of the semiconductor chip, the size of the semiconductor package can be reduced to reduce the size and thickness of the semiconductor package, and to achieve high integration and high performance.
Claims (3)
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| KR100576889B1 (en) * | 2000-12-29 | 2006-05-03 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
| KR20010069358A (en) * | 2001-03-14 | 2001-07-25 | 임종철 | Semiconductor chip bonding by eutectic alloy balls embedded in anisotropic conducting film |
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