KR20020057358A - Multichip module package and manufacture methode the same - Google Patents
Multichip module package and manufacture methode the same Download PDFInfo
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- KR20020057358A KR20020057358A KR1020010000349A KR20010000349A KR20020057358A KR 20020057358 A KR20020057358 A KR 20020057358A KR 1020010000349 A KR1020010000349 A KR 1020010000349A KR 20010000349 A KR20010000349 A KR 20010000349A KR 20020057358 A KR20020057358 A KR 20020057358A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는 멀티 칩 모듈(multi chip module)용 패키지의 구조 및 제조방법에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a structure and a manufacturing method of a package for a multi chip module.
일반적으로 반도체패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스밀봉 패키지, 금속밀봉 패키지 등이 있다. 이와 같은 반도체 패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology,SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로서 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic LeadedChip Carrier), BGA(Ball Grid Array) 등이 있다.In general, semiconductor packages may include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into insert type and surface mount technology (SMT) type according to the mounting method. Representative types include insert type dual in-line package (DIP) and pin grid array (PGA). Typical examples of the mounting type include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array).
또한, 단일의 패키지 안에는 반도체 칩이 한 개 들어있는 것이 보통이나 단일 패키지 안에 2개 이상의 칩이 있는 경우도 있다. 이러한 패키지를 일컬어 소위 멀티 칩 모듈(MCM: multi chip module)이라고 하는바, 이러한 멀티 칩 모듈은 메모리의 용량증가, 속도증가 등 성능면에서 우수하고 비용이 절감되어 전기적 성능과 보드 밀도, 그리고 표면실장 수율이 중요한 메모리 모듈, 핵심 로직 칩셋, 마이크로 프로세서, 마이크로 컨트롤러 시스템에 이상적인 패키지이다. 따라서 멀티칩 모듈 패키지는 랩탑, 휴대용 컴퓨터, 서브 노트북, 텔레콤, 무선기기, PC 카드 등에 주로 사용된다.Also, a single package usually contains one semiconductor chip, but sometimes there are two or more chips in a single package. Such a package is called a multi chip module (MCM). The multi chip module is excellent in terms of performance, such as increased memory capacity and speed, and reduced cost, resulting in electrical performance, board density, and surface mount. Ideal for yield-critical memory modules, key logic chipsets, microprocessors and microcontroller systems. Multichip module packages are therefore commonly used in laptops, portable computers, sub-notebooks, telecoms, wireless devices, and PC cards.
도 1에는 종래 멀티칩 모듈 패키지의 단면도를 도시하였다.1 is a cross-sectional view of a conventional multichip module package.
도면을 참조하면, 상기 멀티칩 모듈 패키지는 단일 인쇄회로기판(PCB:Printed Circuit Board)(8)에 2개 이상의 칩(10)이 부착되어 있다. 상기 칩(10)은 동일한 기능을 갖는 IC회로를 내장할 수도 있으며, 서로 상이한 기능을 갖는 IC회로를 내장할 수도 있다.Referring to the drawings, the multi-chip module package has two or more chips 10 attached to a single printed circuit board (PCB) 8. The chip 10 may have an IC circuit having the same function or an IC circuit having different functions.
상기 인쇄회로기판(8)은 기판용 열경화성 수지(2), 통상 BT 수지(2) 위로 구리박막(4)이 패턴 형성되고, 상기 구리박막(4) 패턴이 형성된 부분위로 솔더마스크(6)가 도포되는바, 상기 솔더마스크(6)는 절연성을 지니고 있으며, 전체 구리박막(4) 위로 도포되지 않고 일부의 구리박막(4)은 오픈 시키는데 상기 오픈된 구리박막(4)이 와이어(12)가 본딩되는 패드(4a)가 된다.The printed circuit board 8 has a copper thin film 4 patterned on a thermosetting resin 2 for a substrate, usually a BT resin 2, and a solder mask 6 is formed on a portion where the copper thin film 4 pattern is formed. As applied, the solder mask 6 is insulative and does not apply over the entire copper thin film 4 but opens a portion of the copper thin film 4. The open copper thin film 4 is connected to the wire 12. It becomes the pad 4a to be bonded.
상기 인쇄회로기판(8)에는 2개 이상의 반도체 칩(10)이 부착되고, 상기 반도체 칩(10)과 인쇄회로기판 간에는 전기신호가 교환되어야 하므로 알루미늄이나 골드 와이어(12)로 칩의 패드와 인쇄회로기판(8)의 패드(4a)에 본딩하여 접속시킨다.Two or more semiconductor chips 10 are attached to the printed circuit board 8, and electrical signals must be exchanged between the semiconductor chip 10 and the printed circuit board, so that the pads of the chips are printed with aluminum or gold wires 12. The pad 4a of the circuit board 8 is bonded and connected.
이와 같이 접속시킨 인쇄회로기판(8)과 칩(10)의 어셈블리를 외력에서 보호하여 손상을 방지하고 운반이 용이하도록 상부를 몰딩하는바, 통상 열경화성 에폭시(14)로 몰딩하여 패키징한다.The assembly of the printed circuit board 8 and the chip 10 connected in this way is protected from external force and molded to the top to prevent damage and to be easily transported, and is usually packaged by molding with a thermosetting epoxy 14.
상기 멀티 칩 모듈 패키지는 마더보드(도시 생략)에 실장되기 위해서는 마더보드와 접속될 부분이 형성되어야 하므로 반도체 패키지 실장방법의 대표적인BGA(Ball Grid Array)방식을 사용하여 멀티칩 모듈 패키지의 배면의 볼 패드(15)에 전도성 볼(16)을 부착함으로써 멀티칩 모듈 패키지가 최종 완성된다.In order to be mounted on a motherboard (not shown), the multi-chip module package needs to be formed with a portion to be connected to the motherboard. By attaching the conductive balls 16 to the pad 15, the multichip module package is finally completed.
상술한 멀티칩 모듈 패키지는 단일 칩 패키지보다 인쇄회로기판의 면적이 넓어서 몰딩되는 부분도 넓어지므로 몰딩되는 상측부분이 몰딩시 상당한 고열을 받게 되다.Since the multi-chip module package described above has a larger area of the printed circuit board than the single chip package, the molded part also becomes wider, and thus the upper part of the molded part receives a considerable heat during molding.
이로 인해 인쇄회로기판은 상부와 하부의 열팽창 계수의 차이로 인하여 워피지(warpage)가 발생하게 되고 이러한 워피지는 멀티칩 모듈 패키지의 불량을 초래하고 신뢰성을 저하시키는 문제점이 있다.As a result, warpage occurs due to a difference in thermal expansion coefficients between the upper and lower parts of the printed circuit board, and the warpage causes a defect of the multichip module package and reduces the reliability.
본 발명은 상술한 종래 기술의 문제점을 해결하고자 안출된 발명으로서, 칩이 장착되어 있는 상부만이 몰딩되어 있는 멀티칩 모듈 패키지의 하부에도 상부의 몰딩재와 동일하거나 그에 상당하는 열팽창계수를 갖도록 몰딩, 또는 프린팅하여 인쇄회로기판의 워피지를 제거할 수 있는 멀티칩 모듈 패키지의 구조 및 제조방법을 제공하는 것을 그 목적으로 한다.The present invention has been made to solve the above-described problems of the prior art, and molding to have a thermal expansion coefficient equal to or equivalent to that of the upper molding material in the lower portion of the multi-chip module package in which only the upper part where the chip is mounted is molded An object of the present invention is to provide a structure and a manufacturing method of a multichip module package capable of removing warpage of a printed circuit board by printing or printing.
도 1 은 종래 멀티칩 모듈 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional multichip module package.
도 2 는 본 발명에 의한 멀티칩 모듈 패키지의 일실시예를 도시한 단면도.Figure 2 is a cross-sectional view showing an embodiment of a multichip module package according to the present invention.
도 3 은 본 발명에 의한 멀티칩 모듈 패키지의 일실시예에 사용된 핀 플레이트를 도시한 사시도.Figure 3 is a perspective view showing a pin plate used in one embodiment of a multichip module package according to the present invention.
도 4 는 본 발명에 의한 멀티칩 모듈 패키지의 제 2 실시예에 사용된 마스크를 도시한 사시도.4 is a perspective view showing a mask used in the second embodiment of the multichip module package according to the present invention;
도 5 는 본 발명에 관련된 멀티칩 모듈 패키지에 사용된 기판의 일례를 보여주는 사시도.5 is a perspective view showing an example of a substrate used in the multichip module package according to the present invention.
도 6 은 상기 도 5의 기판을 사용하여 제조된 멀티칩 모듈 패키지를 도시한 단면도.6 is a cross-sectional view illustrating a multichip module package manufactured using the substrate of FIG. 5.
** 도면의 주요 부분에 대한 부호의 설명 **** Description of symbols for the main parts of the drawing **
2: BT 수지4: 구리박막2: BT resin 4: copper thin film
4a,10a: 와이어 본드 패드6: 솔더마스크4a, 10a: wire bond pad 6: solder mask
8: 인쇄회로기판10: 칩8: printed circuit board 10: chip
12: 와이어14,14': 봉지수단12: wire 14,14 ': sealing means
15: 볼 패드16: 전도성 볼15: ball pad 16: conductive ball
40: 통공부, 슬릿40: through hole, slit
상기 목적을 달성하기 위하여 본 발명의 멀티칩 모듈 패키지의 구조는,The structure of the multichip module package of the present invention to achieve the above object,
인쇄회로기판(8)과;A printed circuit board 8;
상기 인쇄회로기판(8)에 부착되며 접속부재(12)에 의해 접속되는 적어도 2개 이상의 반도체 칩(10)과;At least two semiconductor chips (10) attached to the printed circuit board (8) and connected by a connecting member (12);
상기 인쇄회로기판(8)의 배면 볼 패드(15)에 부착되는 다수의 전도성 볼(16)과;A plurality of conductive balls 16 attached to the rear ball pad 15 of the printed circuit board 8;
상기 반도체 칩(10) 및 접속부재(12)가 설치된 인쇄회로기판(8)의 상부와, 인쇄회로기판(8)의 하부를 몰딩하되 전도성 볼(16)이 부착되기 위한 볼 패드(15)가 개방되는 봉지수단(14)(14');The ball pad 15 for molding the upper part of the printed circuit board 8 and the lower part of the printed circuit board 8 in which the semiconductor chip 10 and the connection member 12 are installed is attached to the conductive ball 16. Sealing means (14, 14 ') being opened;
을 포함하는 구성으로 이루어진다.It consists of a configuration comprising a.
또한, 상기 목적을 달성하기 위한 본 발명의 멀티칩 모듈 패키지 제조방법은,In addition, the multi-chip module package manufacturing method of the present invention for achieving the above object,
인쇄회로기판(8)의 상면에 적어도 2개 이상의 반도체 칩(10)을 부착하고 상기 칩(10)과 인쇄회로기판(8)의 전기 신호 입출력단자 사이를 본딩접속하는 단계와;Attaching at least two semiconductor chips (10) to the upper surface of the printed circuit board (8) and bonding the chip (10) to the electrical signal input / output terminals of the printed circuit board (8);
상기 인쇄회로기판(8)의 배면에서 전도성 볼(16)이 부착되기 위한 볼 패드(15)에 임시부재(20)를 부착하는 단계와;Attaching a temporary member (20) to a ball pad (15) for attaching conductive balls (16) on the back of the printed circuit board (8);
상기 인쇄회로기판(8)의 상면과 배면을 금형내에서 봉지수단(14)(14')으로 몰딩하는 단계와;Molding the upper and rear surfaces of the printed circuit board (8) into sealing means (14) (14 ') in a mold;
상기 인쇄회로기판(8) 배면의 몰딩부(14')에서 상기 임시부재(20)를 제거하는 단계와;Removing the temporary member (20) from the molding portion (14 ') on the back of the printed circuit board (8);
상기 임시부재(20)가 제거된 볼 패드에 전도성 볼을 부착하는 단계;를 포함한다.Attaching the conductive ball to the ball pad from which the temporary member 20 is removed.
본 발명의 구성에 대하여 첨부한 도면을 참조하면서 보다 상세하게 설명한다. 참고로 본 발명의 설명에 앞서, 설명의 중복을 피하기 위하여 종래 기술과 일치하는 부분에 대해서는 종래 도면 부호를 그대로 인용하기로한다.The structure of this invention is demonstrated in detail, referring an accompanying drawing. For reference, prior to description of the present invention, in order to avoid duplication of description, reference numerals of the conventional reference numerals are used as they are.
도 2 는 본 발명에 의한 멀티칩 모듈 패키지의 바람직한 일실시예를 도시한 단면도이다.2 is a cross-sectional view showing a preferred embodiment of a multichip module package according to the present invention.
도면을 참조하면, 인쇄회로기판(8)의 상면에는 반도체 칩(10)이 부착되어 있으며, 상기 반도체 칩(10)은 적어도 2개 이상 실장된다. 상기 반도체 칩(10)은 접속패드(10a)를 상측으로 하여 인쇄회로기판(8)과 와이어(12) 본딩에 의해 접속될 수 있으며, 상기 접속패드(10a)를 인쇄회로기판과 직접 접촉하도록 하여 플립칩(flip chip) 본딩으로 접속시키는 것도 바람직하다.Referring to the drawings, a semiconductor chip 10 is attached to an upper surface of the printed circuit board 8, and at least two semiconductor chips 10 are mounted. The semiconductor chip 10 may be connected to the printed circuit board 8 and the wire 12 by bonding the connection pad 10a to the upper side, and the contact pad 10a may be in direct contact with the printed circuit board. It is also preferable to connect by flip chip bonding.
본 발명의 실시예로는 와이어(12) 본딩을 채용한 구조를 도시하였다. 상기 인쇄회로기판(8)은 열경화성 BT 수지(2)위에 구리박막(4)이 패턴되는바, 와이어 본드 패드부(4a)에는 솔더 마스크(6)를 도포하지 않으며, 이 와이어 본드 패드(4a)와 칩(10)의 상측에 형성된 접속패드(10a)간에 골드 또는 알루미늄 와이어(12)로 양 패드에 본딩하여 접속시킨다.In the embodiment of the present invention, a structure employing wire 12 bonding is illustrated. The printed circuit board 8 is a copper thin film 4 is patterned on the thermosetting BT resin (2), the solder mask 6 is not applied to the wire bond pad portion (4a), this wire bond pad (4a) And pads are bonded to both pads with gold or aluminum wires 12 between the pads 10a formed on the upper side of the chip 10.
상기 와이어(12) 본딩이 완료된 부재를 핸드링, 운반 등이 용이하도록 제품화하기 위하여 봉지수단(14)으로 외관을 형성해주어야 한다. 상기 몰딩 수단으로는 통상 EMC를 사용하는데, 상기 부재를 금형에 넣고 겔(gel)화된 EMC(Epoxy Molding Compound)를 주입하여 인쇄회로기판(8)의 상면과 배면을 몰딩한다.In order to manufacture the wire 12, the bonding is completed to facilitate the handing, transporting, etc. should be formed by the sealing means (14). EMC is generally used as the molding means, and the upper and rear surfaces of the printed circuit board 8 are molded by inserting the member into a mold and injecting a gelled epoxy molding compound (EMC).
상기 몰딩하기 전, 인쇄회로기판(8)의 배면에는 완성된 패키지를 마더 보드(도시 생략)등에 실장시켜 전기신호를 교환하기 위한 전도성 볼(16)이 부착되어야 하는바, 상기 전도성 볼(16)이 부착될 볼 패드(15)에는 몰딩이 되지 않도록 해야한다.Before the molding, the conductive ball 16 for mounting the finished package on a mother board (not shown) or the like to exchange an electrical signal should be attached to the rear surface of the printed circuit board 8, the conductive ball 16 The ball pad 15 to be attached should not be molded.
이를 위하여, 상기 몰딩 전 각 볼 패드 위치에는 핀을 부착시켜 몰딩 후 상기 핀을 분리하여 볼 패드(15)를 외부로 오픈시키도록 한다.To this end, a pin is attached to each ball pad position before the molding to separate the pin after molding to open the ball pad 15 to the outside.
도 3 은 상기 인쇄회로기판(8)의 배면 볼 패드에 몰딩전 핀(22)을 부착시키기 위한 핀 플레이트(20)를 도시한 사시도이다.3 is a perspective view showing a pin plate 20 for attaching the pin 22 before molding to the rear ball pad of the printed circuit board 8.
상기 도면의 핀 플레이트(20)는 별도로 제조하여 인쇄회로기판(8)의 배면에 부착시킨 후 금형내에 위치시킬 수 있으며, 바람직하게는 인쇄회로기판의 배면부 금형면에 부착시켜 몰딩공정시 계속해서 재사용이 가능하게 할 수도 있다.The pin plate 20 of the drawing may be manufactured separately and attached to the rear surface of the printed circuit board 8 and then placed in the mold. Preferably, the pin plate 20 is attached to the rear surface of the printed circuit board and subsequently reused during the molding process. This may be possible.
이와 같이 핀 플레이트(20)를 부착시킨 인쇄회로기판(8)을 금형내에서 EMC로 몰딩하면, 인쇄회로기판(8)의 상부 칩(10), 와이어(12) 등이 몰딩에 의해서 감싸지고 인쇄회로기판 배면 또한 소정높이로 몰딩이 형성된다.When the printed circuit board 8 having the pin plate 20 attached thereto is molded in the mold by EMC, the upper chip 10, the wire 12, and the like of the printed circuit board 8 are wrapped by the molding and printed. The back of the circuit board is also formed with a predetermined height.
이때 인쇄회로기판(8)의 배면에서 전도성 볼(16)이 부착되기 위한 볼 패드(15)에는 몰딩 사이사이에서 핀(22)이 삽입되어 있으므로 상기 핀 플레이트(20)를 분리해내면, 볼 패드(15)는 몰딩되지 않은 채 빈 공간부로 남게 된다.At this time, since the pins 22 are inserted between the moldings in the ball pads 15 to which the conductive balls 16 are attached on the back surface of the printed circuit board 8, the pin pads 20 are removed. 15 is left as an empty space part without being molded.
상기 몰딩되지 않은 볼 패드(15)에 전도성 볼(16)을 부착시킴으로써, 본 발명에 의한 멀티칩 모듈 패키지가 완성된다.By attaching the conductive balls 16 to the unmolded ball pads 15, the multichip module package according to the present invention is completed.
상기 인쇄회로기판(8)의 배면에 형성되는 몰딩부(14')의 높이는 전도성 볼(16)의 지름보다 낮게 형성되는 것을 특징으로 한다. 이는 몰딩부(14')의 높이가 볼(16)의 지름보다 크게 되면, 상술한 멀티칩 모듈 패키지를 마더보드에 실장할 경우 몰딩에 의해 전도성 볼(16)이 보드와 접촉되지 못하므로 접속이 불가능해지기 때문이다.The height of the molding part 14 ′ formed on the rear surface of the printed circuit board 8 is characterized in that it is formed lower than the diameter of the conductive ball 16. This is because when the height of the molding part 14 ′ is greater than the diameter of the ball 16, when the multi-chip module package described above is mounted on the motherboard, the conductive ball 16 does not come into contact with the board by molding. Because it becomes impossible.
이하 상술한 본 발명에 의한 멀티칩 모듈 패키지를 제조하는 방법을 개략적으로 설명하면,Hereinafter, a method of manufacturing a multichip module package according to the present invention as described above will be described.
인쇄회로기판(8)의 상면에 적어도 2개 이상의 반도체 칩(10)을 부착하고 상기 칩(10)과 인쇄회로기판(8)의 전기 신호 입출력단자 사이를 본딩접속하는 단계와;Attaching at least two semiconductor chips (10) to the upper surface of the printed circuit board (8) and bonding the chip (10) to the electrical signal input / output terminals of the printed circuit board (8);
상기 인쇄회로기판(8)의 배면에서 전도성 볼(16)이 부착되기 위한 볼 패드(15)에 임시부재(20)를 부착하는 단계와;Attaching a temporary member (20) to a ball pad (15) for attaching conductive balls (16) on the back of the printed circuit board (8);
상기 인쇄회로기판(8)의 상면과 배면을 금형내에서 봉지수단(14)(14')으로 몰딩하는 단계와;Molding the upper and rear surfaces of the printed circuit board (8) into sealing means (14) (14 ') in a mold;
상기 인쇄회로기판(8) 배면의 몰딩부(14')에서 상기 임시부재(20)를 제거하는 단계와;Removing the temporary member (20) from the molding portion (14 ') on the back of the printed circuit board (8);
상기 임시부재(20)가 제거된 볼 패드(15)에 전도성 볼(16)을 부착하는 단계;를 포함하여 이루어진다.Attaching the conductive ball 16 to the ball pad 15 from which the temporary member 20 is removed.
상기 임시부재로(20)는 핀(22) 혹은 핀 플레이트(20)을 사용함이 바람직하다.Preferably, the temporary member 20 uses a pin 22 or a pin plate 20.
상기 핀(22)을 볼 패드(15)에 부착하고 제거하기 위해서는 판상에 핀(22)이 구비되어 있는 핀 플레이트(20)를 채용함이 바람직하다.In order to attach and remove the pin 22 to the ball pad 15, it is preferable to employ a pin plate 20 having a pin 22 on the plate.
상기 인쇄회로기판(8)의 배면에 형성되는 몰딩부(14')의 높이는 부착될 전도성 볼(16)의 지름보다 낮게 형성한다.The height of the molding part 14 ′ formed on the rear surface of the printed circuit board 8 is lower than the diameter of the conductive ball 16 to be attached.
도 4에는 본 발명에 의한 멀티칩 모듈 패키지의 제조방법에 관한 제 2 실시예에 사용된 마스크(30)를 도시하였다.4 shows a mask 30 used in the second embodiment of the method for manufacturing a multichip module package according to the present invention.
상기 마스크(30)는 그 면적이 적어도 인쇄회로기판(8)의 면적보다 같거나 크고, 박판재이면서 면상에 다수의 홀(32)이 형성되어 있다. 상기 홀(32)의 형상은 원형이나 사각형 등이 채용되어도 무방하다.The mask 30 has an area at least equal to or larger than that of the printed circuit board 8, and is formed of a plurality of holes 32 on the surface of the mask 30. The shape of the hole 32 may be circular or rectangular.
상기 마스크(30)에 구비되어 있는 홀(32)의 직경은 대략 전도성 볼(16)의 지름과 유사하며 상기 마스크(30)를 인쇄회로기판(8)의 배면에 대응시켰을 때 상기 홀(32)의 위치는 인쇄회로기판(8)의 볼 패드(15) 위치와 동일하다.The diameter of the hole 32 provided in the mask 30 is approximately similar to the diameter of the conductive ball 16 and the hole 32 when the mask 30 corresponds to the rear surface of the printed circuit board 8. The position of is equal to the position of the ball pad 15 of the printed circuit board 8.
이하 상기 마스크(30)를 사용하여 본 발명에 의한 멀티칩 모듈 패키지를 제조하는 방법을 제조단계별로 설명한다.Hereinafter, a method of manufacturing a multichip module package according to the present invention using the mask 30 will be described for each manufacturing step.
인쇄회로기판(8)의 상면에 적어도 2개 이상의 반도체 칩(10)을 부착하고 상기 칩(10)과 인쇄회로기판(8)의 전기 신호 입출력단자 사이를 본딩접속하는 단계와;Attaching at least two semiconductor chips (10) to the upper surface of the printed circuit board (8) and bonding the chip (10) to the electrical signal input / output terminals of the printed circuit board (8);
상기 인쇄회로기판(8)의 상면과 배면을 금형내에서 봉지수단(14)(14')으로 몰딩하는 단계와;Molding the upper and rear surfaces of the printed circuit board (8) into sealing means (14) (14 ') in a mold;
상기 인쇄회로기판(8)의 배면 몰딩부(14')에 마스크(30)를 얼라인하여 부착하는 단계와;Aligning and attaching a mask (30) to the rear molding (14 ') of the printed circuit board (8);
상기 마스크(30)의 홀(32)과 대응하는 몰딩부를 식각하는 단계와;Etching the molding part corresponding to the hole 32 of the mask 30;
상기 식각되어 외부로 드러난 볼 패드에 전도성 볼(16)을 부착하는 단계;를포함하여 이루어진다.And attaching the conductive ball 16 to the etched ball pad exposed to the outside.
상기 마스크(30)의 홀(32)과 볼 패드(15) 위치는 서로 동일하게 형성한다.Positions of the holes 32 and the ball pads 15 of the mask 30 are the same.
상술한 멀티칩 모듈 패키지의 실시예와 제 2 실시예는 모두 제거용 임시부재(20)나 마스크(30) 등의 부가 수단을 이용하여 전도성 볼 패드(15)를 외부로 드러나게 하였으나, 천공수단을 사용하여 기계적으로 홀을 형성함으로써 보다 간단한 공정으로 완성할 수 있다.In the above-described embodiment and the second embodiment of the multichip module package, the conductive ball pad 15 is exposed to the outside by using additional means such as the removal temporary member 20 or the mask 30. It can be completed in a simpler process by forming holes mechanically.
이하 상기 천공수단을 이용한 본 발명의 멀티칩 모듈 패키지를 구현하는 방법을 제조단계별로 설명하면 다음과 같다.Hereinafter, a method for implementing the multichip module package of the present invention using the puncturing means will be described for each manufacturing step.
전술한 실시예들과 마찬가지로,Like the above-described embodiments,
인쇄회로기판(8)의 상면에 적어도 2개 이상의 반도체 칩을 부착하고 상기 칩(10)과 인쇄회로기판(8)의 전기 신호 입출력단자 사이를 본딩접속하는 단계와;Attaching at least two semiconductor chips to an upper surface of the printed circuit board (8) and bonding a connection between the chip (10) and the electrical signal input / output terminals of the printed circuit board (8);
상기 인쇄회로기판(8)의 상면과 배면을 금형내에서 봉지수단(14)(14')으로 몰딩하는 단계;를 진행한 후Molding the upper and rear surfaces of the printed circuit board 8 into the sealing means 14 and 14 ′ in the mold;
상기 인쇄회로기판(8)의 배면 몰딩부(14')에 천공수단으로 홀을 형성하여 볼 패드(15) 위치를 개방시키는 단계와;Opening holes in the ball pads (15) by forming holes in the back molding portion (14 ') of the printed circuit board (8) by means of punching means;
상기 개방된 볼 패드에 전도성 볼(16)을 부착하는 단계;를 포함하여 이루어진다.Attaching a conductive ball 16 to the open ball pad.
이때 천공수단으로는 통상의 드릴을 사용하거나 혹은 최근에 널리 사용되는 레이저를 채용함이 바람직하다.In this case, it is preferable to use a conventional drill or employ a laser widely used as a drilling means.
상기 실시예들은 모두 전도성 볼 사이로 봉지수단이 채워지도록 함에 따라그 공정이 다소 복잡하다. 이를 해결하기 위한 다른 실시예로서, 도 5와 같은 기판을 채용한 멀티칩 모듈 패키지를 제안한다.The above embodiments are all somewhat complicated as the encapsulation means are filled between conductive balls. As another embodiment for solving this problem, a multi-chip module package employing the substrate shown in FIG. 5 is proposed.
도 5 에 도시된 바와 같이, 기판(8)의 중앙측에는 다수의 칩(10)이 실장되고, 기판의 외곽 내지 내부에는 통공부(40)가 형성되는바, 그 일례로 슬릿(40)이 구비되어 있다. 상기 기판(8)의 상면을 몰딩할 시 봉지수단이 외곽의 슬릿(40)을 포함하여 봉지되고, 슬릿을 통과하여 기판의 외곽 배면측에 라인상으로 돌출된 몰딩부(14')를 형성하도록 한다.As shown in FIG. 5, a plurality of chips 10 are mounted on a central side of the substrate 8, and through-holes 40 are formed outside or inside the substrate, for example, the slits 40 are provided. It is. When molding the upper surface of the substrate 8, the sealing means is encapsulated including the outer slit 40, and passes through the slit to form a molding portion 14 'protruding in a line on the outer back side of the substrate. do.
도 6 에 상기 도 5의 인쇄회로기판(8)을 봉지수단(14)(14')으로 봉지한 후의 멀티칩 모듈 패키지의 일례를 도시하였다. 도 6을 참조하면, 기판의 상면에는 반도체 칩과 와이어를 감싸면서 봉지수단으로 몰딩되고, 기판의 배면 외곽 또는 적소에 슬릿을 통과한 몰딩부가 라인상으로 형성됨으로써, 상면 몰딩부의 열팽창 계수를 일부 보상하여 워피지를 방지하는 효과를 발생한다.6 shows an example of a multichip module package after encapsulating the printed circuit board 8 of FIG. 5 with the sealing means 14 and 14 '. Referring to FIG. 6, the upper surface of the substrate is molded with encapsulation means while surrounding the semiconductor chip and wire, and a molding part passing through the slit is formed in a line shape on the outside or in place of the back surface of the substrate to partially compensate for the thermal expansion coefficient of the upper molding part. To prevent warpage.
상술한 실시예들의 방법으로 멀티칩 모듈 패키지를 구성하면, 인쇄회로기판의 상면과 배면 모두 동일한 공정에서 몰딩이 행해지므로 인쇄회로기판의 상면과 하면 열팽창 계수의 차이로 인한 워피지(warpage: 휨 현상)가 발생되지 않아 제품 신뢰성이 향상된다.When the multi-chip module package is constructed by the method of the above-described embodiments, the molding is performed in the same process on both the top and bottom of the printed circuit board. ), The product reliability is improved.
인쇄회로기판의 반도체 칩과 리드선을 보호하기 위해 상면에만 몰딩하지 않고 인쇄회로기판의 배면을 동시에 몰딩함으로써, 인쇄회로기판의 상하면에 열적 평형이 이루어져 열팽창계수로 인한 워피지 현상을 제거하고 보다 안정적인 멀티칩모듈 패키지를 제조할 수 있다.In order to protect the semiconductor chip and the lead wire of the printed circuit board, by simultaneously molding the back surface of the printed circuit board instead of molding only on the upper surface, thermal equilibrium is formed on the upper and lower surfaces of the printed circuit board to eliminate warpage phenomenon due to the coefficient of thermal expansion and more stable multi Chip module packages can be manufactured.
Claims (8)
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| CN106920779A (en) * | 2017-03-09 | 2017-07-04 | 三星半导体(中国)研究开发有限公司 | The combining structure of flexible semiconductor packaging part and its transportation resources |
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