KR100386634B1 - Methode to form moisture discharge hole for BGA package substrate - Google Patents
Methode to form moisture discharge hole for BGA package substrate Download PDFInfo
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- KR100386634B1 KR100386634B1 KR10-2000-0085924A KR20000085924A KR100386634B1 KR 100386634 B1 KR100386634 B1 KR 100386634B1 KR 20000085924 A KR20000085924 A KR 20000085924A KR 100386634 B1 KR100386634 B1 KR 100386634B1
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- circuit board
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- discharge hole
- moisture discharge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 칩을 인쇄회로기판에 부착할 때 습기 배출공을 미리 형성하지 않거나 혹은 형성된 습기 배출공을 차단시킨 상태에서 부착하고, 칩이 인쇄회로기판에 부착된 후 습기 배출공을 개방시키는 방법을 채용하여 보다 공정이 단순해지고 제품 신뢰성을 확보할 수 있는 비지에이 패키지용 기판의 습기 배출공 형성방법을 천공하는 것을 그 목적으로 한다.The present invention is a method for attaching the semiconductor chip to the printed circuit board in a state in which the moisture discharge hole is not formed in advance or the formed moisture discharge hole is blocked, and the chip is attached to the printed circuit board to open the moisture discharge hole. The purpose of the present invention is to drill a method for forming a moisture discharge hole of a substrate for a BG package that can simplify the process and ensure product reliability.
상기 목적을 달성하기 위하여 본 발명의 비지에이 패키지용 기판의 습기 배출공 형성방법은,In order to achieve the above object, the method for forming a moisture discharge hole of a substrate for a BG package of the present invention,
인쇄회로기판(8)에 습기 배출용 홀(18)을 형성하는 단계와,Forming a moisture discharge hole 18 in the printed circuit board 8;
상기 홀(18)을 인쇄회로기판(8)의 배면에서 차단부재(20)로 차단하는 단계와,Blocking the hole 18 with the blocking member 20 at the rear of the printed circuit board 8;
상기 인쇄회로기판(8)에 칩(10)을 부착하고 와이어(12) 본딩 후 봉지재(14)로 몰딩하는 단계와,Attaching the chip 10 to the printed circuit board 8 and molding the encapsulant 14 after bonding the wire 12;
상기 차단부재(20)를 제거하는 단계를 포함한다.Removing the blocking member 20.
Description
본 발명은 반도체 패키지에 관한 것으로서 보다 상세하게는 볼 그리드 어레이(BGA:Ball Grid Array) 반도체 패키지에서 칩이 어태치(attach)되는 기판의 습기 배출공 형성방법에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a method of forming a moisture discharge hole of a substrate to which a chip is attached in a ball grid array (BGA) semiconductor package.
일반적으로 볼 그리드 어레이 반도체 패키지(Ball Grid Array semi-conductor Package: 이하 BGA 패키지라 함)란 반도체 칩에서 마더 보드(mother board)로의 입출력 수단이 저면에 2차원적으로 배열된 솔더 볼로 이루어진 것을 말한다.In general, a ball grid array semi-conductor package (hereinafter referred to as a BGA package) refers to a solder ball having two-dimensionally arranged input / output means from a semiconductor chip to a mother board.
이러한 BGA 패키지는 종래의 반도체 패키지 이를테면 DIP(Dual Inline Package), QFP(Quad Flat Package)등 보다 그 부피가 소형이면서도 더 많은 입출력 단자수를 가질수 있는 형태이기 때문에 최근의 초소형 전자제품 및 이동 통신 기기 등에 다양하게 수요를 창출하고 있는 실정이다.Such a BGA package is smaller in size than a conventional semiconductor package such as a dual inline package (DIP) or a quad flat package (QFP), and can have a larger number of input / output terminals. It is creating a variety of demand.
도 1 에는 종래 BGA 패키지의 개략적인 단면도를 도시하였다.1 is a schematic cross-sectional view of a conventional BGA package.
도면을 참조하면, 종래 BGA 패키지는 크게 인쇄회로기판(8), 반도체 칩(10), 솔더볼(16) 등으로 개략적으로 나눌 수 있다. 상기 인쇄회로기판(8)의 표면에는 구리 또는 니켈 합금등으로 형성된 전도성 박막(4)이 패턴형성되고, 상기 전도성 박막(4) 위로 비전도성인 솔더마스크(6)가 부분적으로 도포된다.Referring to the drawings, a conventional BGA package may be roughly divided into a printed circuit board 8, a semiconductor chip 10, a solder ball 16, and the like. A conductive thin film 4 formed of copper or nickel alloy is patterned on the surface of the printed circuit board 8, and a non-conductive solder mask 6 is partially coated on the conductive thin film 4.
상기 솔더마스크(6)가 도포되지 않고 개방된 부분은 반도체 칩(10)과 인쇄회로기판(8)을 전기적으로 접속하기 위한 와이어 본딩 패드(4a)가 된다. 상기 인쇄회로기판(8)의 중앙에는 반도체 칩(10)이 부착되는바, 접착성 페이스트(9), 통상 에폭시등으로 접착하고, 칩(10)의 상단에 형성된 접속패드(10a)와 인쇄회로기판(8)의 와이어 본드 패드(4a)간에 전도성 와이어(12)를 본딩하여 전기접속시킨다.The open portion without the solder mask 6 applied becomes a wire bonding pad 4a for electrically connecting the semiconductor chip 10 and the printed circuit board 8. The semiconductor chip 10 is attached to the center of the printed circuit board 8. The adhesive paste 9 is usually adhered with an epoxy or the like, and the connection pad 10a and the printed circuit formed on the top of the chip 10 are provided. The conductive wire 12 is bonded and electrically connected between the wire bond pads 4a of the substrate 8.
상술한 바와 같이 구성된 인쇄회로기판(8)의 상면을 금형내에서 봉지재(14), 즉 몰드 콤파운드(mold compound)로 몰딩하는바, 이는 반도체 패키지의 보관, 운반 등의 편리성과 와이어(12)로 본딩된 반도체 칩(10)을 보호하기 위해 상기 몰딩공정을 진행한다.The upper surface of the printed circuit board 8 configured as described above is molded in the mold with an encapsulant 14, that is, a mold compound, which is convenient for the storage, transportation, etc. of the semiconductor package and the wire 12. In order to protect the semiconductor chip 10 bonded to the molding process is carried out.
이 후 상면이 몰딩된 인쇄회로기판(8)의 배면에 형성된 솔더 볼 패드(15)에 솔더볼(16)을 부착함으로써 BGA 패키지가 완성된다. 상기 인쇄회로기판(8)의 내부에는 전도성 비아홀(8a)이 형성되어 있어 솔더 볼(16)과 칩(10) 간의 입출력 전기신호를 교환시키는 역할을 한다.Thereafter, the BGA package is completed by attaching the solder balls 16 to the solder ball pads 15 formed on the rear surface of the printed circuit board 8 having the upper surface molded thereon. A conductive via hole 8a is formed in the printed circuit board 8 to exchange input and output electrical signals between the solder ball 16 and the chip 10.
도 2 는 상기 인쇄회로기판(8)과 반도체 칩(10)을 분리하여 도시한 분리 사시도이다.2 is an exploded perspective view illustrating the printed circuit board 8 and the semiconductor chip 10 separately.
도면을 참조하면, 인쇄회로기판(8)의 중앙부, 즉 칩(10)이 부착되는 위치에는 다수개의 홀(18)이 형성되어 있다. 상기 홀(18)은 칩(10)이 인쇄회로기판(8)에 부착된 후 침투하는 습기를 배출시키는 습기 배출공이다. 만일 상기 습기 배출공(18)이 없다면, 상기 BGA 패키지를 마더 보드(도시 생략함)에 실장할 때 고온의 실장 온도로 인해 흡습되어 있던 수분이 기화되고 이어서 반도체 칩(10)과 봉지재(14), 혹은 칩(10)과 접착성 페이스트(9) 및 인쇄회로기판(8)의 가장 약하게 결합된 부분에서부터 계면박리현상이 발생되고 기화되는 압력으로 인해 패키지 부피가 팽창된다.Referring to the drawings, a plurality of holes 18 are formed in the center portion of the printed circuit board 8, that is, the position where the chip 10 is attached. The hole 18 is a moisture discharge hole for discharging moisture that penetrates after the chip 10 is attached to the printed circuit board 8. If the moisture discharge hole 18 is not present, the moisture absorbed by the high temperature at the time of mounting the BGA package on the motherboard (not shown) is vaporized, and then the semiconductor chip 10 and the encapsulant 14 ), Or the package volume is expanded due to the pressure evaporating from the weakest bonding portion of the chip 10 and the adhesive paste 9 and the printed circuit board 8.
이러한 상태가 지속되면, 가장 약하게 결합된 부분부터 균열이 발생되어 크랙(crack) 또는 본딩 손실(bonding damage)이 야기되는 것이다.If this condition persists, cracking occurs from the weakest bonded portion, causing cracking or bonding damage.
상술한 바와 같은 이유로 인해, 인쇄회로기판(8)상에 습기 배출공이 구비되어야 함은 당연하나, 도면에서 보는 바와 같이, 칩(10)을 부착할 때 접착성 페이스트(9)를 칩(10)의 중앙 전면에 도포하지 못하고, 습기 배출공(18)을 피해서 도포해야 하므로 공정상 어려움이 많고 그 접착력 또한 떨어지게 된다.For the reason as described above, it is natural that the moisture discharge hole should be provided on the printed circuit board 8, but as shown in the drawing, the adhesive paste 9 is applied to the chip 10 when the chip 10 is attached. Can not be applied to the front of the center of the moisture, so the moisture discharge hole 18 should be applied to avoid a lot of difficulties in the process and its adhesion is also reduced.
또한, 상기 습기 배출공(18) 위로는 접착성 페이스트(9)가 도포되지 않아 물리적으로 충진되어 있지 않으므로 이격된 공간으로 인한 칩(10)의 스트레스로 칩(10)에 크랙이 발생할 수 있으며, 습기 배출공(18)을 통해 이물질이 함입될 수도 있고, 접착성 페이스트(9)로 에폭시를 사용할 경우 상기 공간부로 인해 열발산 효과가 저하되는 문제점도 있다.In addition, since the adhesive paste 9 is not applied to the moisture discharge hole 18 and thus is not physically filled, cracks may occur in the chip 10 due to stress of the chip 10 due to the spaced apart. Foreign matter may be embedded through the moisture discharge hole 18, or when the epoxy is used as the adhesive paste 9, the heat dissipation effect may be reduced due to the space.
본 발명은 상술한 종래 기술의 문제점을 해결하고자 안출된 발명으로서, 반도체 칩을 인쇄회로기판에 부착하기 전에, 상기 인쇄회로기판상에 습기 배출공을 미리 형성하고 형성된 습기 배출공을 차단하는 차단부재를 설치하여, 칩이 인쇄회로기판에 부착된 후 차단부재를 분리시켜 습기 배출공을 개방시키는 방법을 채용하므로써 공정이 단순해지고 제품 신뢰성을 확보할 수 있는 비지에이 패키지용 기판의 습기 배출공 형성방법을 천공하는 것을 그 목적으로 한다.The present invention has been made to solve the above-described problems of the prior art, and before the semiconductor chip is attached to the printed circuit board, the blocking member for forming a moisture discharge hole in advance on the printed circuit board and blocking the formed moisture discharge hole Method of forming a moisture discharge hole in a BG package board that can simplify the process and secure product reliability by adopting a method in which a chip is attached to a printed circuit board to remove the blocking member and open the moisture discharge hole. Its purpose is to puncture.
도 1 은 종래 BGA 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional BGA package.
도 2 는 종래 BGA 패키지에서 인쇄회로기판과 반도체 칩을 분리도시한 분리사시도.Figure 2 is an exploded perspective view showing the separation of the printed circuit board and the semiconductor chip in the conventional BGA package.
도 3 은 본 발명의 비지에이 패키지용 기판의 습기배출공 형성방법에 의한 차단부재가 부착된 BGA 패키지를 도시한 단면도.3 is a cross-sectional view showing a BGA package with a blocking member by a method for forming a moisture discharge hole of a substrate for a package of the present invention.
도 4 는 도 3 의 차단부재를 도시한 사시도.4 is a perspective view of the blocking member of FIG.
도 5 는 본 발명의 비지에이 패키지용 기판의 습기배출공 형성방법의 다른 실시예를 도시한 단면도.5 is a cross-sectional view showing another embodiment of the method for forming a moisture discharge hole of a substrate for a package of the present invention.
** 도면의 주요 부분에 대한 부호의 설명 **** Description of symbols for the main parts of the drawing **
8: 인쇄회로기판 10: 칩8: printed circuit board 10: chip
12: 와이어 14: 봉지재12: wire 14: encapsulant
16: 솔더볼 20: 차단부재, 핀 플레이트16: solder ball 20: blocking member, pin plate
22: 핀 30: 천공수단22: pin 30: drilling means
32: 드릴32: drill
상기 목적을 달성하기 위하여 본 발명의 비지에이 패키지용 기판의 습기 배출공 형성방법은,In order to achieve the above object, the method for forming a moisture discharge hole of a substrate for a BG package of the present invention,
인쇄회로기판(8)에 습기 배출용 홀(18)을 형성하는 단계와,Forming a moisture discharge hole 18 in the printed circuit board 8;
상기 홀(18)을 인쇄회로기판(8)의 배면에서 차단부재(20)로 차단하는 단계와,Blocking the hole 18 with the blocking member 20 at the rear of the printed circuit board 8;
상기 인쇄회로기판(8)에 칩(10)을 부착하고 와이어(12) 본딩 후 봉지재(14)로 몰딩하는 단계와,Attaching the chip 10 to the printed circuit board 8 and molding the encapsulant 14 after bonding the wire 12;
상기 차단부재(20)를 제거하는 단계를 포함한다.Removing the blocking member 20.
상기 차단부재(20)는 표면에 핀이 형성된 핀 플레이트인 것을 특징으로 한다.The blocking member 20 is characterized in that the pin plate is formed on the surface.
본 발명의 구성에 대하여 첨부한 도면을 참조하면서 보다 상세하게 설명한다. 참고로 본 발명을 설명하기에 앞서, 설명의 중복을 피하기 위하여 종래 기술과일치하는 부분에 대해서는 종래 도면 부호를 그대로 인용하기로 한다.The structure of this invention is demonstrated in detail, referring an accompanying drawing. For reference, prior to describing the present invention, in order to avoid duplication of description of the prior art reference to the same reference numerals will be referred to.
도 3 은 본 발명에 의한 비지에이 패키지용 기판(8)의 습기배출공 형성방법으로 제조되는 BGA 패키지의 일단면을 도시한 단면도이고, 도 4 는 상기 방법에 채용된 핀 플레이트를 도시한 사시도이다.3 is a cross-sectional view showing one end surface of a BGA package manufactured by a method for forming a moisture discharge hole of a substrate 8 for a package for packaging according to the present invention, and FIG. 4 is a perspective view showing a pin plate employed in the method. .
먼저 도 3을 참조하면, 상기 BGA 패키지의 구성은 인쇄회로기판(8)의 상면에 반도체 칩(10)이 부착되어 있으며, 상기 반도체 칩(10)은 인쇄회로기판(8)과의 전기신호를 교환하는 접속매개물로서, 전도성 와이어(12)를 채용하고 있다.First, referring to FIG. 3, in the configuration of the BGA package, a semiconductor chip 10 is attached to an upper surface of a printed circuit board 8, and the semiconductor chip 10 transmits an electrical signal to the printed circuit board 8. As the connection medium to be replaced, the conductive wire 12 is employed.
상기 인쇄회로기판(8)은 통상의 BT 수지(2)위에 구리 또는 니켈 합금으로 이루어져 통전회로를 구성하는 전도성 박막(4)이 패턴 형성되고 상기 전도성 박막(4)위로 비전도성 물질인 솔더 마스크(6)가 도포되어 이루어진다. 상기 전도성 박막(4)의 일부에는 솔더 마스크(6)가 도포되지 않고 개방되는바, 상기 개방된 부분이 와이어 본드 패드(4a)로서, 반도체 칩(10)의 상측에 구비된 접속패드(10a)와 와이어(12)에 의해 전기접속된다.The printed circuit board 8 is formed of a copper or nickel alloy on a conventional BT resin 2 to form a conductive thin film 4 constituting a current-carrying circuit, and a solder mask of a non-conductive material on the conductive thin film 4. 6) is applied. A part of the conductive thin film 4 is opened without a solder mask 6 applied thereto. The open part is a wire bond pad 4a, and a connection pad 10a provided on the semiconductor chip 10 is provided. And wire 12 are electrically connected.
상기 인쇄회로기판(8)의 상면에 부착된 반도체 칩(10)과 와이어(12)는, 보관 및 운반등의 용이성과 칩(10) 자체를 보호하기 위한 봉지재(14)로 몰딩되고, 상기 인쇄회로기판(8)의 배면 소정부에는 솔더볼(16)이 부착되어 있다. 상기 인쇄회로기판(8)에서 칩(10)이 부착되는 부분에는 복수의 홀(18)이 형성되어 있는바, 상기 홀(18)은 차단부재(20)에 의해 차단되어 있다.The semiconductor chip 10 and the wire 12 attached to the upper surface of the printed circuit board 8 are molded with an encapsulant 14 for protecting the chip 10 itself and for ease of storage and transportation. The solder ball 16 is attached to the predetermined rear surface of the printed circuit board 8. A plurality of holes 18 are formed in a portion of the printed circuit board 8 to which the chip 10 is attached, and the holes 18 are blocked by the blocking member 20.
이하 상기 차단부재(20)를 사용하여 비지에이 패키지용 기판(8)의 습기 배출공(18)을 형성하는 방법을 좀더 자세히 설명하면 다음과 같다.Hereinafter, a method of forming the moisture discharge hole 18 of the substrate 8 for the BGA package using the blocking member 20 will be described in more detail.
인쇄회로기판(8)에는 종래와 마찬가지로 그 상면을 봉지재(14)로 몰딩하기 전에 습기배출용 홀(18)이 형성되어 있다. 종래에는 상기 홀(18)을 그대로 유지한 채 그 주변으로 접착성 페이스트(9)를 도포하고 칩(10)을 부착하였으나, 본 발명에서는 상기 칩(10)을 부착하기 전에 상기 인쇄회로기판(8)의 홀을 차단부재(20)로 메운다음 접착성 페이스트(9)를 도포하고 칩(10)을 부착하도록 되어 있다.The printed circuit board 8 is formed with a moisture releasing hole 18 before molding the upper surface thereof with the encapsulant 14 as in the prior art. Conventionally, the adhesive paste 9 was applied to the periphery of the printed circuit board 8 while the hole 18 was maintained as it was, and in the present invention, the chip 10 was attached. Hole is filled with the blocking member 20, and then the adhesive paste 9 is applied and the chip 10 is attached.
도 3 에 도시된 차단부재(20)를 참조하여 설명하면, 상기 차단부재(20)는 대략 사각형의 박판에 돌출된 핀(22)이 구비되어 있는 부재로서, 상기 핀(22)의 직경은 인쇄회로기판(8)의 습기 배출용 홀(18)의 직경과 거의 일치하여 핀(22)이 상기 홀(18)에 삽입되데 홀벽과 핀의 외벽간에 공간이 거의 형성되지 않을 정도이며, 상기 핀(22)과 핀(22)간의 간격은 인쇄회로기판(8)에서 습기배출용 홀(18)과 홀(18)간의 간격과 일치한다. 또한, 상기 핀(22)의 높이는 습기배출용 홀(18)의 높이, 즉 인쇄회로기판(8)의 두께와 동일하게 형성된다.Referring to the blocking member 20 illustrated in FIG. 3, the blocking member 20 is a member having a pin 22 protruding from a substantially rectangular thin plate, and the diameter of the pin 22 is printed. The pin 22 is inserted into the hole 18 so as to substantially match the diameter of the moisture discharging hole 18 of the circuit board 8, so that little space is formed between the hole wall and the outer wall of the pin. The spacing between the pins 22 and 22 coincides with the spacing between the moisture dissipation holes 18 and the holes 18 in the printed circuit board 8. In addition, the height of the pin 22 is formed to be equal to the height of the moisture discharge hole 18, that is, the thickness of the printed circuit board (8).
이와 같은 차단부재(20:이하 핀 플레이트), 즉 핀(22)이 구비된 핀 플레이트(20)를 인쇄회로기판(8)의 배면에서 상측으로 삽입시킨 뒤 칩(10)을 부착하기 위한 접착성 페이스트(9)를 도포하게 된다.An adhesive for attaching the chip 10 after inserting the blocking member 20 (hereinafter referred to as a pin plate), that is, the pin plate 20 provided with the pins 22 on the back side of the printed circuit board 8. The paste 9 is applied.
상기 핀 플레이트(20)가 인쇄회로기판(8)의 습기배출용 홀(18)을 메우게 되면, 인쇄회로기판(8)의 상면은 홀(18)이 형성되기 이전과 같이 평탄해지고 상기 평탄해진 인쇄회로기판(8)의 중앙부에 전체적으로 접착성 페이스트(9)를 도포하고 칩(10)을 부착하게 된다.When the pin plate 20 fills the moisture discharge hole 18 of the printed circuit board 8, the upper surface of the printed circuit board 8 is flattened and flattened as before the hole 18 is formed. The adhesive paste 9 is applied to the entire center of the printed circuit board 8 and the chips 10 are attached.
상기와 같이 칩(10)이 부착된 후 와이어(12)로 칩(10)과 인쇄회로기판(8)을본딩접속시키고, 그 위를 봉지재(14)로 몰딩하게 된다. 상기 몰딩후 봉지수지가 경화되면, 상기 핀 플레이트(20)를 인쇄회로기판(8)에서 분리해낸다. 상기 과정에 의해 BGA 패키지용 기판(8)의 습기배출공(18)을 형성한다.After the chip 10 is attached as described above, the chip 10 and the printed circuit board 8 are bonded to each other by the wire 12, and then, the chip 10 is molded with the encapsulant 14. When the encapsulation resin is cured after molding, the pin plate 20 is separated from the printed circuit board 8. The moisture discharge hole 18 of the substrate 8 for BGA package is formed by the above process.
상술한 과정을 요약하면, 본 발명에 의한 비지에이 패키지용 기판(8)의 습기배출공 형성방법은,Summarizing the above-described process, the method for forming a moisture discharge hole of the substrate 8 for the BGA package according to the present invention,
인쇄회로기판(8)에 습기 배출용 홀(18)을 형성하는 단계와,Forming a moisture discharge hole 18 in the printed circuit board 8;
상기 홀을 인쇄회로기판(8)의 배면에서 차단부재(20)로 차단하는 단계와,Blocking the hole with the blocking member 20 at the rear of the printed circuit board 8;
상기 인쇄회로기판(8)에 칩(10)을 부착하고 와이어 본딩 후 봉지재(14)로 몰딩하는 단계와,Attaching the chip 10 to the printed circuit board 8 and molding the encapsulant 14 after wire bonding;
상기 차단부재(20)를 제거하는 단계를 포함한다.Removing the blocking member 20.
상기 차단부재(20)는 핀(22)이 구비된 핀 플레이트(20)인 것이 바람직하다.The blocking member 20 is preferably a pin plate 20 having a pin 22.
상술한 본 발명의 방법에 의해 습기배출공(18)을 형성하면, 칩(10) 부착부위 전면에 접착성 페이스트를 도포하므로 칩(10)의 접착력이 강화되고, 차단부재에 의해 홀이 메워져 있으므로 홀 안으로 접착성 페이스트(9)가 유출될 염려가 없으며, 칩(10) 하면에 페이스트가 골고루 충진되어 물리적으로 안정되므로 칩(10)에 가해지는 스트레스가 현저히 줄어들게 된다.When the moisture discharge hole 18 is formed by the method of the present invention described above, since the adhesive paste is applied to the entire surface of the chip 10 attachment portion, the adhesive force of the chip 10 is strengthened, and the hole is filled by the blocking member. There is no fear that the adhesive paste 9 will leak into the hole, and since the paste is uniformly filled on the lower surface of the chip 10 and physically stabilized, the stress applied to the chip 10 is significantly reduced.
또한, 열발산효과가 뛰어나고, 이물질이 침투될 가능성을 배제할 수 있다.In addition, the heat dissipation effect is excellent, and it is possible to exclude the possibility of the foreign matter penetrating.
칩(10)이 부착되는 하면에 접착성 페이스트가 골고루 충진되므로 공정이 단순해지고, 접착력이 강화되며, 칩(10)과 기판(8)사이에 공간이 없으므로 이물질이 칩(10)이 구조적으로 안정되어 스트레스가 줄어들고, 이물질이 침투될 수 없고 열발산 효율이 증대된다.Since the adhesive paste is evenly filled on the lower surface to which the chip 10 is attached, the process is simplified, adhesion is enhanced, and since there is no space between the chip 10 and the substrate 8, foreign matter is structurally stable. This reduces stress, prevents foreign matter from penetrating and increases heat dissipation efficiency.
접착성 페이스트 도포시 홀내부로 페이스트가 흘러들어갈 염려가 없으므로 작업이 용이해지며, 결과적으로 제품신뢰성이 향상된다.When the adhesive paste is applied, there is no fear that the paste will flow into the hole, thereby facilitating the work, and consequently, the product reliability is improved.
Claims (4)
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| KR10-2000-0085924A KR100386634B1 (en) | 2000-12-29 | 2000-12-29 | Methode to form moisture discharge hole for BGA package substrate |
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| JPH09172103A (en) * | 1995-12-21 | 1997-06-30 | Toshiba Corp | Manufacturing for semiconductor device and glass epoxy substrate |
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| JP2000114414A (en) * | 1998-09-30 | 2000-04-21 | Hitachi Chem Co Ltd | Semiconductor package and manufacture of it |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5721450A (en) * | 1995-06-12 | 1998-02-24 | Motorola, Inc. | Moisture relief for chip carriers |
| KR0170024B1 (en) * | 1995-10-27 | 1999-02-01 | 황인길 | Ball grid array semiconductor package having moisture radiating property |
| JPH09172103A (en) * | 1995-12-21 | 1997-06-30 | Toshiba Corp | Manufacturing for semiconductor device and glass epoxy substrate |
| US6054755A (en) * | 1997-10-14 | 2000-04-25 | Sumitomo Metal (Smi) Electronics Devices Inc. | Semiconductor package with improved moisture vapor relief function and method of fabricating the same |
| US6014318A (en) * | 1997-10-27 | 2000-01-11 | Nec Corporation | Resin-sealed type ball grid array IC package and manufacturing method thereof |
| JP2000082760A (en) * | 1998-06-25 | 2000-03-21 | Citizen Watch Co Ltd | Semiconductor device |
| JP2000114414A (en) * | 1998-09-30 | 2000-04-21 | Hitachi Chem Co Ltd | Semiconductor package and manufacture of it |
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