KR100381840B1 - Method for manufacturing lead frame having solder ball thermally attached to backside of semiconductor package - Google Patents
Method for manufacturing lead frame having solder ball thermally attached to backside of semiconductor package Download PDFInfo
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- KR100381840B1 KR100381840B1 KR1019960058754A KR19960058754A KR100381840B1 KR 100381840 B1 KR100381840 B1 KR 100381840B1 KR 1019960058754 A KR1019960058754 A KR 1019960058754A KR 19960058754 A KR19960058754 A KR 19960058754A KR 100381840 B1 KR100381840 B1 KR 100381840B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
본 발명은 반도체 패키지의 저면으로 솔더볼이 융착된 리드프레임 제조방법에 관한 것으로서, 더욱 상세하게는 반도체 패키지의 입출력 단자를 솔더볼을 이용하여 패키지의 저면에 다수의 열과 행을 가지면서 배열되도록 융착함으로서 다핀화를 실현하여 패키지의 성능을 향상시키고, 패키지를 경박단소화 하여 고집적화 및 고성능화 할 수 있도록 된 것이다.The present invention relates to a method of manufacturing a lead frame in which solder balls are fused to the bottom of a semiconductor package. More particularly, the present invention relates to soldering an input / output terminal of a semiconductor package by soldering the solder ball to a bottom surface of the package with a plurality of rows and rows. By realizing pinning, the package performance can be improved, and the package can be made lighter and thinner to achieve high integration and high performance.
일반적으로 반도체패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스밀봉 패키지, 금속밀봉 패키지 등이 있다. 이와같은 반도체패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology, SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로서 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic Leaded Chip Carrier), BGA(Ball Grid Array) 등이 있다.In general, semiconductor packages may include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into an insert type and a surface mount technology (SMT) type according to the mounting method. Representative examples of the insert type include a dual in-line package (DIP) and a pin grid array (PGA). Typical examples of the mounting type include a quad flat package (QFP), a plastic leaded chip carrier (PLC), a ceramic leaded chip carrier (CLCC), and a ball grid array (BGA).
최근에는 전자제품의 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해서 삽입형 반도체패키지 보다는 표면실장형 반도체패키지가 널리 사용되고 있는데, 이러한 종래의 패키지에 대한 구조를 도 1과 도 2를 참조하여 QFP와, BGA패키지에 대하여 설명하면 다음과 같다.Recently, in order to increase the mounting degree of components of a printed circuit board according to the miniaturization of electronic products, surface mount type semiconductor packages are widely used rather than insert type semiconductor packages. The structure of such a conventional package is described with reference to FIGS. 1 and 2. The following describes the BGA package.
도 1은 종래의 일반적인 반도체 패키지의 QFP로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(11)과, 상기 반도체칩(11)이 에폭시(16)에 의해 부착되는 탑재판(15)과, 상기 반도체칩(11)의 신호를 외부로 전달할 수 있는 다수의 리드(12)와, 상기 반도체칩(11)과 리드(12)를 연결시켜 주는 와이어(13)와, 상기 반도체칩(11)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지부(14)로 이루어지는 것이다.1 is a QFP of a conventional general semiconductor package, the structure of which is a semiconductor chip 11 in which an electronic circuit is integrated, a mounting plate 15 to which the semiconductor chip 11 is attached by an epoxy 16, and A plurality of leads 12 capable of transmitting signals of the semiconductor chip 11 to the outside, wires 13 connecting the semiconductor chips 11 and the leads 12, the semiconductor chips 11, In order to protect other peripheral components from external oxidation and corrosion, it is made of an encapsulation portion 14 wrapped around the outside thereof.
그러나, 상기의 QFP는 반도체칩이 점차적으로 고성능화되어 가면서 핀의 수가 더욱 더 많아지게 되는데 비하여, 핀과 핀 사이의 거리를 일정치 이하로 좁히는 것은 기술적으로 어려움이 있기 때문에 많은 핀을 모두 수용하기 위해서는 패키지가 커지게 되는 단점이 있다. 이것은 반도체패키지의 소형화 추세에 역행하는 결과를 낳는 문제점이 있는 것이다.However, the above QFP has a higher number of pins as the semiconductor chip is gradually improved in performance. However, it is technically difficult to narrow the distance between the pins to a certain value or less. The disadvantage is that the package becomes large. This is a problem that results in the contrary to the trend of miniaturization of semiconductor packages.
이와같이 다핀화에 따른 기술적 요구를 해결하기 위해서 등장한 것이 BGA패키지로서, 이는 입출력 수단으로서 반도체패키지의 일면전체에 융착된 솔더볼을 이용함으로써 QFP 보다 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 QFP 보다 작게 형성된 것이다.The BGA package, which emerged to solve the technical demands of the multi-pinning method, can accept a larger number of input / output signals than the QFP by using solder balls fused to the entire surface of the semiconductor package as an input / output means. Is smaller than QFP.
이러한 BGA패키지의 구성은 도 2에 도시된 바와같이 표면에 회로패턴(25a)이 형성되고, 이 회로패턴(25a)을 보호하기 위해 솔더마스크(25b)가 코팅된 회로기판(25)과, 상기 회로기판(25)의 상면 중앙에 부착된 반도체칩(21)과, 상기 반도체칩(21)과 상기 회로기판(25)의 회로패턴(25a)을 전기적으로 연결하여 신호를 전달하는 와이어(23)와, 상기 회로기판(25)의 회로패턴(25a)에 융착되어 외부로 신호를 전달하는 솔더볼(22)과, 상기 반도체칩(21)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지부(24)로 구성되는 것이다.As shown in FIG. 2, the BGA package includes a circuit board 25 having a circuit pattern 25a formed thereon, and a solder mask 25b coated thereon to protect the circuit pattern 25a. The semiconductor chip 21 attached to the center of the upper surface of the circuit board 25 and the wire 23 for electrically connecting the semiconductor chip 21 and the circuit pattern 25a of the circuit board 25 to transmit a signal. And solder balls 22 fused to the circuit patterns 25a of the circuit board 25 to transmit signals to the outside, and to protect the semiconductor chip 21 and other peripheral components from external oxidation and corrosion. It is composed of an encapsulation portion 24 wrapped around the outside.
그러나, 이러한 BGA패키지는 내부에 내장된 반도체칩의 크기에 비해서 패키지의 크기가 몇 배 이상 크기 때문에 전자제품들을 소형화시키기에는 한계가 있었던 것이다. 또한, 상기의 BGA패키지는 회로기판이 고가이므로 제품의 가격이 상승되는 요인이 됨은 물론, 상기 회로기판을 통해서 습기가 침투됨으로써 크랙이 발생하게 되는 문제점이 있다.However, such a BGA package has a limitation in miniaturizing electronic products because the package size is several times larger than the size of a semiconductor chip embedded therein. In addition, the BGA package has a problem that the price of the product is increased because the circuit board is expensive, as well as cracks are generated by the penetration of moisture through the circuit board.
이와같은 문제점을 해결하기 위하여, BGA 방식이 아니면서도 기판 접속리드를 패키지의 외부로 돌출 시키지 않고 패키지의 하면으로 노출시킴으로써 실장면적을 줄임과 동시에, 반도체 패키지의 크기를 반도체칩의 크기로 형성하여 패키지를 경박단소화 한 BLP(Bottom Leaded Package)형 CSP(Chip Scale Package)가 도 3에 도시되어 있다.In order to solve such a problem, the surface area of the package is reduced by exposing the board connection lead to the bottom surface of the package without protruding the outside of the package, and the size of the semiconductor package is formed as the size of the semiconductor chip. A BLP (Bottom Leaded Package) type Chip Scale Package (CSP) having a light weight and short size is shown in FIG. 3.
이러한 종래의 BLP형 CSP의 구조는 전자회로가 집적되어 있는 반도체칩(31)과, 상기 반도체칩(31)을 지지함과 아울러 반도체칩(31)의 신호를 외부로 전기적 접속 경로를 이루는 리드(32)와, 상기 반도체칩(31)을 전기적으로 연결시키는 와이어(33)와, 상기의 반도체칩(31), 리드(32) 및 와이어(33)를 외부환경으로 부터 보호하기 위한 봉지부(34)를 포함하며, 상기의 리드(32)는 내측으로 봉지부(34)의 저면에 노출되도록 리드(32)를 절곡 형성하여서 된 것이다.The structure of the conventional BLP type CSP includes a semiconductor chip 31 in which an electronic circuit is integrated, a lead that supports the semiconductor chip 31 and forms an electrical connection path to an external signal of the semiconductor chip 31 ( 32, a wire 33 electrically connecting the semiconductor chip 31, and an encapsulation portion 34 for protecting the semiconductor chip 31, the lead 32, and the wire 33 from an external environment. The lead 32 is formed by bending the lead 32 to be exposed to the bottom surface of the encapsulation portion 34 inward.
그러나, 상기한 BLP형 CSP는 반도체칩(31)을 전기적으로 연결시키는 와이어(33)의 루프(Loop)의 높이 만큼 패키지의 두께가 두껍게 되고, 상기 와이어(33)를 리드(32)에 본딩하기 위한 본딩 에리어(Bonding Area) 만큼의 면적이필요함으로서 패키지의 크기가 커지게 되는 등의 단점이 있어 CSP로 적합하지 못한 것이다. 또한, 상기의 BLP형 CSP는 리드(32)를 절곡하여 봉지부(34)의 저면 외부로 노출되도록 되어 이 노출된 리드(32)를 입출력 단자로 사용하는데, 이는 봉지부(34)가 리드(32)의 노출된 부분을 가리게 되는 등의 이유로 불량이 발생되는 문제점이 있었던 것이다.However, the BLP type CSP has a thickness of a package thickened by the height of a loop of the wire 33 that electrically connects the semiconductor chip 31, and bonding the wire 33 to the lead 32. It is not suitable as a CSP because there is a disadvantage that the size of the package is increased by requiring an area as large as a bonding area. In addition, the BLP type CSP is bent the lead 32 to be exposed to the outside of the bottom of the encapsulation 34 to use the exposed lead 32 as an input and output terminal, which is the encapsulation 34 is a lead ( There was a problem that a defect occurs because of covering the exposed part of 32).
뿐만 아니라, 봉지부(34)의 저면으로 리드(32)를 노출시키기 위하여 리드(32)를 절곡할때에는 다음과 같은 문제점이 발생되는 것이다.In addition, the following problem occurs when the lead 32 is bent to expose the lead 32 to the bottom surface of the encapsulation portion 34.
첫째, 리드와 리드 사이의 간격이 좁아 리드의 간섭으로 인한 절곡 작업이 난이하여 작업성이 떨어지는 것이다.First, since the gap between the lead and the lead is narrow, the bending work due to the interference of the lead is difficult, resulting in poor workability.
둘째, 리드를 절곡시키기 위한 공구(펀치)가 필요함으로서 단가의 상승요인이 되는 것이다.Second, the need for a tool (punch) to bend the lead is an increase in unit cost.
셋째, 리드를 절곡시킬때 절곡되는 길이 만큼 포지션이 이동되어 오차가 발생됨으로서 불량을 유발하는 원인이 되었던 것이다.Third, when the lead is bent, the position is moved by the length to be bent, causing an error by causing an error.
본 발명의 목적은 이와같은 문제점을 해결하기 위하여 발명된 것으로서, 반도체 패키지의 입출력 단자를 솔더볼을 사용하여 패키지의 저면으로 다수의 열과 행을 가지면서 배열되도록 함으로서 다핀화를 실현하여 패키지의 성능을 향상시키고, 패키지를 경박단소화 하여 고집적화 및 고성능화 할 수 있도록 된 반도체 패키지의 저면으로 솔더볼이 융착된 리드프레임 제조방법을 제공하는데 있다.An object of the present invention is to solve the above problems, by using a solder ball to the input and output terminals of the semiconductor package to have a plurality of columns and rows arranged on the bottom of the package to realize the multi-pinning to improve the performance of the package The present invention provides a lead frame manufacturing method in which solder balls are fused to the bottom surface of a semiconductor package, which enables high integration and high performance by making the package light and small.
도 1은 종래의 일반적인 반도체 패키지를 나타낸 단면도1 is a cross-sectional view showing a conventional general semiconductor package
도 2는 종래의 BGA패키지를 나타낸 단면도Figure 2 is a cross-sectional view showing a conventional BGA package
도 3은 종래의 BLP형 CSP를 나타낸 단면도3 is a cross-sectional view showing a conventional BLP type CSP
도 4는 본 발명에 따른 리드의 저면에 솔더볼이 융착된 상태를 나타낸 도면4 is a view showing a state in which the solder ball is fused to the bottom of the lead according to the invention
도 5는 본 발명에 따른 리드에 솔더볼이 융착된 상태를 나타낸 요부 확대도5 is an enlarged view illustrating main parts of a solder ball welded to a lead according to the present invention;
도 6은 본 발명에 따른 리드에 솔더볼을 융착하기 위한 수단으로서 테이프에 미리 솔더볼을 융착시킨 상태의 일예를 나타낸 도면6 is a view showing an example of a state in which the solder ball is fused to the tape in advance as a means for fusion welding the solder ball on the lead according to the present invention;
도 7은 본 발명에 따른 리드에 솔더볼을 융착하기 위한 수단으로 사용되는 지그를 나타낸 도면7 is a view showing a jig used as a means for welding the solder ball to the lead according to the present invention;
도 8은 본 발명에 따른 리드프레임을 이용한 반도체 패키지의 구조를 나타낸 단면도8 is a cross-sectional view illustrating a structure of a semiconductor package using a lead frame according to the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
41 - 반도체 칩 42 - 리드41-Semiconductor Chip 42-Lead
43 - 와이어 44 - 봉지부43-wire 44-encapsulation
45 - 솔더볼45-Solder Ball
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 반도체 패키지의 저면으로 솔더볼이 융착된 리드프레임 제조방법은, 반도체 패키지를 구성하기 위한 다수의 리드(42)로 이루어진 리드프레임에 있어서, 상기 다수의 리드(42) 저면에 솔더볼(45)을 융착하여 반도체 패키지의 입출력 단자로 사용하되, 상기 솔더볼(45)은 반도체 패키지의 저면에 다수의 열과 행을 가지면서 배열되도록 융착되는 것을 특징으로 한다.A lead frame manufacturing method in which solder balls are fused to a bottom surface of a semiconductor package according to the present invention includes a lead frame including a plurality of leads 42 for constituting a semiconductor package, wherein the solder balls 45 are formed on a bottom surface of the plurality of leads 42. ) To be used as an input / output terminal of the semiconductor package, wherein the solder ball 45 is fused to be arranged with a plurality of columns and rows on the bottom surface of the semiconductor package.
상기 다수의 리드(42) 저면에 융착되어 반도체 패키지의 입출력 단자로 사용되는 솔더볼(45)은 테이프(51)에 다수의 열과 행을 가지면서 배열되도록 융착한 다음, 리드(42)의 저면에 위치시킨 상태에서 솔더볼(45)을 리플로우(Reflow)하여 리드(42)의 저면에 융착시킨 후, 테이프(51)를 제거하는 것이다. 또한, 솔더볼(45)이 다수의 열과 행을 가지면서 배열되는 안착홈(52a)이 형성된 지그(52 ; Jig)를 사용하여 리드(42)의 저면에 융착시키는 것이다.The solder balls 45, which are fused to the bottoms of the plurality of leads 42 and used as input / output terminals of the semiconductor package, are welded to the tape 51 to be arranged with a plurality of rows and rows, and then placed on the bottom of the leads 42. In this state, the solder ball 45 is reflowed and fused to the bottom surface of the lead 42, and then the tape 51 is removed. In addition, the solder ball 45 is fused to the bottom surface of the lead 42 by using a jig 52 (Jig) in which a mounting groove 52a in which a plurality of rows and rows are arranged is formed.
상기와 같이 리드(42)의 저면으로 솔더볼(45)을 융착하여 반도체 패키지의 입출력 단자를 형성하면, 리드를 절곡할 필요가 없어 작업이 용이하고, 리드 절곡에 의한 포지션 이동이 없음으로서 불량을 방지할 수 있는 것이다.As described above, when the solder ball 45 is fused to the bottom surface of the lead 42 to form the input / output terminal of the semiconductor package, the lead does not need to be bent, so the work is easy, and there is no position movement due to the bending of the lead, thereby preventing defects. You can do it.
이와같이 구성되는 리드프레임을 이용한 반도체 패키지의 구조는 전자회로가 집적되어 있는 반도체칩(41)과, 상기 반도체칩(41)의 신호를 전기적 접속시키는 와이어(43)와, 상기 와이어(43)에 연결되어 반도체칩(41)의 신호를 외부로 전달하는 리드(42)와, 상기의 반도체칩(41), 와이어(43) 및 리드(42)를 외부환경으로 부터 보호하기 위하여 감싸진 봉지부(44)를 포함하며, 상기의 리드(42)는 저면에솔더볼(45)이 다수의 열과 행을 가지면서 배열되도록 융착되어 봉지부(44)의 저면으로 돌출되는 것이다.The structure of the semiconductor package using the lead frame configured as described above is connected to the semiconductor chip 41 in which the electronic circuit is integrated, the wire 43 for electrically connecting the signal of the semiconductor chip 41, and the wire 43. And a lead portion 42 which transmits a signal of the semiconductor chip 41 to the outside, and an encapsulation portion 44 wrapped to protect the semiconductor chip 41, the wire 43, and the lead 42 from an external environment. The lead 42 is fused so that the solder ball 45 is arranged to have a plurality of columns and rows on the bottom surface thereof and protrudes to the bottom surface of the encapsulation portion 44.
이와같이 구성된 반도체 패키지는 마더보드(Mother Board)에 실장시 리드(42)의 저면으로 융착된 솔더볼(45)에 의해 실장됨으로서 실장이 용이하고, 다핀화를 실현할 수 있어 패키지의 성능을 향상시키며, 패키지를 경박단소화 하여 고집적화 및 고성능화 할 수 있는 것이다.The semiconductor package configured as described above is mounted by a solder ball 45 fused to the bottom surface of the lead 42 when mounted on a motherboard, so that the semiconductor package can be easily mounted and the pin can be realized to improve the performance of the package. It is possible to achieve high integration and high performance by light and small size.
이상의 설명에서와 같이 본 발명에 의하면, 리드의 저면으로 솔더볼을 융착하여 반도체 패키지의 저면으로 다수의 열과 행을 가지면서 배열시켜 패키지의 입출력 단자를 형성함으로서, 다핀화를 실현할 수 있어 패키지의 성능을 향상시키고, 마더보드에 실장시 패키지의 저면으로 돌출된 보조리드에 의해 실장이 용이하며, 패키지를 경박단소화 하여 고집적화 및 고성능화 할 수 있는 효과가 있다.According to the present invention as described above, by soldering the solder ball to the bottom of the lead and arranged with a plurality of rows and rows on the bottom of the semiconductor package to form the input and output terminals of the package, it is possible to realize the multi-pinning to improve the performance of the package Improved and easy to mount by the auxiliary lead protruding to the bottom of the package when mounted on the motherboard, it has the effect of high integration and high performance by making the package light and small.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960058754A KR100381840B1 (en) | 1996-11-28 | 1996-11-28 | Method for manufacturing lead frame having solder ball thermally attached to backside of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960058754A KR100381840B1 (en) | 1996-11-28 | 1996-11-28 | Method for manufacturing lead frame having solder ball thermally attached to backside of semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980039674A KR19980039674A (en) | 1998-08-17 |
| KR100381840B1 true KR100381840B1 (en) | 2003-07-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960058754A KR100381840B1 (en) | 1996-11-28 | 1996-11-28 | Method for manufacturing lead frame having solder ball thermally attached to backside of semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR100381840B1 (en) |
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1996
- 1996-11-28 KR KR1019960058754A patent/KR100381840B1/en not_active IP Right Cessation
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| KR19980039674A (en) | 1998-08-17 |
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