CN104409447A - Embedded capacitor-containing semiconductor package and manufacturing method thereof - Google Patents
Embedded capacitor-containing semiconductor package and manufacturing method thereof Download PDFInfo
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- CN104409447A CN104409447A CN201410724218.1A CN201410724218A CN104409447A CN 104409447 A CN104409447 A CN 104409447A CN 201410724218 A CN201410724218 A CN 201410724218A CN 104409447 A CN104409447 A CN 104409447A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
The invention provides an embedded capacitor-containing semiconductor package and a manufacturing method thereof. The semiconductor package comprises a substrate, at least one chip, a first plastic packaging material, a first conductive thin film, a second conductive thin film, a capacitor and a second plastic packaging material, wherein the at least one chip is positioned on the substrate and is electrically connected with the substrate; the first plastic packaging material is arranged on the substrate and packages the at least one chip; the first conductive thin film covers the outer surface of the first plastic packaging material; the second conductive thin film coats the first conductive thin film; the capacitor is positioned between the first conductive thin film and the second conductive thin film; two electrodes of the capacitor are electrically connected to the first conductive thin film and the second conductive thin film respectively; the second plastic packaging material is positioned between the first conductive thin film and the second conductive thin film and packages the capacitor.
Description
Technical field
The present invention relates to the electromagnetic shielding field to electronic device, more particularly, relate to a kind of embedded capacitor that utilizes and carry out semiconductor package part comprising embedded capacitor of shield electromagnetic interference signal and preparation method thereof.
Background technology
Along with miniaturization, the high speed processing of electronic product, semiconductor subassembly has become more complicated.But while promoting the processing speed of semiconductor subassembly and miniaturization, also problem served by band.Especially, current electronic devices is made up of extensive and very lagre scale integrated circuit (VLSIC), and very easily by outside electromagnetic interference, they also externally launch the electromagnetic wave of different frequency simultaneously, causes interference to the contiguous electronic equipment run.
In the prior art, as shown in fig. 1, usually at semiconductor package part outer surface conductive film 10, this conductive film 10 is electrically connected to the earth signal of substrate simultaneously.When this semiconductor package part is attacked in the electromagnetic radiation coming from packaging part inside, electromagnetic radiation because of conductive film 10 by electrical short, thus can reduce the adverse effect to contiguous semiconductor device at least partially.In addition, conductive film 10 can absorb extraneous electromagnetic interference signal, is current vortex, reduces the interference to chip, guarantee that chip works when the external world exists electromagnetic interference by the Conversion of Energy of electromagnetic signal.Meanwhile, conductive film can as the secondary path returning earth signal.
But along with the development of electronic product, to preventing, the requirement of electromagnetic interference is more and more higher, the demand of signal integrity is improved constantly, needs badly at present and a kind ofly can realize the semiconductor package part of good electromagnetic isolation and more superior signal integrity sex expression and relevant preparation technology.
Summary of the invention
Exemplary embodiment of the present invention relates to a kind of semiconductor package part comprising embedded capacitor, described semiconductor package part can under bilayer conductive film and the effect being placed in the capacitor between bilayer conductive film, make the external world conduct to the electromagnetic interference signal decay of semiconductor package part, thus reduce the interference of electromagnetic signal.In addition, because bilayer conductive film is electrically connected between power supply signal and earth signal respectively, therefore capacitor directly carries out the decoupling of power supply to semiconductor package part, and this is more conducive to signal integrity.
Exemplary embodiment of the present invention also relates to a kind of method preparing the semiconductor package part comprising embedded capacitor, can realize the semiconductor package part with good electromagnetic isolation and more superior signal integrity by the method.In addition, the technological process of the method is simple, is easy to realize.
According to an aspect of the present invention, a kind of semiconductor package part comprising embedded capacitor can comprise: substrate; At least one chip, to be positioned on substrate and to be electrically connected with substrate; First capsulation material, is arranged on substrate and also encapsulates at least one chip described; First conductive film, covers the outer surface of the first capsulation material; Second conductive film, coated first conductive film; Capacitor, between the first conductive film and the second conductive film, the two poles of the earth of capacitor are electrically connected to the first conductive film and the second conductive film respectively; And second capsulation material, between the first conductive film and the second conductive film and enclosed capacitor.
According to an aspect of the present invention, a kind of method of the semiconductor package part for the preparation of comprising embedded capacitor can comprise the steps: to make the first capsulation material encapsulate at least one chip be arranged on substrate; First conductive film is covered the outer surface of the first capsulation material; Capacitor electrode is electrically connected with the first conductive film; The second capsulation material is utilized to encapsulate the first conductive film and capacitor, and another electrode of exposed capacitor; Second conductive film is covered the outer surface of the second capsulation material, and the electrode be exposed of capacitor is electrically connected with the second conductive film, wherein, the first conductive film is electrically connected to power supply signal, and the second conductive film is electrically connected to earth signal.
Accompanying drawing explanation
By the description carried out exemplary embodiment below in conjunction with accompanying drawing, the present invention may be better understood for those skilled in the art.It should be understood that all parts in accompanying drawing need not be drawn in proportion.On the contrary, for the sake of clarity, can at random increase or reduce the size of all parts in the accompanying drawings.In addition, identical in whole specification with accompanying drawing Reference numeral represents identical element all the time.In the accompanying drawings:
Fig. 1 illustrates the cutaway view preventing the semiconductor package part of electromagnetic interference according to prior art;
Fig. 2 illustrates the cutaway view being embedded with the semiconductor package part of capacitor according to the first exemplary embodiment of the present invention;
Fig. 3 illustrates the cutaway view being embedded with the semiconductor package part of capacitor according to the second exemplary embodiment of the present invention;
Fig. 4 illustrates the cutaway view being embedded with the semiconductor package part of capacitor according to the 3rd exemplary embodiment of the present invention;
Fig. 5 a to Fig. 5 c illustrates the process chart of preparation according to the semiconductor package part of the 3rd exemplary embodiment of the present invention.
Embodiment
In more detail the present invention is described below with reference to accompanying drawings, exemplary embodiment of the present invention shown in the drawings.It will be appreciated by those skilled in the art that only with illustrative meaning to provide these embodiments, and should not be interpreted as limiting the scope of the invention.On the contrary, provide these embodiments to make the disclosure to be thoroughly with complete, and scope of the present invention will be conveyed to those skilled in the art fully.
Fig. 2 illustrates the cutaway view preventing the semiconductor package part of electromagnetic interference according to exemplary embodiment of the present invention.
With reference to Fig. 2, substrate 20 can be comprised according to the semiconductor package part of exemplary embodiment of the present invention, arrange be electrically connected on the base plate 20 and with substrate 20 chip assembly 100, arrange on the base plate 20 and the first capsulation material 110 of encapsulate chip assembly 100 and cover first conductive film 200 of outer surface of the first capsulation material 110.In an exemplary embodiment of the present invention, the second capsulation material 120 can be arranged on the first conductive film 200 and to cover the outer surface of the first conductive film 200.Second conductive film 300 can be arranged on the outer surface of the second capsulation material 120, and coated second capsulation material 120.In addition, capacitor 400 can be provided with between the first conductive film 200 and the second conductive film 300, an electrode of capacitor 400 is electrically connected to the first conductive film 200, another electrode of capacitor 400 is electrically connected to the second conductive film 300, and capacitor 400 is embedded in the second capsulation material 120.
In an exemplary embodiment of the present invention, the first conductive film 200 can be electrically connected to the power supply signal of substrate 20, and the second conductive film 300 can be electrically connected to the earth signal of substrate 20.
Substrate 20 can be other substrate in printed circuit board (PCB), ceramic substrate, copper clad laminate or this area.Chip assembly 100 can be at least a chip.Chip assembly 100 can be electrically connected to substrate 20 by wire bonding or by the mode that tin ball bonding connects.In addition, can be electrically connected by connected mode known in the art between the chip in chip assembly 100.
Material for the formation of the first capsulation material 110 can be identical with the material of the second capsulation material 120, all can be epoxy powder coating material, but the present invention is not limited thereto.Such as, other capsulation material can be applied to this.First capsulation material 110 and the second capsulation material 120 can be formed respectively by twice Shooting Technique.
In an exemplary embodiment of the present invention, the second conductive film 300 can the side surface of covered substrate 20, and the side surface due to substrate 20 is powerful radiation source, and therefore this structure can reduce the electromagnetic radiation that device sends significantly.In addition, the material for the formation of the first conductive film 200 and the second conductive film 300 can be the same or different.In an exemplary embodiment of the present invention, the material for the formation of the first conductive film 200 and the second conductive film 300 can comprise at least one in the metal good conductors such as Cu, Ni, Au, Pd and the composite material between them, but is not limited thereto.Such as, described material can comprise all good conductive materials is the material of matrix.In addition, conductivity is slightly weak, but in micro-wave screening, have the such as ferrite of good behaviour, the material of ferrimagnet also can be used for formed conductive film.
Although in the exemplary embodiment shown in the present invention, the first conductive film 200 covers the outer surface of the first capsulation material 110 completely, the present invention is not limited thereto.Such as, in another exemplary embodiment of the present invention, the first conductive film partly can cover the outer surface of the first capsulation material, and the first conductive film is electrically connected to power supply signal.
First conductive film 200 and the second conductive film 300 can be made by traditional films manufacture methods such as plating, sputterings.
Capacitor 400 between the first conductive film 200 and the second conductive film 300 can for being suitable for Embedded capacitor, and such as, other volume such as multilayer ceramic capacitor or film capacitor is little, be suitable for the capacitor etc. that embeds.Capacitor 400 can be arranged between the first conductive film 200 and the second conductive film 300 by surface mounting technology, and capacitor 400 electrode is electrically connected with the first conductive film 200, and another electrode is electrically connected with the second conductive film 300.
As shown in Figure 2, capacitor 400 can be arranged between the sidewall of the first conductive film 200 and the second conductive film 300, to make the semiconductor package part being embedded with capacitor 400 thinning, but the present invention is not limited thereto, capacitor 400 can be arranged on the optional position between the first conductive film 200 and the second conductive film 300, as long as capacitor 400 electrode is electrically connected to the first conductive film 200, another electrode is electrically connected to the second conductive film 300.
Fig. 3 shows the cutaway view of the semiconductor package part according to the second exemplary embodiment of the present invention.Hereinafter, in order to avoid redundancy, eliminate the description to similar elements and structure.Hereinafter, the difference of this exemplary embodiment and above-described embodiment is only described in detail.
As shown in Figure 3, in the second exemplary embodiment of the present invention, the shape of the first capsulation material 110 of plastic package chip assembly 100 can be consistent with the global shape of chip assembly 100.Coated first capsulation material 110 of first conductive film 200, therefore, the contour shape of the first conductive film 200 also can be consistent with the global shape of chip assembly 100.Based on this, capacitor 400 can be arranged in the recess place of the first capsulation material 110 of packaged chip assembly 100, realizes respectively and electrical connection between the first conductive film 200 and the second conductive film 300 simultaneously.
Fig. 4 shows the cutaway view of the semiconductor package part according to the 3rd exemplary embodiment of the present invention.Hereinafter, in order to avoid redundancy, eliminate the description to similar elements and structure.
As shown in Figure 4, first capsulation material 110 of plastic package chip assembly 100 and the shape of the first conductive film 200 can be rectangle, capacitor 400 can be arranged on the first conductive film 200, and two electrodes realizing capacitor 400 are electrically connected with the first conductive film 200 and the second conductive film 300 respectively.
The shape of the first capsulation material 100 and the position of capacitor can be not limited to above-mentioned exemplary embodiment.
Fig. 5 a to Fig. 5 c illustrates the process chart of preparation according to the semiconductor package part of the 3rd exemplary embodiment of the present invention.
According to the manufacture method being embedded with the semiconductor package part of capacitor of the present invention, it comprises the steps.As illustrated in fig. 5 a, first, chip assembly 100 is arranged on the base plate 20, and chip assembly 100 is realized being electrically connected with substrate 20; Then, form the first capsulation material 110 on the base plate 20 and make the first capsulation material 110 encapsulate chip assembly 100, that is, arranging that all chips that chip assembly 100 on the base plate 20 comprises all are encapsulated in wherein by the first capsulation material 110; First capsulation material 110 is formed the first conductive film 200 of coated first capsulation material 110.
Injection molding process can be utilized formed the first capsulation material 110.In addition, the traditional films manufacture methods such as plating, sputtering can be utilized to carry out the first conductive film 200 of the outer surface of obtained covering first capsulation material 110.First conductive film 200 not only can cover the upper surface of the first capsulation material 110, and covers the side of the first capsulation material 110.
Then, as illustrated in fig. 5b, be arranged on by capacitor 400 on first conductive film 200, and make capacitor 400 electrode be electrically connected to the first conductive film 200, another electrode does not contact the first conductive film 200.Capacitor 400 can be multilayer ceramic capacitor, but is not limited thereto, and such as, can be suitable for Embedded capacitor for other type in this area.Capacitor 400 can be arranged on the first conductive film 200 by surface mount process.
As shown in Figure 5 c, injection molding process is utilized to form the second capsulation material 120 on the first conductive film 200, second capsulation material 120 not only covers the upper surface of the first conductive film 200, but also cover the side of the first conductive film 200, thus realize the plastic packaging to the second conductive film 200.In addition, capacitor 400 is placed in the second capsulation material 120, and another electrode described of capacitor 400 is exposed by the second capsulation material 120.In an exemplary embodiment of the present invention, can while the first conductive film 200 and capacitor 400 be encapsulated, another electrode described of direct exposed capacitor 400, but the present invention is not limited thereto.Such as, in another exemplary embodiment of the present invention, can, after encapsulating the first conductive film 200 and capacitor 400, by the additional technique of such as laser drill or etching etc., another electrode described in capacitor 400 be exposed.
Secondly, utilize the techniques such as sputtering, plating on the second capsulation material 120, form the second conductive film 300 of coated second capsulation material 120, and another electrode described be exposed of capacitor 400 is electrically connected with the second conductive film 300.In an exemplary embodiment of the present invention, the second conductive film 300 not only covers the upper surface of the second capsulation material 120, and covers the side surface of the second capsulation material 120.In another exemplary embodiment of the present invention, the side surface of all right covered substrate 20 of the second conductive film.
Although in the exemplary embodiment shown in the present invention, the first conductive film 200 covers the outer surface of the first capsulation material 110 completely, the present invention is not limited thereto.Such as, in another exemplary embodiment of the present invention, the first conductive film partly can cover the outer surface of the first capsulation material, and the first conductive film is electrically connected to power supply signal.
Owing to describe in detail material for the formation of all parts of the present invention and structure hereinbefore, therefore, no longer repeatedly describe at this.
In an exemplary embodiment of the present invention, first conductive film 200 can be electrically connected to the power supply signal of substrate, second conductive film 300 can be electrically connected to the earth signal of substrate, namely, second conductive film 300 ground connection, and the first conductive film 200 and the second conductive film 300 can be electrically connected with two electrodes of capacitor 400 respectively.Therefore, the external world passes to the electromagnetic interference signal to semiconductor package part of the present invention, can decay, thus reduce the interference of electromagnetic signal under the effect of bilayer conductive film and capacitor.In addition, capacitor is placed between earth signal and power supply signal, and therefore capacitor directly can carry out the decoupling of power supply to semiconductor package part, is more conducive to the integrality of signal.In addition, bilayer conductive film and the capacitor be placed between bilayer conductive film also can realize good electromagnetic isolation, prevent from having an impact to contiguous device, and achieve more superior signal integrity sex expression.
In addition, the method technological process that the preparation that exemplary embodiment of the present invention provides comprises the semiconductor package part of embedded capacitor is simple, is easy to realize.
Although be specifically described the present invention in conjunction with the specific embodiments, but it will be appreciated by those skilled in the art that without departing from the spirit and scope of the present invention, various amendment in form and details and change can be carried out to these embodiments.Scope of the present invention is by claims and equivalents thereof.
Claims (10)
1. comprise a semiconductor package part for embedded capacitor, it is characterized in that, described semiconductor package part comprises:
Substrate;
At least one chip, to be positioned on substrate and to be electrically connected with substrate;
First capsulation material, is arranged on substrate and also encapsulates at least one chip described;
First conductive film, covers the outer surface of the first capsulation material;
Second conductive film, coated first conductive film;
Capacitor, between the first conductive film and the second conductive film, the two poles of the earth of capacitor are electrically connected to the first conductive film and the second conductive film respectively; And
Second capsulation material, between the first conductive film and the second conductive film and enclosed capacitor.
2. semiconductor package part as claimed in claim 1, it is characterized in that, the first conductive film is electrically connected to power supply signal, and the second conductive film is electrically connected to earth signal.
3. semiconductor package part as claimed in claim 2, it is characterized in that, the first conductive film part covers the outer surface of the first capsulation material.
4. semiconductor package part as claimed in claim 1, it is characterized in that, substrate is printed circuit board (PCB), ceramic substrate or copper clad laminate.
5. semiconductor package part as claimed in claim 1, is characterized in that, the first capsulation material and the second capsulation material are formed by twice Shooting Technique.
6., for the preparation of the method for semiconductor package part comprising embedded capacitor, it is characterized in that, described method comprises the steps:
The first capsulation material is made to encapsulate at least one chip be arranged on substrate;
First conductive film is covered the outer surface of the first capsulation material;
Capacitor electrode is electrically connected with the first conductive film;
The second capsulation material is utilized to encapsulate the first conductive film and capacitor, and another electrode of exposed capacitor;
Second conductive film is covered the outer surface of the second capsulation material, and another electrode be exposed of capacitor is electrically connected with the second conductive film,
Wherein, the first conductive film is electrically connected to power supply signal, and the second conductive film is electrically connected to earth signal.
7. method as claimed in claim 6, it is characterized in that, the first conductive film part covers the outer surface of the first capsulation material.
8. method as claimed in claim 6, it is characterized in that, utilize the second capsulation material to encapsulate the first conductive film and capacitor and the step of another electrode of exposed capacitor be included in utilize the second capsulation material to encapsulate the first conductive film and capacitor while another electrode described of direct exposed capacitor.
9. method as claimed in claim 6, it is characterized in that, the second capsulation material is utilized to encapsulate the first conductive film and capacitor and the step of another electrode of exposed capacitor comprises: utilizing after the second capsulation material encapsulates the first conductive film and capacitor, to utilize additional technique to carry out another electrode described of exposed capacitor.
10. method as claimed in claim 9, it is characterized in that, described additional technique is laser drill or etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410724218.1A CN104409447A (en) | 2014-12-03 | 2014-12-03 | Embedded capacitor-containing semiconductor package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410724218.1A CN104409447A (en) | 2014-12-03 | 2014-12-03 | Embedded capacitor-containing semiconductor package and manufacturing method thereof |
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| CN104409447A true CN104409447A (en) | 2015-03-11 |
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| CN201410724218.1A Pending CN104409447A (en) | 2014-12-03 | 2014-12-03 | Embedded capacitor-containing semiconductor package and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107507824A (en) * | 2017-09-13 | 2017-12-22 | 尚睿微电子（上海）有限公司 | A kind of encapsulating structure with electro-magnetic screen function and preparation method thereof |
| CN110277381A (en) * | 2018-03-15 | 2019-09-24 | 三星电子株式会社 | Semiconductor package assembly and a manufacturing method thereof |
| CN112242386A (en) * | 2019-07-16 | 2021-01-19 | 江苏长电科技股份有限公司 | SIP packaging structure |
| CN113793843A (en) * | 2021-09-30 | 2021-12-14 | 重庆平创半导体研究院有限责任公司 | Anti-irradiation packaging structure and method |
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| CN113793843A (en) * | 2021-09-30 | 2021-12-14 | 重庆平创半导体研究院有限责任公司 | Anti-irradiation packaging structure and method |
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