CN105870109B - A kind of 2.5D integration packaging semiconductor devices and its processing method - Google Patents
A kind of 2.5D integration packaging semiconductor devices and its processing method Download PDFInfo
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- CN105870109B CN105870109B CN201610335717.0A CN201610335717A CN105870109B CN 105870109 B CN105870109 B CN 105870109B CN 201610335717 A CN201610335717 A CN 201610335717A CN 105870109 B CN105870109 B CN 105870109B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/43—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Present invention discloses a kind of 2.5D integration packaging semiconductor devices and its processing methods, including pinboard, back layer gold is provided on the top surface of pinboard, several tin balls of the underrun of pinboard and PCB substrate connection communication, and they cooperatively form the semiclosed shielding space of specified quantity, at least one upside-down mounting is provided in each shielding space in the chip of pinboard bottom surface, pad connection communication on the bottom surface and PCB substrate of chip is provided with package tin ball and fills the filling glue-line of shielding space between PCB substrate and pinboard.The present invention had both remained the advantages such as the fine wiring integrated level of conventional 2.5D packaging technology is high, low in energy consumption, stress is low, semi-enclosed shielding space is formed again, chip is installed on by the bottom surface of pinboard by reverse installation process again and is located in above-mentioned shielding space, so as to effectively improve the anti-electromagnetic interference capability and antistatic impact capacity of final products.
Description
Technical field
The present invention relates to a kind of semiconductor devices and its processing method more particularly to a kind of 2.5D integration packaging semiconductor devices
Part and its processing method.
Background technique
SIP(System In a Package system in package) it is for example including processor, to deposit multiple functions chip
The functional chips such as reservoir are integrated in an encapsulation, to realize the packaging technology of a basic complete function.SIP is suitable for
On low cost, small area, high-frequency high-speed and electronic product with short production cycle, especially as power amplifier (PA), the whole world are fixed
The portable products markets such as position system, bluetooth module (Bluetooth), image sensing module, memory card.
But in many systems, the cabling on the SIP package substrate of conventional 2D packaging technology is than walking on silicon substrate
The several orders of magnitude of line width, the difference in this size influences whether properties of product and power consumption, in addition, wider on SIP package substrate
Cabling easily lead to routing congestion, therefore have very big limitation to achievable chip type and chip connection quantity,
Thus there is 2.5D packaging technology.
As shown in Fig. 1, traditional 2.5D packaging technology is put between SIP package substrate 20 and at least two chips 30
A silicon intermediary layer 40 has been set, has had silicon perforation (TSV) 50 to be connected thereto the metal layer and following table on surface on this silicon intermediary layer 40
The metal layer in face, also, on the front and back metal layer (may all have multiple metal layers in the case of two kinds) of silicon intermediary layer 40
Cabling be to be made using processing procedure identical with the cabling on silicon chip, chip 30 is connected to silicon using miniature 60 upside-down mounting of tin ball
Intermediary layer 40, at the same time, silicon intermediary layer 40 are connected to SIP substrate 20 using common chip connection solder bump 70.
Advantage using 2.5D packaging technology is that this is upgrading on the basis of traditional 2D encapsulation technology, can hold
Amount and aspect of performance provide huge promotion amplitude, and with the advantage in terms of yield, because with the single big chip of production
It compares, makes many small chips and be more easier；However semiconductor devices made of this packaging technology, however it remains certain
Problem is mainly manifested in:
Since the chip in 2.5D packaging technology product lacks effective electromagnetism, electrostatic shielding structure, chip resists
Electromagnetic interference performance is poor, and antistatic impact capacity is weak, however the products application of 2.5D packaging technology will be used in various equipment
When, since the electromagnetic interference source in equipment is more, electrostatic impact easily occurs, the validity and stability of each chip operation are past
Toward not can guarantee, also just usually there is situation about can not try out；And 2.5D packaging technology is also unable to satisfy high power class device
Radiating requirements.
Summary of the invention
An object of the present invention is positive by pinboard exactly in order to solve the above-mentioned problems in the prior art
Back layer gold and tin ball, PCB substrate cooperatively form semi-enclosed shielding space, and chip is installed on pinboard by reverse installation process
Bottom surface and be located at shielding space in, to provide the 2.5D that a kind of anti-electromagnetic interference capability is good and antistatic impact capacity is strong
Integration packaging semiconductor devices and its processing method.
The purpose of the present invention is achieved through the following technical solutions:
A kind of 2.5D integration packaging semiconductor devices, including pinboard are provided with back layer gold on the top surface of the pinboard,
Several tin balls of the underrun of the pinboard and PCB substrate connection communication, and they cooperatively form the semiclosed of specified quantity
Shielding space is provided at least one upside-down mounting in the chip of the pinboard bottom surface, the chip in each shielding space
Bottom surface and PCB substrate on pad connection communication, package is provided between the PCB substrate and pinboard and the tin ball and is filled out
Fill the filling glue-line of the shielding space.
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: the pinboard is silicon substrate pinboard.
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: it is described back layer gold area and shape with
The area of the switching plate top surface is identical with shape.
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: the back layer gold is Pt metal layer or Ni
The combination layer of layer or Cr layers or W layers or Au layers or AL layers or Cu layers or the above metal.
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: the height of the tin ball is 0.15mm-
0.35mm。
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: the shielding space is two, each
A chip is provided in shielding space.
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: the chip passed through described in several be located at
The dimpling block of pinboard bottom is connected and communicated with the pinboard, and the dimpling block is coated between pinboard bottom and chip
Underfill layer in.
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: the dimpling block is gold goal or tin ball.
Preferably, a kind of 2.5D integration packaging semiconductor devices, in which: the pad passes through tin cream or conductive silver
Slurry connect conducting with the bottom surface of the chip.
A kind of processing method of above-mentioned 2.5D integration packaging semiconductor devices comprising following steps,
S1 carries on the back layer gold procedure of processing: forming back layer gold in the top surface of pinboard；
Flip-chip step: S2 by reverse installation process, makes the chip of specified quantity and the bottom surface circuit layer of the pinboard
It connects and realizes that they are communicated；
S3, pinboard plant ball step: planting playing skill art in the bottom surface of the pinboard according to specified layout form system by BGA
Make a number of tin ball；
The connection step of S4, chip and PCB substrate: conductive silver paste or tin cream are applied on the pad of the PCB substrate, and real
The connection of the existing chip and PCB substrate；
The connection step of S5, pinboard and PCB substrate: the pinboard Surface Mount of aforementioned four step will be completed described in
In PCB substrate, and the connection of realization and the pinboard and PCB substrate；
S6, filler step: filling the gap between the pinboard and PCB substrate with filling glue, and makes to fill glue covering
The tin ball of periphery.
Preferably, the processing method of the 2.5D integration packaging semiconductor devices, in which: the S2, flip-chip step
Suddenly include the following steps:
S21, in the dimpling block of the electrode layer surface production setting quantity of the chip；
S22, by welding technique, by the dimpling block by flip-chip on the pinboard, realize the chip
With the communication of pinboard；
S23 fills high-heat-conductivity glue body between the chip and pinboard and forms the underfill for covering the dimpling block
Layer.
The advantages of technical solution of the present invention, is mainly reflected in:
Deft design of the present invention, structure is simple, is guaranteeing the fine wiring integrated level height of routine 2.5D packaging technology, power consumption
On the basis of the low, characteristics such as stress is low, by the way that back layer gold is arranged in pinboard front, and pass through pinboard and tin ball, PCB substrate
Semi-enclosed shielding space is cooperatively formed, then chip is installed on by the bottom surface of pinboard by reverse installation process and is located at above-mentioned screen
It covers in space, so as to effectively improve the anti-electromagnetic interference capability and antistatic impact capacity of final products, and thermal diffusivity
2.5D encapsulation chip that can be relatively conventional is suitable for the encapsulation of high power device more preferably.
On the other hand, 2.5D integration packaging semiconductor devices of the invention does not need the setting silicon in silicon substrate pinboard and wears
Hole (TSV), structure and processing are all simpler.
Due to using controlled collapsible chip connec-tion, sufficiently solve as chip thinning and caused by chip warpage, sagging
Problem, meanwhile, the DIP chip integrated based on silicon substrate pinboard can further reduce product ruler relative to common DIP chip
It is very little.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the semiconductor devices of routine 2.5D packaging technology in background technique；
Fig. 2 is structural schematic diagram of the invention；
Fig. 3 is S1 in method of the invention, carries on the back the status diagram of layer gold procedure of processing；
Fig. 4 is S2 in method of the invention, the status diagram of flip-chip step
Fig. 5 is S3 of the invention, and pinboard plants the status diagram of ball step；
Fig. 6 is the distribution schematic diagram of tin ball in method of the invention；
Fig. 7 is S4 in method of the invention, the connection step and S5 of chip and PCB substrate, the connection of pinboard and PCB substrate
The status diagram of logical step；
Fig. 8 is S6 in method of the invention, the status diagram of filler step.
Specific embodiment
The purpose of the present invention, advantage and feature, by by the non-limitative illustration of preferred embodiment below carry out diagram and
It explains.These embodiments are only the prominent examples using technical solution of the present invention, it is all take equivalent replacement or equivalent transformation and
The technical solution of formation, all falls within the scope of protection of present invention.
A kind of 2.5D integration packaging semiconductor devices that the present invention discloses, as shown in Fig. 2, including pinboard 1, described turn
Fishplate bar 1 is the substrate of known various feasible materials, preferably silicon substrate pinboard；Meanwhile it being set on the top surface of the pinboard 1
It is equipped with back layer gold 2, the area and shape of the back layer gold 2 are identical as the area of 1 top surface of pinboard and shape, so as to
Guarantee that the later period in subsequent shielding construction, can fully ensure that the closure of shielding construction, integrality and have to greatest extent
Effect property, so as to improve shield effectiveness；And the back layer gold 2 be Pt metal layer or Ni layers or Cr layers or W layers or Au layers or AL layers or
The combination layer of Cu layers or the above metal.And several tin balls 3 of underrun of the pinboard 1 connect and lead to PCB substrate 4
Letter, the size of the tin ball 3 can according to need setting, and the height of preferably the tin ball 7 is 0.15mm- in the present embodiment
0.35mm。
The pinboard 1 cooperatively forms the semi-enclosed shielding space 5 of specified quantity with the tin ball 3, PCB substrate 4, often
At least one chip 6 that 1 bottom surface of pinboard is installed on by reverse installation process is provided in a shielding space 5.
Detailed, the chip 6 is connect by several dimpling blocks 9 positioned at 1 bottom of pinboard with the pinboard 1
And communicate, the dimpling block 9 can be the various metal or alloy with excellent conductive performance, preferably described micro- in the present embodiment
Convex block 9 is gold goal or tin ball, and the dimpling block 9 is coated on the Underfill layer 10 between 1 bottom of pinboard and chip 6
In.
Meanwhile the material of the Underfill layer 10 is at present with epoxy resin, phenolic resin, organic siliconresin and unsaturation
Polyester resin is the most commonly used, preferably epoxy resin plastic packaging glue, and adds the filler materials such as silica, aluminium oxide wherein, to change
The performances such as intensity, electrical property, the viscosity of kind encapsulating material, and the thermomechanical reliability of encapsulating structure is promoted, encapsulating material is encapsulated, is solid
After the completion of change, in the plastic packaging layer 5 of solid-like, the effects of waterproof, moisture-proof, shockproof, dust-proof, insulation can be played, radiated.
Further, in the present embodiment, the shielding space 5 is preferably two, the core being arranged in each shielding space 5
Piece 6 is one, also, the conductive silver paste or tin coated on the positive pad 7 of PCB substrate 4 described in the underrun of the chip 6
Cream is realized with the PCB substrate 4 and connects and communicated.
Further, it is additionally provided with package the tin ball 3 between the PCB substrate 4 and pinboard 1 and fills the shielding
The filling glue-line 8 in space 5, and the material of the filling glue-line 8 can be identical as the material of the Underfill layer 10, certainly
It can also be different, in the present embodiment preferably, their material is identical.
Due to the structure proximate of 2.5D integration packaging semiconductor device structure of the invention and 2.5 conventional packaging technologies,
Principle is identical, therefore can effectively maintain in conventional 2.5 packaging technologies that fine wiring integrated level is high, low in energy consumption, stress is low, one
The capacity and aspect of performance for encapsulating semiconductor devices obtain huge significantly promotion and the advantage with preferable yield.
Simultaneously as the top surface of the silicon substrate pinboard is provided with back layer gold 1, at this point, the top of the shielding space 5
(back layer gold), surrounding (tin ball), bottom surface (metal circuitry of 4 top surface of PCB substrate) are metal material, although depositing between tin ball
Certain gap, but gap is smaller, thus the chip 6 is equivalent to that be in an approximation closed and by metal boundary shape
At space in, along with there are also filling glue-lines 8 between silicon substrate pinboard and PCB substrate 4, so chip 6 and shielding space 5
Outer electromagnetic interference and electrostatic realizes isolation to a certain extent, so that the electromagnetic interference and electrostatic impact that are subject to chip 6 are big
It is big to reduce, improve electromagnetism interference and antistatic impact capacity.
Present invention further teaches a kind of processing methods for above-mentioned 2.5D integration packaging semiconductor devices, as attached drawing 3- is attached
Shown in Fig. 8, specific process is as follows:
S1 carries on the back layer gold procedure of processing: passing through magnetron sputtering, PVD(physical vapour deposition (PVD)), CVD (chemical vapor deposition),
The techniques such as vacuum evaporation, plating, chemical plating form back layer gold 2 in the top surface of pinboard 1, as shown in Fig. 3.
Flip-chip step: S2 as shown in Fig. 4, by reverse installation process, makes the chip 6 of specified quantity and the switching
The bottom surface circuit layer of plate 1 connects and realizes that they are communicated；By taking the structure of above-mentioned preferred 2 chips as an example, the S2, chip is fallen
It is as follows to fill step detailed step:
S21, respectively in the dimpling block 9 of the designated position of the electrode layer surface of two chips 6 production setting quantity；
S22 makes two chips 6 be inverted in the switching by the dimpling block 9 then by welding (Reflow Soldering) technology
On the bottom surface of plate 1, and realize the communication of two chips 6 and pinboard 1；
S23 fills high-heat-conductivity glue body between each chip 6 and pinboard 1 and forms the bottom for covering the dimpling block 9
Portion's filled layer 10, to complete the upside-down mounting of chip 6.
Except of course that above-mentioned reverse installation process, also can be used other feasible reverse installation process
S3, pinboard plant ball step: as shown in Fig. 5, by BGA plant playing skill art the bottom surface of the pinboard 1 according to
Specified layout form makes a number of tin ball 3, and must assure that the height of the tin ball 3 is greater than the height of the dimpling block 9
The height of degree+chip 6；The layout type of the tin ball 3 is preferably as shown in Fig. 6, they enclose 8 word display tube of an approximation
Shape, and two chips 6 are located at the region of two blank of the 8 word display tube.
The connection step of S4, chip and PCB substrate: it as shown in Fig. 7, is applied on the pad 7 of the PCB substrate 4 conductive
Silver paste or tin cream or the good substance of other thermal conductivities realize the conducting of PCB substrate 4 and chip 6 by pad 7.
The connection step of S5, pinboard and PCB substrate: then, the pinboard of tetra- steps of above-mentioned S1-S4 will be completed
On 1 Surface Mount to the PCB substrate 4, and realize the connection of the pinboard 1 and PCB substrate 4, Surface Mount technology is known work herein
Skill, details are not described herein.
S6, filler step: as shown in Fig. 8, filling the gap between the pinboard 1 and PCB substrate 4 with filling glue,
And make the tin ball 3 for filling glue covering periphery, it completes to rectify and improve the processing of 2.5D integration packaging semiconductor devices.
Certainly the sequence of above-mentioned step number S1, S2, S3, S4, S5, S6 do not cause unique restriction to this method,
For example, in other embodiments, the S1, back layer gold procedure of processing can carry out again after the completion of any other step；Or
The S2, flip-chip step and the S3, the sequence that pinboard plants ball step can overturn.
Still there are many embodiment, all technical sides formed using equivalents or equivalent transformation by the present invention
Case is within the scope of the present invention.
Claims (11)
1. a kind of 2.5D integration packaging semiconductor devices, it is characterised in that: including pinboard (1), the top surface of the pinboard (1)
On be provided with back layer gold (2), several tin balls (3) of the underrun of the pinboard (1) and PCB substrate (4) connection communication, and it
Cooperatively form the semiclosed shielding space (5) of specified quantity, be provided at least one upside-down mounting in each shielding space (5)
Chip (6) in the pinboard (1) bottom surface, the bottom surface of the chip (6) connect logical with the pad (7) on PCB substrate (4)
Letter is provided with package the tin ball (3) and fills the shielding space (5) between the PCB substrate (4) and pinboard (1)
It fills glue-line (8).
2. a kind of 2.5D integration packaging semiconductor devices according to claim 1, it is characterised in that: the pinboard (1)
For silicon substrate pinboard.
3. a kind of 2.5D integration packaging semiconductor devices according to claim 2, it is characterised in that: the back layer gold (2)
Area and shape it is identical as the area of the pinboard (1) top surface and shape.
4. a kind of 2.5D integration packaging semiconductor devices according to claim 3, it is characterised in that: the back layer gold (2)
It is the combination layer of Pt metal layer or Ni layers or Cr layers or W layers or Au layers or AL layers or Cu layers or the above metal.
5. a kind of 2.5D integration packaging semiconductor devices according to claim 3, it is characterised in that: the tin ball (3)
Height is 0.15mm-0.35mm.
6. a kind of 2.5D integration packaging semiconductor devices according to claim 3, it is characterised in that: the shielding space
(5) it is two, is provided with a chip (6) in each shielding space (5).
7. a kind of 2.5D integration packaging semiconductor devices according to claim 3, it is characterised in that: the chip (6) is logical
It crosses several dimpling blocks (9) positioned at the pinboard (1) bottom to connect and communicate with the pinboard (1), the dimpling block (9)
It is coated in the Underfill layer (10) between pinboard (1) bottom and chip (6).
8. a kind of 2.5D integration packaging semiconductor devices according to claim 7, it is characterised in that: the dimpling block (9)
For gold goal or tin ball.
9. -8 any a kind of 2.5D integration packaging semiconductor devices according to claim 1, it is characterised in that: the pad
(7) conducting is connect with the bottom surface of the chip (6) by tin cream or conductive silver paste.
10. a kind of processing method of any 2.5D integration packaging semiconductor devices of claim 1-9, it is characterised in that:
Include the following steps,
S1 carries on the back layer gold procedure of processing: forming back layer gold (2) in the top surface of pinboard (1)；
Flip-chip step: S2 by reverse installation process, makes the chip (6) of specified quantity and the bottom surface circuit of the pinboard (1)
Layer connects and realizes that they are communicated；
S3, pinboard plant ball step: planting playing skill art in the bottom surface of the pinboard (1) according to specified layout form system by BGA
Make a number of tin ball (3)；
The connection step of S4, chip and PCB substrate: applying conductive silver paste or tin cream on the pad (7) of the PCB substrate (4), and
Realize the connection of the chip (6) and PCB substrate (4)；
The connection step of S5, pinboard and PCB substrate: the pinboard (1) Surface Mount of aforementioned four step will be completed described in
In PCB substrate (4), and the connection of realization and the pinboard (1) and PCB substrate (4)；
Filler step: S6 fills the gap between the pinboard (1) and PCB substrate (4) with filling glue, and covers filling glue
Cover the tin ball (3) of periphery.
11. the processing method of 2.5D integration packaging semiconductor devices according to claim 10, it is characterised in that: described
S2, flip-chip step include the following steps:
S21, in the dimpling block (9) of the electrode layer surface production setting quantity of the chip (6)；
Chip (6) is inverted on the pinboard (1), described in realization by S22 by welding technique by the dimpling block (9)
The communication of chip (6) and pinboard (1)；
S23 fills high-heat-conductivity glue body between the chip (6) and pinboard (1) and forms the bottom for covering the dimpling block (9)
Filled layer (10).
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| CN108389838A (en) * | 2018-02-08 | 2018-08-10 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip-packaging structure and chip packaging method |
| CN109411375B (en) * | 2018-10-25 | 2020-09-15 | 中国科学院微电子研究所 | Packaging auxiliary device and packaging method |
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| CN112216659A (en) * | 2019-07-11 | 2021-01-12 | 中芯集成电路（宁波）有限公司 | Integrated structure, manufacturing method thereof, electronic device and image sensor module |
| CN111498791A (en) * | 2020-04-30 | 2020-08-07 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system packaging structure and manufacturing method thereof |
| CN112234027A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 2.5D electronic packaging structure |
| CN112234026A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 3D chip package |
| CN112382621A (en) * | 2020-11-09 | 2021-02-19 | 海光信息技术股份有限公司 | Multi-chip package module and method |
| WO2022236787A1 (en) * | 2021-05-13 | 2022-11-17 | 华为技术有限公司 | Chip packaging structure and packaging system |
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| US8710634B2 (en) * | 2009-03-25 | 2014-04-29 | Stats Chippac Ltd. | Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof |
| US8779562B2 (en) * | 2011-03-24 | 2014-07-15 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer shield and method of manufacture thereof |
| US8718550B2 (en) * | 2011-09-28 | 2014-05-06 | Broadcom Corporation | Interposer package structure for wireless communication element, thermal enhancement, and EMI shielding |
| CN103137609B (en) * | 2013-03-04 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | With the integrated circuit package structure of electromagnetic armouring structure |
| CN205609517U (en) * | 2016-05-19 | 2016-09-28 | 苏州捷研芯纳米科技有限公司 | 2. 5D integrated encapsulation semiconductor device |
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2016
- 2016-05-19 CN CN201610335717.0A patent/CN105870109B/en active Active
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