CN103296009B - With the shielding construction, 3D encapsulating structure and preparation method thereof of EBG - Google Patents
With the shielding construction, 3D encapsulating structure and preparation method thereof of EBG Download PDFInfo
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention provides a kind of shielding construction with EBG, 3D encapsulating structure and preparation method thereof, the described shielding construction with EBG comprises insulating barrier and at least two metal flats; Wherein, at least one metal flat etching has periodically EBG structure; Insulating barrier is provided with between described metal flat.Described preparation comprises with the method for EBG shielding construction and prepares at least one deck metal flat; Prepare intermediate insulating layer; Prepare at least one deck with the metal flat of periodicity EBG structure.Described a kind of 3D encapsulating structure, comprises shielding construction, bare chip, the interconnect substrate with EBG; Described bare chip is bonded on described interconnect substrate, and described bare chip is connected with described shielding construction.The preparation method that a kind of 3D encapsulates also is provided.The present invention effectively can reduce the near-field coupling problem between vertical 3D interconnect package chips.
Description
Technical field
The present invention relates to microelectronic packaging technology field, particularly one is with the shielding construction, 3D encapsulating structure and preparation method thereof of EBG (ElectromagneticBandGap, EBG).
Background technology
Along with the rise of communication electronics, people are more and more higher to miniaturized and high sensitivity module or system demand, also more and more stricter to the requirement of signal quality.High-density integration technology, develops rapidly as the technology such as system in package (System-in-Package, SiP) obtain, but the miniaturized integration packaging of mixed signal multichip system but one of technological difficulties becoming this field.
Digital signal frequency constantly rises, and rise/fall is along more and more trembling, and the impact of high fdrequency component on sensitive circuits such as simulation or radio frequency chips of digital signal is increasing.The sensitivity of general communication system is all at-100dBm, global positioning system (GlobalPositionSystem, GPS) sensitivity is even lower than-148dBm, the sensitivity requirement of some transceiver modules is also very high, a very important problem during electromagnetic compatibility (ElectromagneticInterfere, EMI) in mixed-signal system has become system compact to encapsulate.The noise disturbing chip to produce in microelectronics Packaging forms interference mainly through three approach to sensitive chip: one, the transient noise (SimultaneousSwitchingNoise, SSN) that causes of digital circuit high-speed switch is by substrate contribution sensitive circuit; Two, the capacitive couplings between chip and sensitive chip interconnection line and inductive couplings is disturbed; Three, disturb between chip and sensitive chip due to near-field coupling that 3D stack assembly causes.
Take system in package as the novel 3D encapsulation technology of representative, except three-dimensional chip stacking (StackedDiepackage), encapsulation stacking POP (PackageonPackage, etc. POP) outside technology, the encapsulation miniaturization that is applied as of some new materials and new technology brings opportunity, as flexible base, board, silicon through hole (ThroughSiliconVia, TSV) keyset technology and glass through hole (ThroughGlassVia, TGV) keyset technology become one of interconnected hot research direction of vertical 3D.The three-dimensional stacked middle sensitive chip of chip and interference chip directly stacking, constantly reduce for adapting to encapsulation miniature chip thickness, near-field coupling problem is very serious, and between vertical chip, in addition shielding construction reduces noise usually.In POP encapsulation sensitive chip and interference Chip Vertical interconnect distance comparatively far away, near-field coupling problem is not too serious, but vertical dimension under this packing forms is comparatively large, is unfavorable for that encapsulation is miniaturized.TSV, TGV keyset is thinner, and thickness only has hundreds of even tens microns, and after vertical interconnect, the near-field coupling problem of chip chamber is also very serious on the mixed-signal system impact that sensitivity is very high.
EBG structure is that a kind of periodically band gap suppresses structure, can regulate suppression frequency range by amount of cycles and cellular construction.Be usually used in antenna structure suppressing back lobe energy, improve antenna radiation efficiency.EBG structual shield cover is used in radio frequency (RadioFrequency, RF) transceiver and the integrated system of radio-frequency power amplifier by patent CN200910143507.1, and periodic structure reduces the electromagnetic interference under identical radome between chip.This structure is applied to system two dimension integrated technology, but not three-dimensional packaging technology.The EBG structure of encapsulation field applies the suppression aspect mainly concentrated on momentary switch noise (simultaneousswitchingnoise, SSN), also belongs to and suppresses the two dimension of noise.Usually for the noise suppressed between assembling chip two-dimentional in power source substrate distributed network (Powerdeliverynetwork, PDN), have in the patents such as US20070289771A1 and clearly set forth.In recent years, along with developing rapidly of TSV technology, become increasingly conspicuous based on the signal integrity of TSV and Power Integrity problem, some scholars, the people such as JounghoKim as KAIST starts EBG structure to be used for TSV keyset or LTCC (LowTemperatureCo-firedCeramic, in the PDN network of LTCC) keyset, be obviously also belong to suppress the two dimension of SSN noise.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of shielding construction with EBG (ElectromagneticBandGap, EBG), 3D encapsulating structure and preparation method thereof that effectively can reduce near-field coupling problem between vertical 3D interconnect package chips.
For solving the problems of the technologies described above, the invention provides a kind of shielding construction with EBG and comprising:
At least one insulating barrier and at least two metal flats;
Wherein, at least one metal flat etching has periodically EBG structure; An insulating barrier is provided with between two metal flats.
The present invention also provides a kind of shielding construction with EBG, comprises at least one insulating barrier and at least two metal flats; Wherein, each described insulator layer etch has periodically EBG structure, and is arranged between described two metal flats.
The present invention also provides a kind of method preparing shielding construction with EBG, comprising: prepare at least one deck metal flat by sputtering sedimentation, hydatogenesis, change plated deposition, lamination or electroplating deposition process on the surface in supporting bracket; Prepare at least one insulating barrier; On described insulating barrier, form at least layer of metal plane again with sputtering sedimentation, hydatogenesis, change plated deposition, electroplating deposition or laminating technology, and be etched into periodically EBG structure.
The present invention also provides a kind of method preparing shielding construction with EBG, is included in supporting bracket and prepares at least one deck metal flat by sputtering sedimentation, hydatogenesis, change plated deposition, lamination or electroplating deposition process on the surface; Prepare at least one insulating barrier, and etching cycle EBG structure on which insulating layer; At least layer of metal plane is formed again with sputtering sedimentation, hydatogenesis, change plated deposition, electroplating deposition or laminating technology on described insulating barrier.
The present invention also provides a kind of 3D encapsulating structure, comprises the shielding construction with EBG, also comprises bare chip, interconnect substrate; Described bare chip is bonded on described interconnect substrate, and described bare chip is connected with described shielding construction.
The present invention also provides a kind of method preparing 3D encapsulating structure, comprises processing interconnect substrate; 3D encapsulates, the fixing and bonding of lower layer chip; Shielding construction is fixed and is connected; 3D encapsulates, the fixing and bonding of upper strata chip.
Provided by the invention with EBG (ElectromagneticBandGap, EBG) shielding construction, make full use of the band-stop response of EBG structure, with a kind of efficiently, easily method realize the near-field coupling between three-dimensional stacked chip, especially very effective to the near-field coupling inhibition being applied to medium, high frequency package system; Periodic unit structure and amount of cycles by optimizing EBG structure suppress the noise of different frequency range.EBG concrete structure can not be affected, therefore by precalculating the shield effectiveness accurately estimating described shielding construction owing to encapsulating interconnect architecture in preparation process.
Accompanying drawing explanation
Fig. 1 be first embodiment of the invention based on 3D encapsulation with the profile of the shielding construction of EBG;
Fig. 2 be second embodiment of the invention based on 3D encapsulation with the profile of the shielding construction of EBG.
Fig. 3 is the schematic diagram of mushroom-shaped EBG shielding construction;
Fig. 4 is the schematic diagram of coplanar EBG shielding construction;
Fig. 5 is the schematic diagram of photonic crystal power/ground planes EBG shielding construction;
The shield effectiveness curve chart that Fig. 6 is shielding construction shown in Fig. 2.
Embodiment
A kind of shielding construction with EBG that the embodiment of the present invention provides, comprises insulating barrier and at least two metal flats; Wherein, at least one metal flat etching has periodically EBG structure; Insulating barrier is provided with between described metal flat.Be provided with at least one deck etching above and/or under insulating barrier and have the metal flat of periodically EBG structure.In one example, as shown in Figure 3, be provided with second layer metal plane on the insulating layer and etching has periodic structure third layer metal flat, wherein, by second layer metal plane, and utilize mode such as metallization via hole, RDL etc. to be connected with third layer metal flat, thus form mushroom-shaped EBG shielding construction with first layer metal plane together with insulating barrier.In another example, as shown in Figure 4, have the metal flat of periodically EBG structure when insulating barrier being provided with one deck etching, insulating barrier be arranged with layer of metal plane, form plane EBG shielding construction thus.
A kind of shielding construction with EBG that the embodiment of the present invention provides, comprises at least one insulating barrier and at least two metal flats; Wherein, each described insulator layer etch has periodically EBG structure, and is arranged between described two metal flats.As shown in Figure 5, between metal flat 1, metal flat 2, be provided with the insulating barrier 3 having periodically EBG structure containing etching, form photonic crystal power/ground planes EBG shielding construction thus.
Below in conjunction with the embodiment shown in Fig. 1, Fig. 2, the shielding construction with EBG provided by the invention, 3D encapsulating structure and preparation method thereof are described in detail.
Embodiment one
In 3D encapsulating structure as shown in Figure 1, bare chip 109 and 110 adopts flip chip bonding mode to be bonded on interconnect substrate 112, and fills underfill for the protection of flip-chip bump 111.Individually shielded device 103 with EBG structure utilizes adhesive to be fixed on bare chip 109 and 110.Shielding device 103 comprises supporting bracket 107, etching has the first metal flat 106 of periodically EBG structure, insulating barrier 105 and the second metal flat 104, wherein, the periodically cell configuration of EBG structure, the quantity noise frequency range that even malformation suppresses as required determines.Supporting bracket can be silica-based or the multiple base material such as glass-based, organic substrate, even ceramic substrate.The insulating material of respective insulation layers 105 can be SiO
2, Si
3ni
4, the multiple material such as organic material substrate or ceramic material.Bare chip 101 utilizes adhesive to be fixed on shielding device 103, and adopts wire bonding mode to be bonded on interconnect substrate 112, and bonding line 102 is gold thread, the various material such as copper cash or aluminum steel.The casting glues 108 such as plastic packaging glue are filled between the stacking bare chip of 3D 101,109,110 and shielding device 103, play the fixing effect being shaped and protecting bare chip.The soldered ball 113 of ball grid array is for the electrical connection between interconnect substrate and printed circuit board.
Be described the preparation method of shielding device in Fig. 1 103 below, this preparation method comprises the following steps:
Step 10: prepare the first metal flat.
Layer of metal plane is deposited by processes such as sputtering sedimentation, hydatogenesis, change plated deposition, lamination, electroplating depositions on the surface in the supporting bracket of different materials.Wherein supporting plate material can be silicon, glass, organic substrate, ceramic substrate etc.
Step 20: prepare intermediate insulating layer.
When adopting silica-based or glass substrate as supporting bracket, with process deposits one deck SiO such as physical vapour deposition (PVD)s (PhysicalVaporDeposition, PVD)
2or Si
3ni
4deng film, or make one deck organic film as insulating barrier by the technique such as spin coating or spraying; When adopting organic substrate as supporting bracket, the method for pressing organic board is adopted to form insulating barrier; Insulating barrier is formed with sintering process in metal surface when adopting ceramic substrate to make supporting bracket;
Step 30: preparation second is with the metal flat of periodic structure.
In one embodiment, layer of metal plane is formed again by techniques such as sputtering sedimentation, hydatogenesis, change plated deposition, electroplating deposition or laminations on insulating barrier, and be etched into periodic structure, form plane EBG shielding construction with the first metal flat together with intermediate insulating layer.
In another embodiment, sputtering sedimentation, hydatogenesis, change plated deposition, lamination or electroplating deposition is adopted to form the second metal flat and the 3rd metal flat on the insulating layer.Second metal flat is etched into periodic structure, and utilizes mode such as metallization via hole, RDL etc. to be connected with the 3rd metal flat, form mushroom-shaped EBG shielding construction with the first metal flat together with insulating barrier.
Step 10 to step 30 is step of preparation process of the shielding device with one deck periodicity EBG structure, also can by repeating step 10 to step 30, make the shielding device with EBG periodic structure of multilayer on the supporting plate, or make at the upper and lower surface of supporting bracket the EBG structure that one or more layers has periodic distribution respectively.
Embodiment two
In 3D encapsulating structure as shown in Figure 2, bare chip 209 adopts wire bonding mode to be bonded on interconnect substrate 212.Individually shielded device 214 with EBG structure utilizes adhesive to be fixed on bare chip 209, and described shielding device 214 adopts flexible base, board to prepare, and comprises the first metal flat 217, and insulating barrier 216 and etching have the second metal flat 215 of periodic structure.Wherein, the cell configuration of periodic structure, the quantity noise frequency range that even malformation suppresses as required determines.Bare chip 201 utilizes adhesive to be fixed on shielding device 214, and adopts wire bonding mode to be bonded on interconnect substrate 212, and bonding line 202 is gold thread, the various material such as copper cash or aluminum steel.The casting glues 208 such as plastic packaging glue are filled between the stacking bare chip of 3D 201,209 and shielding device 214, play the fixing effect being shaped and protecting bare chip.The soldered ball 213 of ball grid array is for the electrical connection between interconnect substrate and printed circuit board.
The material of above metal flat is copper, gold or aluminium etc., preferably copper.
Below in conjunction with Fig. 6, the shield effectiveness of shielding construction in the 3D encapsulating structure shown in Fig. 2 is described.S21 simulation curve between below 40GHz frequency range bare chip 201 and 209.Solid line 418 shows the S21 curve based on not having in the second embodiment under shielding construction 214; Short-term 419 shows the S21 curve replaced with based on shielding construction 214 in the second embodiment under traditional screen shield structure, and namely traditional screen shield structure adopts complete metal plane to shield electromagnetic noise; Dotted line 420 shows based on the S21 curve under shielding construction 214 in the second embodiment.Based on the second embodiment, the S21 curve in comparison diagram 6 under different structure can draw to draw a conclusion: do not adopt the near-field coupling between the 3D stacked chips of any shielding construction very serious, the especially more difficult suppression of medium, high frequency noise.Conventional planar shielding construction and all have good shield effectiveness with the Novel shielding structure of EBG.But compare traditional screen shield structure, the Novel shielding structure with EBG has better shield effectiveness for medium, high frequency band noise.Due to the band-stop response of EBG structure and periodic unit structure and amount of cycles closely related, effective suppression to different noise frequency range can be reached by optimizing EBG structure, applying more flexible.
Be introduced the processing step that shielding device is applied in when actual 3D encapsulates below, it comprises the following steps:
Step one: use etching, lamination, machinery/technique such as laser drill or plating to process substrate, thus form interconnect substrate.
Step 2: 3D encapsulates, the fixing and bonding of lower layer chip.
When described chip is bare chip, and when adopting the form of flip chip bonding to interconnect between bare chip and interconnect substrate, adopt reflow soldering process bare chip is fixed on described interconnect substrate by flip-chip bump, and around described flip-chip bump filling underfill to protect flip-chip bump;
When described chip is bare chip, and when adopting the form of wire bonding to interconnect between described bare chip and interconnect substrate, use binding agent to fit on interconnect substrate by bare chip, adopt lead key closing process to be connected between bare chip and interconnect substrate by wire bonding line;
When described chip is packaged chip, reflow soldering process is adopted to be fixed on described interconnect substrate by packaged chip.
Step 3: shielding construction is fixed and is connected.
When described shielding construction is as individually shielded device, in spraying one deck insulation colloid of the upper surface of the chip of above-mentioned installation, then independent shielding device is mounted the surface of chip.When shielding device needs with when being systematically connected, can adopt micro convex point, solder ball, the various ways such as wire bonding line make the layer of metal plane in shielding construction be connected with the ground level in interconnect substrate.Shielding device effectively can isolate the crosstalk between upper and lower stacked chips, plays shielding action.
Step 4: 3D encapsulates, the fixing and bonding of upper strata chip.
When described chip is bare chip, and when adopting the form of flip chip bonding to interconnect between described bare chip and interconnect substrate, adopt reflow soldering process bare chip is fixed on described interconnect substrate by flip-chip bump, and around described flip-chip bump filling underfill to protect flip-chip bump;
When described chip is bare chip, and when adopting the form of wire bonding to interconnect between described bare chip and interconnect substrate, use binding agent to fit on interconnect substrate by bare chip, adopt lead key closing process to be connected between bare chip and interconnect substrate by wire bonding line;
When described chip is packaged chip, reflow soldering process is adopted to be fixed on described interconnect substrate by packaged chip;
Step 5: according to actual package requirement, employing plastic packaging, mode such as some glue, lower filler etc. are protected 3D stacked chips.
Step 6: packaging pin is fixing and interconnected.Be fixed on by packaging pin on interconnect substrate, the modes such as use Reflow Soldering, wave-soldering or Mechanical Contact realize the electrical connection between described interconnect substrate and printed circuit board.Described packaging pin is the hard contact etc. of the soldered ball of ball grid array, the needle-like pin of pin array or planar lattice array.
Of the present invention have following beneficial effect:
1, provided by the invention based on the shielding construction of 3D encapsulation with EBG, make full use of the band-stop response of EBG structure, with a kind of efficiently, easily method realize the near-field coupling between three-dimensional stacked chip, especially very effective to the near-field coupling inhibition being applied to medium, high frequency package system;
2, provided by the invention based on the shielding construction of 3D encapsulation with EBG, periodic unit structure and amount of cycles by optimizing EBG structure suppress the noise of different frequency range.EBG concrete structure can not be affected, therefore by precalculating the shield effectiveness accurately estimating described shielding construction owing to encapsulating interconnect architecture in preparation process;
3, provided by the invention based on the shielding construction of 3D encapsulation with EBG, the chip in shielding construction can be any packaged type;
4, provided by the invention based on 3D encapsulation with the shielding construction of EBG, independent shielding device can be formed, be convenient to flexible Application;
5, provided by the invention based on the shielding construction of 3D encapsulation with EBG, except effectively suppressing stacked chips near-field coupling, also in conjunction with package system power distribution network, the near field shielding between power supply noise and two-dimentional chip can be reduced, realizes the comprehensive electromagnetic shielding to internal system noise;
6, provided by the invention based on the shielding construction of 3D encapsulation with EBG, can apply multiple processing technology and base material, the manufacturing process used is mature on the whole, and is conducive to the miniaturization of package system.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to example to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (1)
1. prepare a method for 3D encapsulating structure, it is characterized in that,
Described 3D encapsulating structure comprises the shielding construction with EBG; Also comprise:
First bare chip, interconnect substrate;
Described first bare chip is bonded on described interconnect substrate, and described first bare chip is connected with described shielding construction;
The described shielding construction with EBG comprises:
At least one insulating barrier and at least two metal flats;
Wherein, at least one metal flat etching has periodically EBG structure; An insulating barrier is provided with between two metal flats;
The method of the described 3D of preparation encapsulating structure comprises:
Processing interconnect substrate;
3D encapsulates, the fixing and bonding of lower layer chip;
Shielding construction is fixed and is connected;
3D encapsulates, the fixing and bonding of upper strata chip;
Described 3D encapsulation, the fixing and bonding of lower layer chip comprises:
When described lower layer chip is bare chip, and when adopting the form of flip chip bonding to interconnect between described lower layer chip and interconnect substrate, adopt reflow soldering process described lower layer chip is fixed on described interconnect substrate by flip-chip bump, and around described flip-chip bump filling underfill to protect flip-chip bump;
When described lower layer chip is bare chip, and when adopting the form of wire bonding to interconnect between described lower layer chip and interconnect substrate, use binding agent to fit on interconnect substrate by described lower layer chip, adopt lead key closing process to be connected between described lower layer chip and interconnect substrate by wire bonding line;
When described lower layer chip is packaged chip, reflow soldering process is adopted to be fixed on described interconnect substrate by packaged chip;
Described shielding construction is fixing to be comprised with being connected:
Spray one deck insulation colloid at the upper surface of the lower layer chip of above-mentioned installation, then independent described shielding construction is mounted the surface of chip;
When described shielding construction needs to be connected to the ground, adopt micro convex point, solder ball or wire bonding line mode make the layer of metal plane in shielding construction be connected with the ground level in interconnect substrate;
Described 3D encapsulation, the fixing and bonding of upper strata chip comprises:
When described upper strata chip is bare chip, and when adopting the form of flip chip bonding to interconnect between described upper strata chip and interconnect substrate, adopt reflow soldering process described upper strata chip is fixed on described interconnect substrate by flip-chip bump, and around described flip-chip bump filling underfill to protect flip-chip bump;
When described upper strata chip is bare chip, and when adopting the form of wire bonding to interconnect between described upper strata chip and interconnect substrate, use binding agent to fit on interconnect substrate by described upper strata chip, adopt lead key closing process to be connected between described upper strata chip and interconnect substrate by wire bonding line;
When described upper strata chip is packaged chip, reflow soldering process is adopted to be fixed on described interconnect substrate by packaged chip.
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| US10049953B2 (en) | 2015-09-21 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors |
| US9917072B2 (en) | 2015-09-21 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process |
| CN106373973B (en) * | 2016-11-24 | 2019-11-05 | 江苏骏龙光电科技股份有限公司 | A kind of anti-interference imaging sensor |
| CN110565058B (en) * | 2019-08-29 | 2021-07-27 | 江苏长电科技股份有限公司 | Magnetron sputtering method of BGA product |
| CN111863776B (en) * | 2020-07-30 | 2022-09-20 | 中山大学 | Low-noise double-sided integrated injectable biological photoelectric electrode microprobe and preparation method thereof |
| CN111863777B (en) * | 2020-07-30 | 2022-05-31 | 中山大学 | Low-noise single-sided integrated injectable biological photoelectric electrode microprobe and preparation method thereof |
| CN112187310B (en) * | 2020-09-07 | 2022-03-22 | 南京航空航天大学 | Novel millimeter wave front end module based on EBG encapsulation and LTCC circuit |
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| TW200814871A (en) * | 2006-09-01 | 2008-03-16 | Univ Nat Taiwan | Substrate for high-speed circuit |
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