CN111653552B - Square flat chip packaging structure with high electromagnetic pulse interference resistance - Google Patents
Square flat chip packaging structure with high electromagnetic pulse interference resistance Download PDFInfo
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- CN111653552B CN111653552B CN202010549022.9A CN202010549022A CN111653552B CN 111653552 B CN111653552 B CN 111653552B CN 202010549022 A CN202010549022 A CN 202010549022A CN 111653552 B CN111653552 B CN 111653552B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a square flat chip packaging structure with high anti-electromagnetic pulse interference capability, which comprises: the packaging structure comprises a bare chip and a packaging part, wherein the bare chip comprises a bare chip main body, a shielding structure and a plurality of first pins are arranged on the bare chip main body, and the first pins are connected with the shielding structure; the package comprises a lead frame body and a first bonding pad, wherein the bare chip body is arranged on the lead frame body, and the first bonding pad is connected with the lead frame body; the first pin is connected with the first bonding pad through a first bonding wire. According to the square flat chip packaging structure, the shielding structure is formed on the upper surface of the bare chip main body, the first pin connected with the shielding structure is connected with the first bonding pad in a bonding mode through the bonding wire, the shielding shell wrapping the bare chip main body is formed, and the electromagnetic pulse interference resistance can be achieved without developing a special shielding shell.
Description
Technical Field
The invention belongs to the technical field of electromagnetic pulse protection, and particularly relates to a square flat chip packaging structure with high electromagnetic pulse interference resistance.
Background
The package is a package for mounting a semiconductor integrated circuit chip, which not only plays a role of mounting, fixing, sealing, protecting the chip and enhancing the heat conduction performance, but also is a bridge for communicating the internal world of the chip with an external circuit, i.e., the connection points on the chip are connected to the pins of the package by wires, and the pins are connected with other devices by wires on the printed circuit board. QFP (Quad Flat Package) is a new type of Package developed specifically for small pin pitch surface mount IC chips (Integrated Circuit chips). QFPs are package formats that have been developed to accommodate the increase in IC chip capacity and the increase in the number of I/os, and are now widely used.
With the development of microelectronic technology, semiconductor integrated circuits have been widely used in many important fields such as communication, traffic, energy, military, national defense, and the like. However, the inevitable co-operation of a large number of electronic devices leads to the problem of electromagnetic compatibility, and especially for semiconductor devices with ever-increasing integration, microwave interference and flip-flop effects become increasingly serious. Various external electromagnetic interferences can be input into an electronic system through various coupling ways, so that the problems of computer errors, equipment restart, instrument crash and the like are caused, some electronic devices can be permanently failed in severe cases, the faults can cause great damage to the electronic system, and great inconvenience is brought to the life of people. High power microwaves, as a new source of electromagnetic interference, are attracting much attention, and the electromagnetic radiation thereof interferes with and destroys electronic systems and facilities, possibly resulting in circuit failure and system breakdown. Therefore, how to improve the capability of the integrated circuit against electromagnetic interference, especially the interference of the digital circuit caused by high-power microwave electromagnetic radiation, becomes an urgent problem to be solved.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a quad flat chip package structure with high electromagnetic pulse interference resistance. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a square flat chip packaging structure with high anti-electromagnetic pulse interference capability, which comprises: a bare chip and a package, wherein,
the bare chip comprises a bare chip main body, wherein a shielding structure and a plurality of first pins are arranged on the bare chip main body, and the first pins are connected with the shielding structure;
the package comprises a lead frame main body and a first bonding pad, wherein the bare chip main body is installed on the lead frame main body, and the first bonding pad is connected with the lead frame main body;
the first pin is connected with the first bonding pad through a first bonding wire.
In one embodiment of the invention, the die includes a plurality of second pins, the second pins and the first pins being spaced apart from each other on the die body.
In one embodiment of the invention, the package includes a chip pin and a second pad connected to the second pin by a second bonding wire.
In one embodiment of the invention, the package further includes a package housing for hermetically protecting the bare chip, and the lower surface of the lead frame body is located outside the package housing.
In one embodiment of the invention, the shielding structure is a metal mesh structure.
In one embodiment of the present invention, the mesh size of the metal mesh structure is less than or equal to 1/10 of the wavelength of the electromagnetic wave to be shielded.
In an embodiment of the invention, a mesh width of the metal mesh structure is smaller than or equal to a width of the first pin.
In an embodiment of the invention, the thickness of the shielding structure is greater than or equal to the skin depth of the electromagnetic wave to be shielded in the top layer material of the bare chip main body.
In an embodiment of the invention, a distance between adjacent first pins is less than or equal to 1/10 of the wavelength of the electromagnetic wave to be shielded.
In an embodiment of the present invention, a distance between the bonding point of the first lead and the bonding point of the first pad is less than or equal to 1/10 of the wavelength of the electromagnetic wave to be shielded.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the square flat chip packaging structure with high anti-electromagnetic pulse interference capability, the shielding structure is formed on the upper surface of the bare chip main body, the first pin connected with the shielding structure is connected with the first bonding pad in a bonding mode through the bonding wire, the shielding shell wrapping the bare chip main body is formed, and anti-electromagnetic pulse interference can be achieved without developing a special shielding shell;
2. according to the square flat chip packaging structure with high anti-electromagnetic pulse interference capability, in the installation and use process, the lower surface of the lead frame main body and the metal bonding pad grounded on the upper surface of the PCB are effectively electrically connected, so that the anti-electromagnetic pulse interference capability of a device can be improved;
3. the square flat chip packaging structure with high electromagnetic pulse interference resistance is simple in structure, easy to process in batches, convenient to use and good in engineering application feasibility.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a quad flat chip package structure with high electromagnetic pulse interference resistance according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an upper surface of a die according to an embodiment of the invention;
FIG. 3 is a top view of a package (excluding chip pins and a package housing) provided by an embodiment of the invention;
FIG. 4 is a bottom schematic view of a package provided by an embodiment of the present invention;
fig. 5 is a schematic mounting diagram of a quad flat chip package structure according to an embodiment of the present invention.
Description of the reference numerals
100-bare chip; 101-a bare chip body; 102-a shielding structure; 103-a first pin; 104-a second pin; 200-a package; 201-a lead frame body; 202-a first pad; 203-second bonding pad; 204-chip pin; 205-an encapsulating housing; 300-a first bond wire; 400-a second bond wire; 500-PCB board.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a quad flat chip package structure with high electromagnetic pulse interference resistance according to the present invention will be described in detail with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Referring to fig. 1-4, fig. 1 is a schematic diagram of a quad flat chip package structure with high electromagnetic pulse interference resistance according to an embodiment of the present invention; fig. 2 is a schematic diagram of an upper surface of a die according to an embodiment of the invention; FIG. 3 is a top view of a package (excluding chip pins and a package housing) provided by an embodiment of the invention; fig. 4 is a bottom schematic view of a package provided by an embodiment of the invention. As shown in the figure, the square flat chip package structure with high electromagnetic pulse interference resistance of the embodiment of the present invention includes a bare chip 100 and a package 200, where the bare chip 100 includes a bare chip main body 101, a shielding structure 102 and a plurality of first pins 103 are disposed on the bare chip main body 101, and the plurality of first pins 103 are all connected to the shielding structure 102; the package 200 includes a lead frame body 201 and a first pad 202, the bare chip body 101 is mounted on the lead frame body 201, and the first pad 202 is connected to the lead frame body 201; the first lead 103 is connected to the first pad 202 through a first bonding wire 300.
Specifically, the shielding structure 102 is a metal mesh structure, wherein a mesh size L1 of the metal mesh structure is smaller than or equal to 1/10 of a wavelength of an electromagnetic wave to be shielded, and a mesh width L2 of the metal mesh structure is smaller than or equal to a width L3 of the first lead 103. It should be noted that the shielding structure 102 of the present embodiment can be manufactured by using a top metal process of the die main body 101, and preferably, the thickness of the shielding structure 102 is greater than or equal to the skin depth of the electromagnetic wave to be shielded in the top material of the die main body 101. When there is an alternating current or an alternating electromagnetic field in the conductor, the current distribution inside the conductor is not uniform, and the current is concentrated in the "skin" part of the conductor, that is to say the current is concentrated in the thin layer on the outside of the conductor, a phenomenon known as the skin effect. The skin effect increases the effective resistance of the conductor, the higher the frequency, the more pronounced the skin effect, and when a current with a high frequency passes through the wire, it can be considered that the current flows only in a thin layer on the surface of the wire, and the thickness of the portion of the wire is called the skin depth.
Further, preferably, the distance between the adjacent first pins 103 is less than or equal to 1/10 of the wavelength of the electromagnetic wave to be shielded; the distance between the bonding point of the first lead 103 and the bonding point of the first pad 202 is less than or equal to 1/10 of the wavelength of the electromagnetic wave to be shielded and is greater than the minimum bonding pitch of the bonding equipment. The first pin 103 employs a pin having a large driving capability (i.e., having a large current output) in an I/O (input/output) bank. It should be noted that the minimum bonding pitch of the bonding apparatus is a basic parameter of the bonding apparatus, and the minimum bonding pitches of different models of bonding apparatuses are different.
In this embodiment, the first lead 103 is used as a lead of the shielding structure 102, the first pad 202 is used as a shielding pad, the first lead 103 and the first pad 202 are connected by the first bonding wire 300, and a shielding case wrapping the bare chip main body 101 is formed on the surface of the bare chip main body 101, so as to achieve electromagnetic pulse interference resistance.
The principle that the square flat chip packaging structure of the embodiment has anti-electromagnetic pulse interference is as follows: the shielding case for the bare chip body 101 formed in this embodiment is similar to a Faraday cage, which can achieve electrostatic shielding, a Faraday cage (Faraday cage) is a metal housing that prevents electromagnetic fields (EM field) from entering or escaping, and an ideal Faraday cage is composed of an unbroken, perfect conductive layer, which is not achieved in practice, but can be achieved by using a fine mesh copper screen. The shielding case wrapped outside the bare chip main body 101 of the embodiment plays a role in protecting the bare chip main body 101, so that the bare chip main body is not affected by an external electric field to form electrostatic shielding, and the square flat chip packaging structure of the embodiment has anti-electromagnetic pulse interference capability.
The square flat chip packaging structure with high electromagnetic pulse interference resistance of the embodiment forms the shielding structure 102 on the upper surface of the bare chip main body 101 by utilizing the processing of the top layer metal of the square flat chip packaging structure, the first lead 103 connected with the shielding structure 102 is connected with the first bonding pad 202 in a bonding mode through the first bonding wire 300, a shielding shell wrapping the bare chip main body 101 is formed, a special shielding shell does not need to be developed, the electromagnetic pulse interference resistance can be realized, the structure is simple, the batch processing is easy, the use is convenient, and the engineering application feasibility is better.
Further, the die 100 further includes a plurality of second pins 104, the second pins 104 and the first pins 103 are disposed on the die body 101 at intervals, as shown in fig. 2, in this embodiment, the second pins 104 are normal functional pins of the die body 101, and are normal signal and power terminals of the die body 101. It should be noted that, in other embodiments, a plurality of second leads 104 may be disposed between adjacent first leads 103, and the specific number may be determined according to the distance between adjacent first leads 103, which is not limited herein.
Further, as shown in fig. 3 and 4, the package 200 further includes a second pad 203, a chip pin 204, and a package housing 205, wherein the second pad 203 is connected to the chip pin 204, and the second lead 104 is connected to the second pad 203 through a second bonding wire 400. In this embodiment, the second pad 203 is a normal function pad of the bare chip main body 101, and is a signal and power supply terminal which is normal when the bare chip main body 101 is packaged, the second pad 203 and the chip pin 204 are bonded by a wire, and the chip pin 204 is used for external electrical connection of the bare chip main body 101. The package housing 205 is used for protecting the bare chip 100, wherein the bare chip 100, the lead frame body 201, the first pad 202, the second pad 203, the first bonding wire 300, the second bonding wire 400, and the connection portion between the chip pin 204 and the second pad 203 are all located inside the package housing 205. As shown in fig. 4, the bottom of the package housing 205 is hollowed out, and the lower surface of the lead frame body 201 is located outside the package housing 205.
When the square flat chip packaging structure with high electromagnetic pulse interference resistance of the embodiment of the invention is used as an electronic component, the square flat chip packaging structure is usually required to be installed on a Printed Circuit Board (PCB), and the PCB is used as a support body of the electronic component and is a carrier for forming electrical connection among various electronic components. Referring to fig. 5, fig. 5 is a schematic mounting diagram of a quad flat chip package structure according to an embodiment of the invention. As shown in the figure, when the quad flat chip package structure of this embodiment is mounted and used, a metal pad is disposed at a mounting position on the PCB 500, the size of the metal pad is as large as the lower surface of the lead frame body 201 exposed out of the package housing 205, and the metal pad is connected to the ground mesh. It should be noted that during the mounting process, it is necessary to ensure that the lower surface of the lead frame body 201 exposed out of the package shell 205 and the metal pad on the PCB 500 form an effective electrical connection, for example, bonding with a conductive adhesive.
In the square flat chip packaging structure with high anti-electromagnetic pulse interference capability of the embodiment of the invention, in the installation and use process, the lower surface of the lead frame main body 201 and the metal bonding pad on the upper surface of the PCB board 500 are effectively electrically connected, the metal bonding pad on the upper surface of the PCB board 500 is connected to the ground, that is, the shielding shell which is formed by connecting the shielding structure 102 and the first bonding pad 202 and wraps the bare chip main body 101 is connected to the ground, so that the anti-electromagnetic pulse interference capability of the device is improved.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "plurality" or "a plurality" means two or more unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. A square flat chip packaging structure with high electromagnetic pulse interference resistance is characterized by comprising: a bare chip (100) and a package (200), wherein,
the bare chip (100) comprises a bare chip main body (101), wherein a shielding structure (102) and a plurality of first pins (103) are arranged on the bare chip main body (101), and the plurality of first pins (103) are all connected with the shielding structure (102);
the package (200) includes a lead frame body (201) and a first pad (202), the bare chip body (101) is mounted on the lead frame body (201), and the first pad (202) is connected to the lead frame body (201);
the first pin (103) is connected with the first pad (202) through a first bonding wire (300), the first pin (103) is used as a pin of the shielding structure (102), the first pad (202) is used as a shielding pad, the first pin (103) and the first pad (202) are connected through the first bonding wire (300), and a shielding shell wrapping the bare chip main body (101) is formed on the surface of the bare chip main body (101);
the shielding structure (102) is a metal mesh structure, the mesh size of the metal mesh structure is smaller than or equal to 1/10 needing to shield the wavelength of the electromagnetic wave, and the mesh width of the metal mesh structure is smaller than or equal to the width of the first pin (103);
the thickness of the shielding structure (102) is greater than or equal to the skin depth of electromagnetic waves to be shielded in the top layer material of the bare chip main body (101);
the shielding structure (102) is manufactured by utilizing top layer metal processing of the bare chip main body (101).
2. The quad flat chip package structure with high EMI resistance of claim 1, wherein the die (100) comprises a plurality of second leads (104), and the second leads (104) and the first leads (103) are spaced apart from each other on the die body (101).
3. The quad flat chip package structure with high EMI resistance according to claim 2, wherein the package (200) comprises a second bonding pad (203) and a chip pin (204), the second bonding pad (203) is connected to the second lead (104) through a second bonding wire (400).
4. The quad flat chip package structure with high electromagnetic pulse interference resistance of claim 3, wherein the package (200) further comprises a package housing (205), the package housing (205) is used for sealing and protecting the bare chip (100), and the lower surface of the lead frame body (201) is located outside the package housing (205).
5. The quad flat chip package structure with high electromagnetic pulse interference resistance of claim 1, wherein the distance between adjacent first leads (103) is less than or equal to 1/10 of the wavelength of the electromagnetic wave to be shielded.
6. The quad flat chip package structure with high electromagnetic pulse interference resistance of claim 1, characterized in that the distance between the bonding point of the first lead (103) and the bonding point of the first pad (202) is less than or equal to 1/10 of the wavelength of the electromagnetic wave to be shielded.
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| CN202010549022.9A CN111653552B (en) | 2020-06-16 | 2020-06-16 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
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| CN202010549022.9A CN111653552B (en) | 2020-06-16 | 2020-06-16 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
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| CN108541205A (en) * | 2017-03-01 | 2018-09-14 | 鹏鼎控股(深圳)股份有限公司 | Electro-magnetic shielding cover and preparation method thereof |
| CN111276461A (en) * | 2020-02-19 | 2020-06-12 | 青岛歌尔微电子研究院有限公司 | Square flat pin-free packaging structure, preparation method thereof and electronic device |
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