CN111276461A - Square flat pin-free packaging structure, preparation method thereof and electronic device - Google Patents
Square flat pin-free packaging structure, preparation method thereof and electronic device Download PDFInfo
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- CN111276461A CN111276461A CN202010103373.7A CN202010103373A CN111276461A CN 111276461 A CN111276461 A CN 111276461A CN 202010103373 A CN202010103373 A CN 202010103373A CN 111276461 A CN111276461 A CN 111276461A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a square flat pin-free packaging structure, a preparation method thereof and an electronic device, wherein the square flat pin-free packaging structure comprises: the frame is provided with a first side and a second side which are opposite, the first side is provided with a chip base and a plurality of pin arranging areas which are arranged around the periphery of the chip base, the plurality of pin arranging areas are arranged in an inner ring and an outer ring, and each pin arranging area is provided with a plurality of pins which are distributed along the circumferential direction of the pin arranging area; the chip is arranged on the chip base; the lead wires are correspondingly connected with the external terminals of the chip and the pins; the plastic package body is arranged on the frame and simultaneously seals the pin, the chip and the lead. According to the invention, the plurality of pin groups which are arranged in the inner ring and the outer ring are arranged around the chip, so that the pin density of the square flat pin-free packaging structure is improved, and the packaging integration level is favorably improved.
Description
Technical Field
The invention relates to the technical field of square flat pin-free packaging structures, in particular to a square flat pin-free packaging structure, a preparation method thereof and an electronic device.
Background
QFN (Quad Flat Non-leaded Package) is a common Package form, has good electrical and thermal properties, small volume, light weight, low development cost, and is widely used. However, at present, QFN is limited by insufficient number of I/O (input/output pins), so the integration level is affected accordingly.
Disclosure of Invention
The invention mainly aims to provide a quad flat non-leaded package structure, a preparation method thereof and an electronic device, and aims to improve the pin density of the quad flat non-leaded package structure.
In order to achieve the above object, the present invention provides a quad flat non-leaded package structure, including:
the frame is provided with a first side and a second side which are opposite, the first side is provided with a chip base and a plurality of pin setting areas which are arranged around the periphery of the chip base, the pin setting areas are arranged in an inner ring and an outer ring, and each pin setting area is provided with a plurality of pins which are distributed along the circumferential direction of the pin setting area;
the chip is arranged on the chip base;
the leads are correspondingly connected with the external terminals of the chip and the pins; and the number of the first and second groups,
and the plastic package body is arranged on the frame and simultaneously seals the pin, the chip and the lead.
Optionally, the second side of the frame is provided with an electroplated layer.
Further, the invention also provides a preparation method of the square flat pin-free packaging structure, which comprises the following steps:
providing a frame, wherein the frame is provided with a first side and a second side which are opposite, an opening is formed on the frame, so that a chip base area and a plurality of pin arranging areas which are arranged around the periphery of the chip base are formed on the first side, the plurality of pin arranging areas are arranged in an inner ring and an outer ring, and each pin arranging area is provided with a plurality of pins which are distributed along the circumferential direction of the pin arranging area;
pre-packaging the frame, and filling an opening on the frame with resin to obtain a pre-packaged frame;
arranging a chip in a chip base area of the frame after the pre-packaging;
arranging lead wires correspondingly connected with external terminals of the chip and the pins;
and carrying out plastic package on the frame to form a plastic package body for simultaneously sealing the pin, the chip and the lead, so as to obtain the square flat pin-free packaging structure.
Optionally, after the step of pre-encapsulating the frame and filling the opening on the frame with resin to obtain a pre-encapsulated frame, the method further includes:
and arranging a plurality of pins in the pin arrangement area of the pre-packaged frame.
Optionally, the step of setting a plurality of pins in the pin setting area of the pre-packaged frame includes:
the second side of the frame is ground to sever the electrical connection between the pins to form a plurality of effectively separated pins.
Optionally, the step of grinding the second side of the frame to sever the electrical connection between the pins to form a plurality of effectively separated pins comprises:
the grinding is chemical grinding or mechanical grinding.
Optionally, after the step of setting a plurality of pins in the pin setting area of the pre-packaged frame, the method further includes:
electroplating the frame to form an electroplated layer on the second side of the frame.
Optionally, in the step of disposing a chip in the chip base region of the pre-packaged frame:
the chip is arranged in a manner of being fixed to the chip base region by bonding.
Optionally, the frame is formed on a substrate, the substrate is provided with a plurality of frames, and correspondingly, the frames are subjected to plastic package to form a plastic package body which simultaneously seals the pins, the chip and the leads, and the step of manufacturing the square flat leadless package structure includes:
and carrying out plastic package on the frame to form a plastic package body for simultaneously sealing the pins, the chip and the leads, and then cutting the substrate to manufacture a plurality of independent square flat pin-free packaging structures.
In addition, the invention also provides an electronic device which comprises the quad flat non-lead packaging structure.
According to the technical scheme provided by the invention, the frame is provided with the chip base and the pin arrangement areas which are arranged around the periphery of the chip base, the pin arrangement areas are arranged in an inner ring and an outer ring, each pin arrangement area is provided with a plurality of pins which are distributed along the circumferential direction of the pin arrangement area, namely, a plurality of pin groups which are distributed in the inner ring and the outer ring are arranged around the chip, so that the pin density of the square flat pin-free packaging structure is improved, and the packaging integration level is favorably improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other related drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a QFN package structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another perspective view of the quad flat non-leaded package of FIG. 1;
FIG. 3 is a schematic flow chart illustrating a method for manufacturing a QFN package structure according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of the frame of FIG. 3 after being pre-packaged;
FIG. 5 is a schematic view of the structure of FIG. 3 after the pins and the plating layer are provided;
FIG. 6 is a schematic structural diagram of the chip in FIG. 3 after being mounted;
FIG. 7 is a schematic view of the structure of FIG. 3 after the lead wires are disposed;
fig. 8 is a schematic structural diagram of the plastic package body formed by plastic package in fig. 3.
The reference numbers illustrate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially. In addition, the meaning of "and/or" appearing throughout includes three juxtapositions, exemplified by "A and/or B" including either A or B or both A and B. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
QFN (Quad Flat Non-leaded Package) is a common Package form, has good electrical and thermal properties, small volume, light weight, low development cost, and is widely used. However, at present, QFN is limited by insufficient number of I/O (input/output pins), so the integration level is affected accordingly.
In view of the above, the present invention provides a qfn package structure, and fig. 1 and 2 show an embodiment of the qfn package structure according to the present invention. Referring to fig. 1 and fig. 2, in the present embodiment, a quad flat non-leaded package structure 100 includes a frame 1, a chip 3, a lead 4 and a plastic package body 5, wherein the frame 1 has a first side and a second side opposite to each other, the first side is provided with a chip 3 base and a plurality of pin setting areas surrounding the periphery of the chip 3 base, the plurality of pin setting areas are arranged in an inner ring and an outer ring, and each of the pin setting areas is provided with a plurality of pins 2 distributed along the circumferential direction of the pin setting area; the chip 3 is arranged on the chip 3 base; the lead wires 4 are correspondingly connected with the external terminals of the chip 3 and the pins 2; the plastic package body 5 is arranged on the frame 1 and simultaneously seals the pin 2, the chip 3 and the lead 4.
In the technical scheme provided by the invention, a chip 3 base and a plurality of pin setting areas which are arranged around the periphery of the chip 3 base are arranged on a frame 1, the pin setting areas are arranged in an inner ring and an outer ring, and each pin setting area is provided with a plurality of pins 2 which are distributed along the circumferential direction of the pin setting area, namely, a plurality of pin 2 groups which are distributed in the inner ring and the outer ring are arranged around the chip 3, so that the density of the pins 2 of the square flat pin-free packaging structure 100 is improved, and the packaging integration level is favorably improved.
The number of the pin setting regions is not specifically limited, for example, the number may be two or more, and the greater the number, the higher the density of the corresponding pins 2, in this embodiment, the number of the pin setting regions is 2, which is taken as an example for explanation, that is, as shown in fig. 1 and fig. 2, two rows of pins 2 arranged in an inner ring and an outer ring are surrounded on the periphery of the chip 3. Further, a second side of the frame 1 is provided with a plating layer (not shown) provided corresponding to each pin 2. Through the setting of the electroplated layer, the pin 2 is protected, so that the pin 2 is prevented from being oxidized, and the stability of the square flat pin-free packaging structure 100 is improved.
Further, the present invention also provides a method for manufacturing the qfn package 100, and fig. 3 shows an embodiment of the method for manufacturing the qfn package 100 according to the present invention. Referring to fig. 3, in the present embodiment, the method for manufacturing the qfn package 100 includes the following steps:
step S10, providing a frame 1, where the frame 1 has a first side and a second side opposite to each other, and an opening 6 is formed on the frame 1 to form a chip 3 base region and a plurality of pin setting regions surrounding the periphery of the chip 3 base on the first side, where the plurality of pin setting regions are arranged in an inner and outer ring, and each pin setting region is provided with a plurality of pins 2 distributed along the circumference of the pin setting region;
Step S20, pre-packaging the frame 1, and filling the opening 6 on the frame 1 with resin to obtain the pre-packaged frame 1;
the frame 1 formed with the chip 3 base region and the plurality of pin arrangement regions is pre-packaged, so that the frame 1 is formed into a flat closed structure, as shown in fig. 4, thereby avoiding the problem that the conventional QFN package needs to be adhered to the back surface of the frame 1 by using an adhesive tape to prevent glue overflow during Molding. Specifically, in this embodiment, a specific method for pre-packaging the frame 1 is as follows: the openings 6 of the frame 1 are filled with a resin (e.g., epoxy resin, etc.), and the resin filling the openings 6 can also integrate all gaps formed between the base region of the chip 3 and the plurality of pins 2, so as to form a reinforcing layer on the first side of the frame 1, thereby avoiding the problem of unstable structure of the frame 1 during subsequent processing, such as forming the plurality of pins 2 independent of each other.
Further, in this embodiment, when the step S10 forms the pin disposing region by illuminating and developing after disposing the mask, the plurality of pins 2 are disposed independently of each other on the first side of the frame 1 and are connected to each other on the second side of the frame 1, and therefore, after the step S20, the method further comprises:
step S30, a plurality of pins 2 are arranged in the pin arrangement area of the pre-packaged frame 1.
In the present embodiment, the manner of providing a plurality of pins 2 that are completely independent of each other is: the second side of the frame 1 is ground to cut the electrical connection between the pins 2, i.e. to cut the parts of the plurality of pins 2 that are connected to each other at the second side of the frame 1, resulting in an effectively separated plurality of pins 2, as shown in fig. 5. Further, in this embodiment, the grinding is chemical grinding or mechanical grinding, and the mutually connected portions of the plurality of pins 2 are removed by chemical grinding or mechanical grinding, so that the plurality of pins 2 are completely independent from each other, and a plurality of effectively separated pins 2 are formed.
Since the first side of the frame 1 is used for disposing the chip 3, the pins 2, and the leads 4 connecting the chip 3 and the pins 2, and finally the molding compound 5 is required to be disposed to package the chip 3, the pins 2, and the leads 4 at the same time, that is, the first side of the frame 1 can be isolated from air by the molding compound 5 to prevent oxidation of the components, in this embodiment, in order to prevent oxidation of the second side of the frame 1, it is preferable that after step S30, the method further includes:
step S40, electroplating the frame 1 to form an electroplated layer on the second side of the frame 1.
In this way, by providing the plating layer on the second side of the frame 1, and the plating layer is disposed corresponding to the pins 2, the pins 2 are prevented from being oxidized, which affects the stability of the quad flat non-leaded package structure 100.
Step S50, arranging a chip 3 in a chip 3 base area of the frame 1 after pre-packaging;
after the plurality of pins 2 and the plating layer are completely provided, the chip 3 is provided on the base area of the chip 3 on the frame 1, and as shown in fig. 6, the chip 3 may be fixedly mounted on the base area of the chip 3 by means of, for example, adhesion, and the adhesive material used may be, for example, an adhesive tape or an adhesive resin.
Step S60, setting external terminals correspondingly connected with the chip 3 and a plurality of leads 4 of the pins 2;
after the chip 3 is completely arranged, the leads 4 are arranged in a welding manner, as shown in fig. 7, each lead 4 is correspondingly connected with an external port of the chip 3 and one of the pins 2, so that the plurality of pins 2 are electrically connected with the chip 3. The lead 4 may be a conductive metal material, such as gold wire, copper wire, alloy wire, or the like, and is preferably gold wire.
Step S70, performing plastic package on the frame 1 to form a plastic package body 5 for simultaneously sealing the pin 2, the chip 3 and the lead 4, and obtaining the square flat leadless package structure 100.
After the plurality of pins 2, the chip 3, and the leads 4 are arranged, the frame 1 is subjected to plastic package, and a plastic package body 5 for simultaneously sealing the pins 2, the chip 3, and the leads 4 is formed on the first side of the frame 1, as shown in fig. 8, so as to obtain the square flat non-lead package structure 100.
It should be noted that, in the present embodiment shown in fig. 3, the step of providing the plurality of effectively separated pins 2 on the frame 1 and electroplating the frame 1 to form the electroplated layer is performed before the step of plastically molding the frame 1, but in other embodiments of the present invention, the step of providing the plurality of effectively separated pins 2 on the frame 1 and electroplating the frame 1 to form the electroplated layer may be performed after the step of plastically molding the frame 1, that is, all processing processes on the first side of the frame 1 are completed first, and then the second side of the frame 1 is processed, so that the above-mentioned square non-lead package structure 100 can be similarly obtained.
With the above-mentioned embodiments, the qfn package structure 100 can be successfully manufactured, and in practical production, for process saving, it is usually processed in batch, so in this embodiment, it is more preferable that the frame 1 is formed on a substrate, and the substrate is provided with a plurality of frames 1, correspondingly, step S70 includes: and carrying out plastic package on the frame 1 to form a plastic package body 5 for simultaneously sealing the pins 2, the chip 3 and the leads 4, and then cutting the substrate to manufacture a plurality of independent square flat pin-free packaging structures 100. Thus, the processing efficiency can be improved by processing a plurality of frames 1 arranged on the same substrate, wherein the number of the frames 1 arranged on the substrate is not limited, and may be any number of more than two, in this embodiment, refer to fig. 3 to 8 together, taking the substrate provided with two frames 1 as an example for description, after the plastic package processing is completed, the substrate is cut according to the dotted line shown in fig. 8, and then a plurality of independent square flat leadless package structures 100 can be obtained.
In addition, the present invention also provides an electronic device, which includes the above-mentioned qfn package structure 100. It can be understood that, since the electronic device includes all the features of the qfn package 100, all the advantages of the qfn package 100 are also provided, and the description thereof is omitted here.
The above is only a preferred embodiment of the present invention, and it is not intended to limit the scope of the invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall be included in the scope of the present invention.
Claims (10)
1. A quad flat non-leaded package structure, comprising:
the frame is provided with a first side and a second side which are opposite, the first side is provided with a chip base and a plurality of pin setting areas which are arranged around the periphery of the chip base, the pin setting areas are arranged in an inner ring and an outer ring, and each pin setting area is provided with a plurality of pins which are distributed along the circumferential direction of the pin setting area;
the chip is arranged on the chip base;
the leads are correspondingly connected with the external terminals of the chip and the pins; and the number of the first and second groups,
and the plastic package body is arranged on the frame and simultaneously seals the pin, the chip and the lead.
2. The quad flat non-leaded package structure of claim 1 wherein the second side of the frame is provided with an electroplated layer.
3. A preparation method of a square flat pin-free packaging structure is characterized by comprising the following steps:
providing a frame, wherein the frame is provided with a first side and a second side which are opposite, an opening is formed on the frame, so that a chip base area and a plurality of pin arranging areas which are arranged around the periphery of the chip base are formed on the first side, the plurality of pin arranging areas are arranged in an inner ring and an outer ring, and each pin arranging area is provided with a plurality of pins which are distributed along the circumferential direction of the pin arranging area;
pre-packaging the frame, and filling an opening on the frame with resin to obtain a pre-packaged frame;
arranging a chip in a chip base area of the frame after the pre-packaging;
arranging lead wires correspondingly connected with external terminals of the chip and the pins;
and carrying out plastic package on the frame to form a plastic package body for simultaneously sealing the pin, the chip and the lead, so as to obtain the square flat pin-free packaging structure.
4. The method of manufacturing qfn package structure according to claim 3, wherein the step of pre-encapsulating the frame, filling the opening in the frame with resin, and obtaining the pre-encapsulated frame further comprises:
and arranging a plurality of pins in the pin arrangement area of the pre-packaged frame.
5. The method of manufacturing qfn package structure according to claim 4, wherein the step of providing a plurality of pins in the pin-providing area of the pre-packaged frame comprises:
the second side of the frame is ground to sever the electrical connection between the pins to form a plurality of effectively separated pins.
6. The method of manufacturing qfn package structure of claim 5, wherein the step of grinding the second side of the frame to sever the electrical connection between the pins to form the effectively separated plurality of pins comprises:
the grinding is chemical grinding or mechanical grinding.
7. The method for manufacturing qfn package structure according to claim 4, wherein after the step of disposing a plurality of pins in the pin disposing region of the pre-packaged frame, the method further comprises:
electroplating the frame to form an electroplated layer on the second side of the frame.
8. The method for manufacturing qfn package structure of claim 3, wherein in the step of disposing a chip on the chip pad area of the pre-packaged frame:
the chip is arranged in a manner of being fixed to the chip base region by bonding.
9. The method for manufacturing the qfn package structure according to claim 3, wherein the frame is formed on a substrate, the substrate is provided with a plurality of frames, and the frames are correspondingly plastic-encapsulated to form a plastic-encapsulated body for simultaneously encapsulating the pins, the chip and the leads, so as to obtain the qfn package structure, comprising the steps of:
and carrying out plastic package on the frame to form a plastic package body for simultaneously sealing the pins, the chip and the leads, and then cutting the substrate to manufacture a plurality of independent square flat pin-free packaging structures.
10. An electronic device comprising the qfn package structure of claim 1 or 2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103373.7A CN111276461A (en) | 2020-02-19 | 2020-02-19 | Square flat pin-free packaging structure, preparation method thereof and electronic device |
| PCT/CN2020/135035 WO2021164386A1 (en) | 2020-02-19 | 2020-12-09 | Quad flat non-leaded package structure and preparation method therefor, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103373.7A CN111276461A (en) | 2020-02-19 | 2020-02-19 | Square flat pin-free packaging structure, preparation method thereof and electronic device |
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| Publication Number | Publication Date |
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| CN111276461A true CN111276461A (en) | 2020-06-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010103373.7A Pending CN111276461A (en) | 2020-02-19 | 2020-02-19 | Square flat pin-free packaging structure, preparation method thereof and electronic device |
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| Country | Link |
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| CN (1) | CN111276461A (en) |
| WO (1) | WO2021164386A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653552A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
| CN111653551A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | BGA chip packaging structure with high anti-electromagnetic pulse interference capability |
| WO2021164386A1 (en) * | 2020-02-19 | 2021-08-26 | 青岛歌尔微电子研究院有限公司 | Quad flat non-leaded package structure and preparation method therefor, and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339809A (en) * | 2011-11-04 | 2012-02-01 | 北京工业大学 | QFN (quad flat non-lead) package with multiple circles of pins and manufacturing method thereof |
| CN102683230A (en) * | 2012-05-30 | 2012-09-19 | 天水华天科技股份有限公司 | Quad flat no-lead multi-circle-arranged integrated circuit (IC) chip packaging part and production method thereof |
| CN105280597A (en) * | 2014-07-23 | 2016-01-27 | 华天科技（西安）有限公司 | Packaging member for reducing width of lead wire by using grinding technology and manufacture process thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7226811B1 (en) * | 1998-06-10 | 2007-06-05 | Asat Ltd. | Process for fabricating a leadless plastic chip carrier |
| CN101740407A (en) * | 2008-11-25 | 2010-06-16 | 三星电子株式会社 | Process for encapsulating square flat outer-pin-free encapsulating structure |
| CN111276461A (en) * | 2020-02-19 | 2020-06-12 | 青岛歌尔微电子研究院有限公司 | Square flat pin-free packaging structure, preparation method thereof and electronic device |
-
2020
- 2020-02-19 CN CN202010103373.7A patent/CN111276461A/en active Pending
- 2020-12-09 WO PCT/CN2020/135035 patent/WO2021164386A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339809A (en) * | 2011-11-04 | 2012-02-01 | 北京工业大学 | QFN (quad flat non-lead) package with multiple circles of pins and manufacturing method thereof |
| CN102683230A (en) * | 2012-05-30 | 2012-09-19 | 天水华天科技股份有限公司 | Quad flat no-lead multi-circle-arranged integrated circuit (IC) chip packaging part and production method thereof |
| CN105280597A (en) * | 2014-07-23 | 2016-01-27 | 华天科技（西安）有限公司 | Packaging member for reducing width of lead wire by using grinding technology and manufacture process thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021164386A1 (en) * | 2020-02-19 | 2021-08-26 | 青岛歌尔微电子研究院有限公司 | Quad flat non-leaded package structure and preparation method therefor, and electronic device |
| CN111653552A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
| CN111653551A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | BGA chip packaging structure with high anti-electromagnetic pulse interference capability |
| CN111653552B (en) * | 2020-06-16 | 2022-06-10 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021164386A1 (en) | 2021-08-26 |
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Application publication date: 20200612 |