WO2021164386A1 - Quad flat non-leaded package structure and preparation method therefor, and electronic device - Google Patents

Quad flat non-leaded package structure and preparation method therefor, and electronic device Download PDF

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Publication number
WO2021164386A1
WO2021164386A1 PCT/CN2020/135035 CN2020135035W WO2021164386A1 WO 2021164386 A1 WO2021164386 A1 WO 2021164386A1 CN 2020135035 W CN2020135035 W CN 2020135035W WO 2021164386 A1 WO2021164386 A1 WO 2021164386A1
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WO
WIPO (PCT)
Prior art keywords
frame
pins
chip
package structure
lead package
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Application number
PCT/CN2020/135035
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French (fr)
Chinese (zh)
Inventor
尹保冠
于上家
陈建超
Original Assignee
青岛歌尔微电子研究院有限公司
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Publication of WO2021164386A1 publication Critical patent/WO2021164386A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the application relates to the technical field of a square flat no-lead packaging structure, and in particular to a square flat no-lead packaging structure, a preparation method thereof, and an electronic device.
  • QFN Quad Flat Non-leaded Package
  • I/O input/output, input and output pins
  • the main purpose of this application is to propose a quad flat no-lead package structure and a preparation method thereof, and an electronic device, aiming to improve the pin density of the square flat no-lead package structure.
  • this application proposes a quad flat no-lead package structure, which includes:
  • a frame the frame has opposite first and second sides, the first side is provided with a chip base and a plurality of pin setting areas surrounding the outer periphery of the chip base, and a plurality of the pins
  • the setting area is arranged in an inner and outer ring, and each of the pin setting areas is provided with a plurality of pins distributed along the circumference of the pin setting area;
  • the chip is set on the chip base
  • Leads correspondingly connect the external terminals of the chip and a plurality of the pins;
  • the plastic encapsulation body is arranged on the frame and simultaneously seals the pins, chips and leads.
  • the second side of the frame is provided with an electroplating layer.
  • this application also proposes a method for manufacturing a quad flat no-lead package structure, which includes the following steps:
  • a frame is provided, the frame has a first side and a second side opposite to each other, and an opening is formed on the frame to form a chip base area and a plurality of chips surrounding the chip base on the first side.
  • a pin setting area, a plurality of the pin setting areas are arranged in an inner and an outer ring, and each of the pin setting areas is provided with a plurality of pins distributed along the circumference of the pin setting area;
  • Pre-encapsulating the frame and filling the opening on the frame with resin to obtain a pre-encapsulated frame;
  • the frame is plastic-encapsulated to form a plastic-encapsulated body that simultaneously seals the pins, chips and leads, and a square flat no-lead package structure is obtained.
  • the method further includes:
  • a plurality of pins are arranged in the pin setting area of the pre-packaged frame.
  • the step of setting a plurality of pins in the pin setting area of the pre-packaged frame includes:
  • the second side of the frame is polished to cut off the electrical connection structure between the pins to form a plurality of pins that are effectively separated:
  • the grinding is chemical grinding or mechanical grinding.
  • the method further includes:
  • the frame is electroplated to form a plating layer on the second side of the frame.
  • the chip is arranged in a manner of being fixed to the chip base area by bonding.
  • the frame is formed on a substrate, and a plurality of the frames are provided on the substrate.
  • the frame is plastic-encapsulated to form a plastic-encapsulation that simultaneously seals the pins, chips, and leads Body, the steps of fabricating a quad flat no-lead package structure include:
  • the frame is plastic-encapsulated to form a plastic-encapsulated body that simultaneously seals the pins, chips and leads, and then the substrate is cut to form a plurality of independent square flat no-lead package structures.
  • the present application also proposes an electronic device including the above-mentioned quad flat no-lead package structure.
  • a chip base and a plurality of pin setting areas surrounding the outer periphery of the chip base are arranged on the frame, and the plurality of pin setting areas are arranged in an inner and outer ring, and each The pin setting area is provided with a plurality of pins distributed along the circumference of the pin setting area, that is, a plurality of pin groups arranged in an inner and outer ring are arranged around the chip, so that the square shape is improved.
  • the pin density of the flat no-lead package structure helps to improve the package integration.
  • FIG. 1 is a schematic structural diagram of an embodiment of a quad flat no-lead package structure provided by this application;
  • FIG. 2 is a schematic structural diagram of the quad flat no-lead package structure in FIG. 1 from another perspective;
  • FIG. 3 is a schematic flowchart of an embodiment of a method for manufacturing a square flat no-lead package structure provided by this application;
  • Fig. 4 is a schematic diagram of the structure of the frame in Fig. 3 after pre-encapsulation
  • FIG. 5 is a schematic diagram of the structure after the pins and the electroplating layer are set in FIG. 3;
  • FIG. 6 is a schematic diagram of the structure after the chip is set in FIG. 3;
  • FIG. 7 is a schematic diagram of the structure after the leads are set in FIG. 3;
  • FIG. 8 is a schematic diagram of the structure of FIG. 3 after plastic packaging is performed to form a plastic package.
  • QFN Quad Flat Non-leaded Package
  • I/O input/output, input and output pins
  • FIGS. 1 and 2 show an embodiment of the quad flat no-lead package structure provided by this application.
  • the quad flat no-lead package structure 100 includes a frame 1, a chip 3, a lead 4, and a plastic package 5.
  • the frame 1 has a first side and a first side opposite to each other. On the two sides, the first side is provided with a chip 3 base and a plurality of pin setting areas surrounding the outer periphery of the chip 3 base. A plurality of the pin setting areas are arranged in an inner and outer ring.
  • the pin arrangement area is provided with a plurality of pins 2 distributed along the circumference of the pin arrangement area; the chip 3 is arranged on the base of the chip 3; the lead 4 is correspondingly connected to the outside of the chip 3 A terminal and a plurality of the pins 2; the plastic encapsulation body 5 is arranged on the frame 1, and the pins 2, the chip 3 and the leads 4 are sealed at the same time.
  • each pin arrangement area is provided with a plurality of pins 2 distributed along the circumference of the pin arrangement area, that is, a plurality of groups of pins 2 arranged in an inner and outer ring are arranged around the chip 3
  • the pin 2 density of the quad flat no-lead package structure 100 is increased, which is beneficial to improve the package integration.
  • the number of the pin setting area is not specifically limited. For example, it can be two or more. The more the number, the higher the density of the corresponding pin 2.
  • the pin 2 The number of setting areas is two as an example for description. That is, as shown in FIG. 1 and FIG. 2, the chip 3 is surrounded by two rows of pins 2 arranged in an inner and outer ring. Further, an electroplating layer (not shown) is provided on the second side of the frame 1, and the electroplating layer is provided corresponding to each pin 2. Through the arrangement of the electroplating layer, the pin 2 is protected to prevent the pin 2 from being oxidized, and the stability of the quad flat no-lead package structure 100 is improved.
  • FIG. 3 shows an embodiment of the method for preparing a quad flat no-lead package structure 100 provided by this application.
  • the method for preparing the quad flat no-lead package structure 100 includes the following steps:
  • Step S10 Provide a frame 1, which has a first side and a second side opposite to each other.
  • An opening 6 is formed on the frame 1 to form a chip 3 base area on the first side and surround it.
  • a plurality of pin setting areas on the outer periphery of the chip 3 base, the plurality of pin setting areas are arranged in an inner and outer ring, and each of the pin setting areas is provided with a plurality of pins along the circumference of the pin setting area.
  • Pin 2 to be distributed;
  • the frame 1 is made of conductive metal material, usually copper or copper alloy.
  • a mask can be set on the frame 1, and then illuminated and developed to form an opening 6 (as shown in FIG. 4), so that the frame 1
  • the chip 3 base area and a plurality of pin setting areas are formed on the first side, wherein a plurality of the pin setting areas are arranged on the outer periphery of the chip 3 base area and arranged in an inner and outer ring.
  • the pin arrangement area is provided with a plurality of pins 2 distributed along the circumference of the pin arrangement area, that is, a plurality of pins 2 arranged in an inner and outer ring are arranged around the base area of the chip 3 Therefore, the pin 2 density of the quad flat no-lead package structure 100 is increased, which is beneficial to improve the package integration.
  • Step S20 pre-encapsulating the frame 1 and filling the opening 6 on the frame 1 with resin to obtain the pre-encapsulated frame 1;
  • the frame 1 formed with the base area of the chip 3 and a plurality of pin setting areas is pre-packaged, so that the frame 1 is formed into a flat plate-shaped closed structure, as shown in FIG. 4, thereby eliminating the need for traditional QFN
  • the package must be pasted on the back of the frame 1 with tape to prevent the problem of glue overflow during molding.
  • the specific method for pre-encapsulating the frame 1 is: filling the opening 6 on the frame 1 with resin (for example, epoxy resin, etc.), at this time, filling the opening 6
  • resin for example, epoxy resin, etc.
  • the resin can also connect all the gaps formed between the base area of the chip 3 and the plurality of pins 2 into a whole, thereby forming a reinforcing layer on the first side of the frame 1 to avoid subsequent processing
  • the structure of the frame 1 is unstable.
  • step S10 when the pin setting area is formed by light and developing after setting a mask in step S10, a plurality of the pins 2 are mutually arranged on the first side of the frame 1. It is independently arranged, and is connected to each other on the second side of the frame 1. Therefore, after step S20, it further includes:
  • Step S30 setting a plurality of pins 2 in the pin setting area of the pre-packaged frame 1.
  • the way to provide a plurality of pins 2 completely independent of each other is to grind the second side of the frame 1 to cut off the electrical connection structure between the pins 2, that is, to cut off a plurality of The connecting part of the pins 2 on the second side of the frame 1 finally forms a plurality of pins 2 that are effectively separated, as shown in FIG. 5.
  • the polishing is chemical polishing or mechanical polishing, and the interconnected parts of the plurality of pins 2 are removed by chemical polishing or mechanical polishing, so that the plurality of pins 2 2 are completely independent of each other, forming multiple pins 2 that are effectively separated.
  • step S30 in order to prevent the frame 1 from being damaged Oxidation occurs on the second side, preferably after step S30, further comprising:
  • Step S40 electroplating the frame 1 to form an electroplating layer on the second side of the frame 1.
  • Step S50 setting the chip 3 in the chip 3 base area of the pre-packaged frame 1;
  • the chip 3 is arranged on the base area of the chip 3 on the frame 1, as shown in FIG.
  • the adhesive material used can be, for example, adhesive tape or adhesive resin.
  • Step S60 setting up leads 4 corresponding to the external terminals of the chip 3 and the plurality of pins 2;
  • each lead 4 is correspondingly connected to an external port of the chip 3 and a pin 2.
  • the lead 4 may be made of conductive metal material, such as gold wire, copper wire or alloy wire, etc., more preferably gold wire.
  • step S70 the frame 1 is plastic-encapsulated to form a plastic-encapsulated body 5 that simultaneously seals the pins 2, the chip 3 and the leads 4, and a square flat no-lead package structure 100 is produced.
  • the frame 1 is plastic-encapsulated, and the pins 2, the chip 3 and the leads 4 are simultaneously sealed on the first side of the frame 1.
  • the plastic package body 5 of, that is, the square flat no-lead package structure 100 is manufactured.
  • a plurality of effectively separated pins 2 are provided on the frame 1, and the step of electroplating the frame 1 to form an electroplated layer is to
  • the frame 1 is implemented before the step of plastic encapsulation, and in other embodiments of the present application, a plurality of effectively separated pins 2 can also be provided on the frame 1, and the frame 1 is electroplated to form an electroplated layer
  • the step is performed after the step of plastic-sealing the frame 1, that is, all the processing processes on the first side of the frame 1 are completed first, and then the second side of the frame 1 is processed, Similarly, the above-mentioned quad flat no-lead package structure 100 can be manufactured.
  • the quad flat no-lead package structure 100 can be successfully manufactured. In actual production, in order to save the process, it is usually processed in batches. Therefore, in this embodiment, it is more preferable to The frame 1 is formed on a substrate, and a plurality of the frames 1 are provided on the substrate.
  • step S70 includes: plastic-encapsulating the frame 1 to form and simultaneously seal the pins 2, the chip 3 and the leads. 4, and then cut the substrate to form a plurality of independent square flat no-lead package structures 100.
  • the number of frames 1 provided on the substrate is not limited, and it can be any number of two or more.
  • two frames 1 are provided on the substrate as an example for description. After the molding process is completed, the substrate is cut according to the dotted line shown in FIG. 8 , A plurality of independent quad flat no-lead package structures 100 can be obtained.
  • the present application also proposes an electronic device, including the quad flat no-lead package structure 100 as described above. It is understandable that, since the electronic device includes all the features of the quad flat no-lead package structure 100, it also has all the beneficial effects of the quad flat no-lead package structure 100, which will not be repeated here. .

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

Disclosed are a quad flat non-leaded package structure (100) and a preparation method therefor, and an electronic device. The quad flat non-leaded package structure (100) comprises a frame (1), a chip (3), a lead (4) and a plastic packaging body (5), wherein the frame (1) is provided with a first side and a second side which are opposite each other, the first side is provided with a base of the chip (3) and a plurality of pin setting areas surrounding the periphery of the base of the chip (3), the plurality of pin setting areas are arranged in an inner ring and an outer ring, and each pin setting area is provided with a plurality of pins (2) distributed in the circumferential direction of the pin setting area; the chip (3) is arranged on the base of the chip (3); the lead (4) is correspondingly connected to an external terminal of the chip (3) and the plurality of pins (2); and the plastic packaging body (5) is arranged on the frame (1) and also seals the pins (2), the chip (3) and the lead (4).

Description

方形扁平无引脚封装结构及其制备方法、以及电子器件Square flat no-lead packaging structure and preparation method thereof, and electronic device
本申请要求于2020年2月19日申请的、申请号为202010103373.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application filed on February 19, 2020 with the application number 202010103373.7, the entire content of which is incorporated into this application by reference.
技术领域Technical field
本申请涉及方形扁平无引脚封装结构技术领域，具体涉及一种方形扁平无引脚封装结构及其制备方法、以及电子器件。The application relates to the technical field of a square flat no-lead packaging structure, and in particular to a square flat no-lead packaging structure, a preparation method thereof, and an electronic device.
背景技术Background technique
QFN（Quad Flat Non-leaded Package，方形扁平无引脚封装）是一种常见的封装形式，具有良好的电和热性能、体积小、重量轻、开发成本低，其应用也非常广泛。但是目前QFN受限于I/O（input/output，输入输出管脚）数量不够多，所以集成度也受到相应影响。QFN (Quad Flat Non-leaded Package) is a common package form, with good electrical and thermal properties, small size, light weight, low development cost, and its application is also very wide. However, QFN is currently limited by the insufficient number of I/O (input/output, input and output pins), so the integration level is also affected accordingly.
技术解决方案Technical solutions
本申请的主要目的是提出一种方形扁平无引脚封装结构及其制备方法、以及电子器件，旨在提高方形扁平无引脚封装结构的管脚密度。The main purpose of this application is to propose a quad flat no-lead package structure and a preparation method thereof, and an electronic device, aiming to improve the pin density of the square flat no-lead package structure.
为实现上述目的，本申请提出一种方形扁平无引脚封装结构，包括：In order to achieve the above objective, this application proposes a quad flat no-lead package structure, which includes:
框架，所述框架具有相对的第一侧和第二侧，所述第一侧设有芯片基座和围设于所述芯片基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，每一所述管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚；A frame, the frame has opposite first and second sides, the first side is provided with a chip base and a plurality of pin setting areas surrounding the outer periphery of the chip base, and a plurality of the pins The setting area is arranged in an inner and outer ring, and each of the pin setting areas is provided with a plurality of pins distributed along the circumference of the pin setting area;
芯片，设于所述芯片基座；The chip is set on the chip base;
引线，对应连接所述芯片的外接端子与多个所述管脚；以及，Leads correspondingly connect the external terminals of the chip and a plurality of the pins; and,
塑封体，设于所述框架上，且同时密封所述管脚、芯片和引线设置。The plastic encapsulation body is arranged on the frame and simultaneously seals the pins, chips and leads.
在一实施例中，所述框架的第二侧设有电镀层。In an embodiment, the second side of the frame is provided with an electroplating layer.
进一步地，本申请还提出一种方形扁平无引脚封装结构的制备方法，包括以下步骤：Furthermore, this application also proposes a method for manufacturing a quad flat no-lead package structure, which includes the following steps:
提供一框架，所述框架具有相对的第一侧和第二侧，所述框架上形成有开口，以在所述第一侧形成芯片基座区和围设于所述芯片基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，每一所述管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚；A frame is provided, the frame has a first side and a second side opposite to each other, and an opening is formed on the frame to form a chip base area and a plurality of chips surrounding the chip base on the first side. A pin setting area, a plurality of the pin setting areas are arranged in an inner and an outer ring, and each of the pin setting areas is provided with a plurality of pins distributed along the circumference of the pin setting area;
对所述框架进行预封装，使用树脂填充所述框架上的开口，获得预封装后的框架；Pre-encapsulating the frame, and filling the opening on the frame with resin to obtain a pre-encapsulated frame;
在所述预封装后的框架的芯片基座区设置芯片；Disposing a chip in the chip base area of the pre-packaged frame;
设置对应连接所述芯片的外接端子和多个所述管脚的引线；Setting leads corresponding to the external terminals of the chip and the plurality of pins;
对所述框架进行塑封，形成同时密封所述管脚、芯片和引线的塑封体，制得方形扁平无引脚封装结构。The frame is plastic-encapsulated to form a plastic-encapsulated body that simultaneously seals the pins, chips and leads, and a square flat no-lead package structure is obtained.
在一实施例中，对所述框架进行预封装，使用树脂填充所述框架上的开口，获得预封装后的框架的步骤之后，还包括：In an embodiment, after the step of pre-encapsulating the frame, filling the openings on the frame with resin, and obtaining the pre-encapsulated frame, the method further includes:
在所述预封装后的框架的管脚设置区设置多个管脚。A plurality of pins are arranged in the pin setting area of the pre-packaged frame.
在一实施例中，在所述预封装后的框架的管脚设置区设置多个管脚的步骤，包括：In an embodiment, the step of setting a plurality of pins in the pin setting area of the pre-packaged frame includes:
对所述框架的第二侧进行研磨，以切断管脚之间的电连接结构，形成有效分离的多个管脚。Grinding the second side of the frame to cut off the electrical connection structure between the pins to form a plurality of pins that are effectively separated.
在一实施例中，对所述框架的第二侧进行研磨，以切断管脚之间的电连接结构，形成有效分离的多个管脚的步骤中：In one embodiment, the second side of the frame is polished to cut off the electrical connection structure between the pins to form a plurality of pins that are effectively separated:
所述研磨为化学研磨或机械研磨。The grinding is chemical grinding or mechanical grinding.
在一实施例中，在所述预封装后的框架的管脚设置区设置多个管脚的步骤之后，还包括：In an embodiment, after the step of setting a plurality of pins in the pin setting area of the pre-packaged frame, the method further includes:
对所述框架进行电镀，以在所述框架的第二侧形成电镀层。The frame is electroplated to form a plating layer on the second side of the frame.
在一实施例中，在所述预封装后的框架的芯片基座区设置芯片的步骤中：In one embodiment, in the step of arranging chips in the chip base area of the pre-packaged frame:
所述芯片的设置方式为通过粘接固定于所述芯片基座区。The chip is arranged in a manner of being fixed to the chip base area by bonding.
在一实施例中，所述框架形成于一基板上，所述基板上设有多个所述框架，对应地，对所述框架进行塑封，形成同时密封所述管脚、芯片和引线的塑封体，制得方形扁平无引脚封装结构的步骤包括：In an embodiment, the frame is formed on a substrate, and a plurality of the frames are provided on the substrate. Correspondingly, the frame is plastic-encapsulated to form a plastic-encapsulation that simultaneously seals the pins, chips, and leads Body, the steps of fabricating a quad flat no-lead package structure include:
对所述框架进行塑封，形成同时密封所述管脚、芯片和引线的塑封体，然后对基板进行切割，制成多个独立的方形扁平无引脚封装结构。The frame is plastic-encapsulated to form a plastic-encapsulated body that simultaneously seals the pins, chips and leads, and then the substrate is cut to form a plurality of independent square flat no-lead package structures.
此外，本申请还提出一种电子器件，包括如上所述的方形扁平无引脚封装结构。In addition, the present application also proposes an electronic device including the above-mentioned quad flat no-lead package structure.
本申请提供的技术方案中，通过在框架上设置芯片基座和围设于所述芯片基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，且每一管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚，也即，围绕所述芯片设置有多个呈内外环排布的管脚组，如此，提高了方形扁平无引脚封装结构的管脚密度，从而有利于提高封装集成度。In the technical solution provided by the present application, a chip base and a plurality of pin setting areas surrounding the outer periphery of the chip base are arranged on the frame, and the plurality of pin setting areas are arranged in an inner and outer ring, and each The pin setting area is provided with a plurality of pins distributed along the circumference of the pin setting area, that is, a plurality of pin groups arranged in an inner and outer ring are arranged around the chip, so that the square shape is improved. The pin density of the flat no-lead package structure helps to improve the package integration.
附图说明Description of the drawings
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅为本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。In order to more clearly describe the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only For some embodiments of the present application, for those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative work.
图1为本申请提供的方形扁平无引脚封装结构的一实施例的结构示意图；FIG. 1 is a schematic structural diagram of an embodiment of a quad flat no-lead package structure provided by this application;
图2为图1中方形扁平无引脚封装结构的另一视角的结构示意图；FIG. 2 is a schematic structural diagram of the quad flat no-lead package structure in FIG. 1 from another perspective;
图3为本申请提供的方形扁平无引脚封装结构的制备方法的一实施例的流程示意图；FIG. 3 is a schematic flowchart of an embodiment of a method for manufacturing a square flat no-lead package structure provided by this application;
图4为图3中对框架进行预封装后的结构示意图；Fig. 4 is a schematic diagram of the structure of the frame in Fig. 3 after pre-encapsulation;
图5为图3中设置管脚和电镀层后的结构示意图；FIG. 5 is a schematic diagram of the structure after the pins and the electroplating layer are set in FIG. 3;
图6为图3中设置芯片后的结构示意图；FIG. 6 is a schematic diagram of the structure after the chip is set in FIG. 3;
图7为图3中设置引线后的结构示意图；FIG. 7 is a schematic diagram of the structure after the leads are set in FIG. 3;
图8为图3中进行塑封形成塑封体后的结构示意图。FIG. 8 is a schematic diagram of the structure of FIG. 3 after plastic packaging is performed to form a plastic package.
附图标号说明：Attached icon number description:
100 100 方形扁平无引脚封装结构 Quad flat no-lead package structure 4 4 引线 lead
1 1 框架 frame 5 5 塑封体 Plastic package
2 2 管脚 Pin 6 6 开口 Opening
3 3 芯片 chip   To   To
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。The realization, functional characteristics, and advantages of the purpose of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings.
本发明的实施方式Embodiments of the present invention
为使本申请实施例的目的、技术方案和优点更加清楚，下面将对本申请实施例中的技术方案进行清楚、完整地描述。实施例中未注明具体条件者，按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者，均为可以通过市售购买获得的常规产品。另外，全文中出现的“和/或”的含义，包括三个并列的方案，以“A和/或B”为例，包括A方案、或B方案、或A和B同时满足的方案。此外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。In order to make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below. If no specific conditions are indicated in the examples, it shall be carried out in accordance with the conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments used without the manufacturer's indication are all conventional products that can be purchased on the market. In addition, the meaning of "and/or" in the full text includes three parallel schemes. Taking "A and/or B" as an example, it includes scheme A, scheme B, or schemes that meet both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on what can be achieved by a person of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist. , Is not within the scope of protection required by this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.
QFN（Quad Flat Non-leaded Package，方形扁平无引脚封装）是一种常见的封装形式，具有良好的电和热性能、体积小、重量轻、开发成本低，其应用也非常广泛。但是目前QFN受限于I/O（input/output，输入输出管脚）数量不够多，所以集成度也受到相应影响。QFN (Quad Flat Non-leaded Package) is a common package form, with good electrical and thermal properties, small size, light weight, low development cost, and its application is also very wide. However, QFN is currently limited by the insufficient number of I/O (input/output, input and output pins), so the integration level is also affected accordingly.
鉴于此，本申请提出一种方形扁平无引脚封装结构，图1和图2所示为本申请提供的方形扁平无引脚封装结构的一实施例。请参阅图1和图2，在本实施例中，方形扁平无引脚封装结构100包括框架1、芯片3、引线4以及塑封体5，其中，所述框架1具有相对的第一侧和第二侧，所述第一侧设有芯片3基座和围设于所述芯片3基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，每一所述管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚2；所述芯片3设于所述芯片3基座；所述引线4对应连接所述芯片3的外接端子与多个所述管脚2；所述塑封体5设于所述框架1上，且同时密封所述管脚2、芯片3和引线4设置。In view of this, this application proposes a quad flat no-lead package structure. FIGS. 1 and 2 show an embodiment of the quad flat no-lead package structure provided by this application. 1 and 2, in this embodiment, the quad flat no-lead package structure 100 includes a frame 1, a chip 3, a lead 4, and a plastic package 5. The frame 1 has a first side and a first side opposite to each other. On the two sides, the first side is provided with a chip 3 base and a plurality of pin setting areas surrounding the outer periphery of the chip 3 base. A plurality of the pin setting areas are arranged in an inner and outer ring. The pin arrangement area is provided with a plurality of pins 2 distributed along the circumference of the pin arrangement area; the chip 3 is arranged on the base of the chip 3; the lead 4 is correspondingly connected to the outside of the chip 3 A terminal and a plurality of the pins 2; the plastic encapsulation body 5 is arranged on the frame 1, and the pins 2, the chip 3 and the leads 4 are sealed at the same time.
本申请提供的技术方案中，通过在框架1上设置芯片3基座和围设于所述芯片3基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，且每一管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚2，也即，围绕所述芯片3设置有多个呈内外环排布的管脚2组，如此，提高了方形扁平无引脚封装结构100的管脚2密度，从而有利于提高封装集成度。In the technical solution provided by this application, by arranging a chip 3 base and a plurality of pin setting areas surrounding the outer periphery of the chip 3 base on the frame 1, the plurality of pin setting areas are arranged in an inner and outer ring, And each pin arrangement area is provided with a plurality of pins 2 distributed along the circumference of the pin arrangement area, that is, a plurality of groups of pins 2 arranged in an inner and outer ring are arranged around the chip 3 In this way, the pin 2 density of the quad flat no-lead package structure 100 is increased, which is beneficial to improve the package integration.
所述管脚设置区的个数不做具体限定，例如可以是两个或两个以上，个数越多，则对应的管脚2密度越高，在本实施例中均以所述管脚设置区的个数为2个为例进行说明，也即，如图1和图2所示，所述芯片3的外围围设有呈内外环设置的两排管脚2。进一步地，所述框架1的第二侧设有电镀层（未图示），所述电镀层对应各个管脚2设置。通过所述电镀层的设置，对所述管脚2起到保护作用，以防止所述管脚2发生氧化，提高所述方形扁平无引脚封装结构100的稳定性。The number of the pin setting area is not specifically limited. For example, it can be two or more. The more the number, the higher the density of the corresponding pin 2. In this embodiment, the pin 2 The number of setting areas is two as an example for description. That is, as shown in FIG. 1 and FIG. 2, the chip 3 is surrounded by two rows of pins 2 arranged in an inner and outer ring. Further, an electroplating layer (not shown) is provided on the second side of the frame 1, and the electroplating layer is provided corresponding to each pin 2. Through the arrangement of the electroplating layer, the pin 2 is protected to prevent the pin 2 from being oxidized, and the stability of the quad flat no-lead package structure 100 is improved.
进一步地，本申请还提出一种方形扁平无引脚封装结构100的制备方法，图3所示为本申请提供的方形扁平无引脚封装结构100的制备方法的一实施例。请参阅图3，在本实施例中，所述方形扁平无引脚封装结构100的制备方法包括以下步骤：Furthermore, the present application also proposes a method for preparing a quad flat no-lead package structure 100. FIG. 3 shows an embodiment of the method for preparing a quad flat no-lead package structure 100 provided by this application. Referring to FIG. 3, in this embodiment, the method for preparing the quad flat no-lead package structure 100 includes the following steps:
步骤S10、提供一框架1，所述框架1具有相对的第一侧和第二侧，所述框架1上形成有开口6，以在所述第一侧形成芯片3基座区和围设于所述芯片3基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，每一所述管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚2；Step S10. Provide a frame 1, which has a first side and a second side opposite to each other. An opening 6 is formed on the frame 1 to form a chip 3 base area on the first side and surround it. A plurality of pin setting areas on the outer periphery of the chip 3 base, the plurality of pin setting areas are arranged in an inner and outer ring, and each of the pin setting areas is provided with a plurality of pins along the circumference of the pin setting area. Pin 2 to be distributed;
所述框架1为导电的金属材质，通常为铜或铜合金，可以在所述框架1上设置掩膜，然后光照、显影形成开口6（如图4所示），从而在所述框架1的第一侧上形成所述芯片3基座区和多个管脚设置区，其中，多个所述管脚设置区围设于所述芯片3基座区外周且呈内外环设置，每一所述管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚2，也即，围绕所述芯片3基座区设置有多个呈内外环排布的管脚2组，由此，提高了所述方形扁平无引脚封装结构100的管脚2密度，从而有利于提高封装集成度。The frame 1 is made of conductive metal material, usually copper or copper alloy. A mask can be set on the frame 1, and then illuminated and developed to form an opening 6 (as shown in FIG. 4), so that the frame 1 The chip 3 base area and a plurality of pin setting areas are formed on the first side, wherein a plurality of the pin setting areas are arranged on the outer periphery of the chip 3 base area and arranged in an inner and outer ring. The pin arrangement area is provided with a plurality of pins 2 distributed along the circumference of the pin arrangement area, that is, a plurality of pins 2 arranged in an inner and outer ring are arranged around the base area of the chip 3 Therefore, the pin 2 density of the quad flat no-lead package structure 100 is increased, which is beneficial to improve the package integration.
步骤S20、对所述框架1进行预封装，使用树脂填充所述框架1上的开口6，获得预封装后的框架1；Step S20, pre-encapsulating the frame 1 and filling the opening 6 on the frame 1 with resin to obtain the pre-encapsulated frame 1;
对形成有所述芯片3基座区和多个管脚设置区的框架1进行预封装，以使得所述框架1形成为平板状的封闭结构，如图4所示，从而免去了传统QFN封装必须使用胶带粘贴在框架1背面，以防止Molding时溢胶的问题。具体地，在本实施例中，对所述框架1进行预封装的具体方法为：使用树脂（例如环氧树脂等）填充所述框架1上的开口6，此时，填充所述开口6的树脂还能将所述芯片3基座区和多个管脚2之间形成的所有间隙连成整体，从而在所述框架1的第一侧形成一个加强层，以避免在后续的加工过程中，例如形成彼此独立的多个管脚2时，所述框架1结构不稳定的问题。The frame 1 formed with the base area of the chip 3 and a plurality of pin setting areas is pre-packaged, so that the frame 1 is formed into a flat plate-shaped closed structure, as shown in FIG. 4, thereby eliminating the need for traditional QFN The package must be pasted on the back of the frame 1 with tape to prevent the problem of glue overflow during molding. Specifically, in this embodiment, the specific method for pre-encapsulating the frame 1 is: filling the opening 6 on the frame 1 with resin (for example, epoxy resin, etc.), at this time, filling the opening 6 The resin can also connect all the gaps formed between the base area of the chip 3 and the plurality of pins 2 into a whole, thereby forming a reinforcing layer on the first side of the frame 1 to avoid subsequent processing For example, when a plurality of pins 2 independent of each other are formed, the structure of the frame 1 is unstable.
进一步地，在本实施例中，当步骤S10中采用设置掩膜后光照、显影的方式形成所述管脚设置区时，多个所述管脚2在所述框架1的第一侧呈彼此独立设置，而在所述框架1的第二侧则是相互连接的，因此，在步骤S20之后，还包括：Further, in this embodiment, when the pin setting area is formed by light and developing after setting a mask in step S10, a plurality of the pins 2 are mutually arranged on the first side of the frame 1. It is independently arranged, and is connected to each other on the second side of the frame 1. Therefore, after step S20, it further includes:
步骤S30、在所述预封装后的框架1的管脚设置区设置多个管脚2。Step S30, setting a plurality of pins 2 in the pin setting area of the pre-packaged frame 1.
在本实施例中，设置多个彼此完全独立的管脚2的方式为：对所述框架1的第二侧进行研磨，以切断管脚2之间的电连接结构，也即，切断多个所述管脚2在所述框架1的第二侧相互连接的部分，最终形成有效分离的多个管脚2，如图5所示。进一步地，在本实施例中，所述研磨为化学研磨或机械研磨，通过化学研磨或机械研磨的方式，将多个所述管脚2相互连接的部分去除掉，使得多个所述管脚2之间彼此完全独立，形成有效分离的多个管脚2。In this embodiment, the way to provide a plurality of pins 2 completely independent of each other is to grind the second side of the frame 1 to cut off the electrical connection structure between the pins 2, that is, to cut off a plurality of The connecting part of the pins 2 on the second side of the frame 1 finally forms a plurality of pins 2 that are effectively separated, as shown in FIG. 5. Further, in this embodiment, the polishing is chemical polishing or mechanical polishing, and the interconnected parts of the plurality of pins 2 are removed by chemical polishing or mechanical polishing, so that the plurality of pins 2 2 are completely independent of each other, forming multiple pins 2 that are effectively separated.
由于所述框架1的第一侧是用于设置芯片3、管脚2和连接芯片3与管脚2的引线4等部件的，在最后需要设置塑封体5将所述芯片3、管脚2和引线4同时封装，也即，所述框架1的第一侧可以通过所述塑封体5与空气隔绝，以防止零部件的氧化，因此，在本实施例中，为防止所述框架1的第二侧发生氧化，优选为在步骤S30之后，还包括：Since the first side of the frame 1 is used to set the chip 3, the pin 2 and the lead 4 connecting the chip 3 and the pin 2, at the end, a plastic package 5 needs to be set to connect the chip 3 and the pin 2. It is packaged at the same time with the lead 4, that is, the first side of the frame 1 can be isolated from the air by the plastic encapsulation body 5 to prevent oxidation of parts. Therefore, in this embodiment, in order to prevent the frame 1 from being damaged Oxidation occurs on the second side, preferably after step S30, further comprising:
步骤S40、对所述框架1进行电镀，以在所述框架1的第二侧形成电镀层。Step S40, electroplating the frame 1 to form an electroplating layer on the second side of the frame 1.
如此，通过在所述框架1的第二侧设置电镀层，且所述电镀层对应所述管脚2设置，从而防止所述管脚2发生氧化，影响所述方形扁平无引脚封装结构100的稳定性。In this way, by providing an electroplating layer on the second side of the frame 1, and the electroplating layer is provided corresponding to the pin 2, thereby preventing the pin 2 from being oxidized and affecting the quad flat no-lead package structure 100 The stability.
步骤S50、在所述预封装后的框架1的芯片3基座区设置芯片3；Step S50, setting the chip 3 in the chip 3 base area of the pre-packaged frame 1;
在多个所述管脚2和电镀层设置完毕后，在所述框架1上的芯片3基座区设置芯片3，如图6所示，具体可采用例如粘接等方式，将芯片3固定安装于所述芯片3基座区，所采用的粘接材料可以是例如粘接胶带或粘接树脂等。After the plurality of pins 2 and the electroplating layer are set up, the chip 3 is arranged on the base area of the chip 3 on the frame 1, as shown in FIG. For mounting on the base area of the chip 3, the adhesive material used can be, for example, adhesive tape or adhesive resin.
步骤S60、设置对应连接所述芯片3的外接端子和多个所述管脚2的引线4；Step S60, setting up leads 4 corresponding to the external terminals of the chip 3 and the plurality of pins 2;
在所述芯片3设置完毕后，通过焊接的方式设置引线4，如图7所示，每一引线4对应连接所述芯片3的一外接端口与一所述管脚2，如此，将多个所述管脚2均与所述芯片3电性连接。所述引线4可以是导电金属材质，例如金线、铜线或合金线等等，更优选为金线。After the chip 3 is set up, the leads 4 are arranged by welding. As shown in FIG. 7, each lead 4 is correspondingly connected to an external port of the chip 3 and a pin 2. In this way, a plurality of The pins 2 are electrically connected to the chip 3. The lead 4 may be made of conductive metal material, such as gold wire, copper wire or alloy wire, etc., more preferably gold wire.
步骤S70、对所述框架1进行塑封，形成同时密封所述管脚2、芯片3和引线4的塑封体5，制得方形扁平无引脚封装结构100。In step S70, the frame 1 is plastic-encapsulated to form a plastic-encapsulated body 5 that simultaneously seals the pins 2, the chip 3 and the leads 4, and a square flat no-lead package structure 100 is produced.
在完成所述多个管脚2、芯片3以及引线4的设置后，对所述框架1进行塑封，在所述框架1的第一侧形成同时密封所述管脚2、芯片3和引线4的塑封体5，如图8所示，即制得所述方形扁平无引脚封装结构100。After completing the arrangement of the plurality of pins 2, the chip 3 and the leads 4, the frame 1 is plastic-encapsulated, and the pins 2, the chip 3 and the leads 4 are simultaneously sealed on the first side of the frame 1. As shown in FIG. 8, the plastic package body 5 of, that is, the square flat no-lead package structure 100 is manufactured.
需要说明的是，在图3所示的本实施例中，在所述框架1上设置多个有效分离的管脚2、以及对所述框架1进行电镀形成电镀层的步骤，是在对所述框架1进行塑封的步骤之前实施的，而在本申请的其他实施例中，也可以将所述框架1上设置多个有效分离的管脚2、以及对所述框架1进行电镀形成电镀层的步骤，放在对所述框架1进行塑封的步骤之后进行，也即，先完成对所述框架1的第一侧的所有处理工艺，然后再对所述框架1的第二侧进行处理，同样也能制得如上所述的方形扁平无引脚封装结构100。It should be noted that, in the embodiment shown in FIG. 3, a plurality of effectively separated pins 2 are provided on the frame 1, and the step of electroplating the frame 1 to form an electroplated layer is to The frame 1 is implemented before the step of plastic encapsulation, and in other embodiments of the present application, a plurality of effectively separated pins 2 can also be provided on the frame 1, and the frame 1 is electroplated to form an electroplated layer The step is performed after the step of plastic-sealing the frame 1, that is, all the processing processes on the first side of the frame 1 are completed first, and then the second side of the frame 1 is processed, Similarly, the above-mentioned quad flat no-lead package structure 100 can be manufactured.
通过上述提供的实施例，可以成功制得所述方形扁平无引脚封装结构100，而在实际生产中，为节省工艺，通常是批量加工的，所以，在本实施例中，更优选为所述框架1形成于一基板上，所述基板上设有多个所述框架1，对应地，步骤S70包括：对所述框架1进行塑封，形成同时密封所述管脚2、芯片3和引线4的塑封体5，然后对基板进行切割，制成多个独立的方形扁平无引脚封装结构100。如此，可以通过对同一基板设置的多个所述框架1进行加工，提高了加工效率，其中，所述基板上设的框架1个数不做限定，可以是两个以上的任何数量，在本实施例中，一并参阅图3至图8，以所述基板上设置有两个所述框架1为例进行说明，在完成对塑封处理后，按照图8中所示的虚线对基板进行切割，即可获得多个独立的方形扁平无引脚封装结构100。Through the embodiments provided above, the quad flat no-lead package structure 100 can be successfully manufactured. In actual production, in order to save the process, it is usually processed in batches. Therefore, in this embodiment, it is more preferable to The frame 1 is formed on a substrate, and a plurality of the frames 1 are provided on the substrate. Correspondingly, step S70 includes: plastic-encapsulating the frame 1 to form and simultaneously seal the pins 2, the chip 3 and the leads. 4, and then cut the substrate to form a plurality of independent square flat no-lead package structures 100. In this way, the processing efficiency can be improved by processing multiple frames 1 provided on the same substrate. The number of frames 1 provided on the substrate is not limited, and it can be any number of two or more. In the embodiment, referring to FIGS. 3 to 8 together, two frames 1 are provided on the substrate as an example for description. After the molding process is completed, the substrate is cut according to the dotted line shown in FIG. 8 , A plurality of independent quad flat no-lead package structures 100 can be obtained.
此外，本申请还提出一种电子器件，包括如上所述的方形扁平无引脚封装结构100。可以理解的是，由于所述电子器件包括了所述方形扁平无引脚封装结构100的所有特征，因此也具有由所述方形扁平无引脚封装结构100的所有有益效果，在此不做赘述。In addition, the present application also proposes an electronic device, including the quad flat no-lead package structure 100 as described above. It is understandable that, since the electronic device includes all the features of the quad flat no-lead package structure 100, it also has all the beneficial effects of the quad flat no-lead package structure 100, which will not be repeated here. .
以上仅为本申请的优选实施例，并非因此限制本申请的专利范围，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包括在本申请的专利保护范围内。The above are only preferred embodiments of this application, and do not limit the patent scope of this application. For those skilled in the art, this application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included in the scope of patent protection of this application.

Claims (10)

  1. 一种方形扁平无引脚封装结构，其中，包括：A quad flat no-lead package structure, which includes:
    框架，所述框架具有相对的第一侧和第二侧，所述第一侧设有芯片基座和围设于所述芯片基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，每一所述管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚；A frame, the frame has opposite first and second sides, the first side is provided with a chip base and a plurality of pin setting areas surrounding the outer periphery of the chip base, and a plurality of the pins The setting area is arranged in an inner and outer ring, and each of the pin setting areas is provided with a plurality of pins distributed along the circumference of the pin setting area;
    芯片，设于所述芯片基座；The chip is set on the chip base;
    引线，对应连接所述芯片的外接端子与多个所述管脚；以及，Leads correspondingly connect the external terminals of the chip and a plurality of the pins; and,
    塑封体，设于所述框架上，且同时密封所述管脚、芯片和引线设置。The plastic encapsulation body is arranged on the frame and simultaneously seals the pins, chips and leads.
  2. 如权利要求1所述的方形扁平无引脚封装结构，其中，所述框架的第二侧设有电镀层。The quad flat no-lead package structure of claim 1, wherein the second side of the frame is provided with an electroplating layer.
  3. 一种方形扁平无引脚封装结构的制备方法，其中，包括以下步骤：A method for preparing a square flat no-lead package structure, which includes the following steps:
    提供一框架，所述框架具有相对的第一侧和第二侧，所述框架上形成有开口，以在所述第一侧形成芯片基座区和围设于所述芯片基座外周的多个管脚设置区，多个所述管脚设置区呈内外环设置，每一所述管脚设置区设置有多个沿着所述管脚设置区的周向分布的管脚；A frame is provided, the frame has a first side and a second side opposite to each other, and an opening is formed on the frame to form a chip base area and a plurality of chips surrounding the chip base on the first side. A pin setting area, a plurality of the pin setting areas are arranged in an inner and an outer ring, and each of the pin setting areas is provided with a plurality of pins distributed along the circumference of the pin setting area;
    对所述框架进行预封装，使用树脂填充所述框架上的开口，获得预封装后的框架；Pre-encapsulating the frame, and filling the opening on the frame with resin to obtain a pre-encapsulated frame;
    在所述预封装后的框架的芯片基座区设置芯片；Disposing a chip in the chip base area of the pre-packaged frame;
    设置对应连接所述芯片的外接端子和多个所述管脚的引线；Setting leads corresponding to the external terminals of the chip and the plurality of pins;
    对所述框架进行塑封，形成同时密封所述管脚、芯片和引线的塑封体，制得方形扁平无引脚封装结构。The frame is plastic-encapsulated to form a plastic-encapsulated body that simultaneously seals the pins, chips and leads, and a square flat no-lead package structure is obtained.
  4. 如权利要求3所述的方形扁平无引脚封装结构的制备方法，其中，对所述框架进行预封装，使用树脂填充所述框架上的开口，获得预封装后的框架的步骤之后，还包括：The method for preparing a square flat no-lead package structure according to claim 3, wherein after the step of pre-encapsulating the frame, filling the openings on the frame with resin, and obtaining the pre-encapsulated frame, the method further comprises :
    在所述预封装后的框架的管脚设置区设置多个管脚。A plurality of pins are arranged in the pin setting area of the pre-packaged frame.
  5. 如权利要求4所述的方形扁平无引脚封装结构的制备方法，其中，在所述预封装后的框架的管脚设置区设置多个管脚的步骤，包括：4. The method for manufacturing a quad flat no-lead package structure according to claim 4, wherein the step of arranging a plurality of pins in the pin setting area of the pre-packaged frame comprises:
    对所述框架的第二侧进行研磨，以切断管脚之间的电连接结构，形成有效分离的多个管脚。Grinding the second side of the frame to cut off the electrical connection structure between the pins to form a plurality of pins that are effectively separated.
  6. 如权利要求5所述的方形扁平无引脚封装结构的制备方法，其中，对所述框架的第二侧进行研磨，以切断管脚之间的电连接结构，形成有效分离的多个管脚的步骤中：The method for manufacturing a square flat no-lead package structure according to claim 5, wherein the second side of the frame is ground to cut off the electrical connection structure between the pins to form a plurality of effectively separated pins In the steps:
    所述研磨为化学研磨或机械研磨。The grinding is chemical grinding or mechanical grinding.
  7. 如权利要求4所述的方形扁平无引脚封装结构的制备方法，其中，在所述预封装后的框架的管脚设置区设置多个管脚的步骤之后，还包括：4. The method for manufacturing a quad flat no-lead package structure according to claim 4, wherein after the step of arranging a plurality of pins in the pin setting area of the pre-packaged frame, the method further comprises:
    对所述框架进行电镀，以在所述框架的第二侧形成电镀层。The frame is electroplated to form a plating layer on the second side of the frame.
  8. 如权利要求3所述的方形扁平无引脚封装结构的制备方法，其中，在所述预封装后的框架的芯片基座区设置芯片的步骤中：3. The method for manufacturing a square flat no-lead package structure according to claim 3, wherein, in the step of arranging chips in the chip base area of the pre-packaged frame:
    所述芯片的设置方式为通过粘接固定于所述芯片基座区。The chip is arranged in a manner of being fixed to the chip base area by bonding.
  9. 如权利要求3所述的方形扁平无引脚封装结构的制备方法，其中，所述框架形成于一基板上，所述基板上设有多个所述框架，对应地，对所述框架进行塑封，形成同时密封所述管脚、芯片和引线的塑封体，制得方形扁平无引脚封装结构的步骤包括：The method for manufacturing a square flat no-lead package structure according to claim 3, wherein the frame is formed on a substrate, and a plurality of the frames are provided on the substrate, and correspondingly, the frame is plastic-encapsulated , Forming a plastic package that simultaneously seals the pins, chips and leads, and the steps of fabricating a square flat no-lead package structure include:
    对所述框架进行塑封，形成同时密封所述管脚、芯片和引线的塑封体，然后对基板进行切割，制成多个独立的方形扁平无引脚封装结构。The frame is plastic-encapsulated to form a plastic-encapsulated body that simultaneously seals the pins, chips and leads, and then the substrate is cut to form a plurality of independent square flat no-lead package structures.
  10. 一种电子器件，其中，包括如权利要求1或2所述的方形扁平无引脚封装结构。An electronic device comprising the quad flat no-lead package structure as claimed in claim 1 or 2.
PCT/CN2020/135035 2020-02-19 2020-12-09 Quad flat non-leaded package structure and preparation method therefor, and electronic device WO2021164386A1 (en)

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CN111276461A (en) * 2020-02-19 2020-06-12 青岛歌尔微电子研究院有限公司 Square flat pin-free packaging structure, preparation method thereof and electronic device
CN111653552B (en) * 2020-06-16 2022-06-10 西安科技大学 Square flat chip packaging structure with high electromagnetic pulse interference resistance
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